CN108735603A - Transistor unit and its manufacturing method - Google Patents

Transistor unit and its manufacturing method Download PDF

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Publication number
CN108735603A
CN108735603A CN201710581416.0A CN201710581416A CN108735603A CN 108735603 A CN108735603 A CN 108735603A CN 201710581416 A CN201710581416 A CN 201710581416A CN 108735603 A CN108735603 A CN 108735603A
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China
Prior art keywords
hard mask
interlayer dielectric
metal gates
gate
dielectric
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CN201710581416.0A
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Chinese (zh)
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CN108735603B (en
Inventor
李凱璿
赖柏宇
王圣祯
杨世海
陈燕铭
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

A kind of transistor unit and its manufacturing method.Comprising being formed, metal gates are handled the manufacturing method of transistor unit in the first interlayer dielectric, on metal gates and the first interlayer dielectric, selectivity growth hard mask is on metal gates, and not from the first interlayer dielectric growth hard mask, the second interlayer dielectric of deposition on hard mask and the first interlayer dielectric, planarization the second interlayer dielectric and hard mask, and form gate contact plug and pass through hard mask, with electrical couplings metal gates.

Description

Transistor unit and its manufacturing method
Technical field
This exposure be about a kind of transistor and its manufacturing method, it is extremely hard especially with regard to a kind of sag of transistor Shade and its manufacturing method.
Background technology
In the formation of the metal gates and respective metal contact plunger of fin field-effect transistor, metal gates are usually It inside contracts, and is filled in hard mask to recess due to the recess of metal gates.Then, some parts for removing hard mask, with shape At contact openings, the metal gates of exposure are passed through.Gate contact plug is formed, to be connected to metal gates.
The recess of hard mask leads to the loss of metal gates, therefore need form the metal gates higher than last height, to mend Repay the height lost.The increased height of metal gates leads to the difficulty for the gap filling to form metal gates.Furthermore hard In the etching of shade, the recess of hard mask is perplexed by pattern load effect, and pattern load effect (pattern- Loading effect) cause some parts of metal gates to be inside contracted compared with other metal gates.
Invention content
One aspect of this exposure be a kind of method, be comprising formed metal gates in the first interlayer dielectric, in gold Belong to and handled in grid and the first interlayer dielectric, selectively grow up hard mask on metal gates, and not from the first interlayer Dielectric medium grows up hard mask, the second interlayer dielectric of deposition on hard mask and the first interlayer dielectric, the second interlayer of planarization Dielectric medium and hard mask, and form gate contact plug and pass through hard mask, with electrical couplings metal gates.
Another aspect of this exposure be a kind of method, be comprising formed metal gates in the first interlayer dielectric, it is interior Contract the first interlayer dielectric, so that the top surface of the first interlayer dielectric is hard less than the top surface of metal gates, selectivity growth Shade is on metal gates.Hard mask includes the sidewall sections of the top section and horizontal growth grown up upwards.Method also includes The second interlayer dielectric is deposited on hard mask and the first interlayer dielectric, planarization hard mask, makes the bottom part of hard mask Maintain covering metal gates.It forms gate contact plug and passes through the second interlayer dielectric, with electrical couplings metal gates.
Another aspect of this exposure is a kind of device, is comprising the first interlayer dielectric, has in the first interlayer dielectric The gate stack of metal gates in matter, first comprising the first part overlapped with gate stack and with the first interlayer dielectric The hard mask of the overlapping second part in part.Second interlayer dielectric has the side wall contacted with the side wall of hard mask.The second layer Between dielectric medium and the second part of the first interlayer dielectric it is overlapping.Gate contact plug passes through hard mask, to splice with grid pile It touches.
Description of the drawings
According to following detailed description and attached drawing is coordinated to read, the aspect of this exposure is made to obtain preferable understanding.It should be noted It is that, such as the standard practice of industry, many features are not to be proportionally painted.In fact, in order to carry out understanding discussion, perhaps The size of multiple features can pass through arbitrary scaling.
Fig. 1 to Figure 17 is to be painted to be regarded according to the perspective in intermediate stage of this formation in transistor for disclosing some embodiments Figure and cross section view；
Figure 18 is to be painted the flow chart for forming transistor and contact plunger that some embodiments are disclosed according to this.
Specific implementation mode
It discloses below and many different embodiments or illustration is provided, with the different characteristic to carry out an invention.Composition described below Certain illustrated with arrangement mode is to simplify this exposure.These only serve as illustrating certainly, and purpose be not construed as limiting. For example, fisrt feature is formed in the description above second feature to include fisrt feature and second feature has and directly connect Tactile embodiment also includes that other features are formed between fisrt feature and second feature, so that fisrt feature and the second spy Levy the embodiment not being in direct contact.The size of many features can be painted in varing proportions, so that it simplifies and clear.Except this it Outside, this is disclosed in meeting repeat element symbol and/or letter in various illustrations.This purpose repeated be in order to simplify and clear, and Do not indicate that between the various embodiments discussed and/or configuration there is any relationship.
Furthermore space relativity term, for example, " lower section (underlying) ", " ... under (below) ", " be less than (lower) ", " top (overlying) ", " be higher than (upper) " etc., be for ease of element depicted in description attached drawing or The relationship of feature and other elements or feature.Space relativity term also includes element other than discribed direction in attached drawing Different directions in use or operation.Device can be oriented otherwise and (is rotated by 90 ° or in other directions), and this paper institutes Space relativity description can also so be understood.
Transistor and its manufacturing method are provided according to various illustrative embodiments.It is painted manufacture transistor according to some embodiments Intermediate stage.Some variations of some embodiments are discussed.Through various views and the embodiment of explanation, similar reference number It is for indicating similar element.In the illustrative embodiments being painted, fin field-effect transistor (Fin Field-Effect Transistors, FinFETs) it is to the concrete example as the concept for explaining this exposure.Planar transistor, which can also be used, originally to be taken off The concept of dew.
Fig. 1 to Figure 17 be painted according to this disclose some embodiments the formation in fin field-effect transistor intermediate stage Cross section view and see-through view.Step shown in Fig. 1 to Figure 16 is also in the flow chart 200 shown in Figure 18 with chart formula table It is existing.
Fig. 1 is painted the see-through view of initial structure.Initial structure includes wafer 10, and wherein wafer 10 also includes base material 20. Base material 20 can be semiconductor substrate, can be silicon substrate, SiGe base material or the base material formed by other semi-conducting materials.Base material 20 It can be adulterated by n-type impurity or p-type impurity.Form such as region shallow trench isolation (Shallow Trench Isolation, STI) Area of isolation 22, extended in base material 20 with the top surface from base material 20.Between adjacent shallow trench isolation regions 22 The part of base material 20 is as semiconductor bar 24.According to some illustrative embodiments, the top surface of semiconductor bar 24 and shallow trench every Top surface from region 22 be substantially with each other in sustained height.Some embodiments are disclosed according to this, semiconductor bar 24 is former The part of base material 20, therefore, the material of semiconductor bar 24 are the material identicals with base material 20.Other implementations are disclosed according to this Example, semiconductor bar 24 is the part by being etched in the base material 20 between shallow trench isolation regions 22, to form recess, and is formed Substitution item, and epitaxy is carried out, with other semi-conducting materials of growing up again in recess.Therefore, semiconductor bar 24 be by with base material 20 different semi-conducting materials are formed.According to some illustrative embodiments, semiconductor bar 24 is by SiGe, silicon carbide or III-V Group iii v compound semiconductor material is formed.
Shallow trench isolation regions 22 may include lining oxide layer (figure is not painted), and wherein lining oxide layer can be through base material 20 The thermal oxide of superficial layer is formed by thermal oxide.Lining oxide layer is alternatively silicon oxide layer deposited, is to utilize such as atomic layer Deposit (Atomic Layer Deposition, ALD), high density plasma chemical vapor deposition (High-Density Plasma Chemical Vapor Deposition, HDPCVD) or chemical vapor deposition (Chemical Vapor Depostion, CVD) it is formed.Shallow trench isolation regions 22 can also reside in the dielectric material on lining oxide layer, dielectric Material can be to utilize flow-type chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD), rotation Coating (spin-on coating) or similar fashion are formed.
Referring to Fig. 2, shallow trench isolation regions 22 are to inside contract, so that the top section of semiconductor bar 24 is protruding to higher than shallow The top surface 22A of the remainder of trench isolation regions 22 protrudes fin 24 ' to be formed.Corresponding step is depicted in such as figure Step 202 in flow chart 200 shown in 18.It is etched using dry etch process, wherein Nitrogen trifluoride (NF3) and ammonia (NH3) it is to be used as etching gas.In etch process, plasma can be generated.Also it may include argon gas.It is another according to this exposure A little embodiments carry out inside contracting for shallow trench isolation regions 22 using wet etch process.Etch chemistries may include such as hydrogen fluorine Acid.
Referring to Fig. 3, forming dummy gate stacks 30 on the top surface and side wall of (protrusion) fin 24 '.Corresponding step Suddenly the step 204 being depicted in flow chart 200 as shown in figure 18.Dummy gate stacks 30 and may include dummy gate dielectric medium 32 and the dummy gate electrode 34 on dummy gate dielectric medium.It is formed using such as polysilicon and other workable materials Dummy gate electrode 34.Each dummy gate stacks 30 and also may include one (or a plurality of) on dummy gate electrode 34 Hard mask layer 36.Hard mask layer 36 can by silicon nitride, silicon nitride, carbonitride of silicium or in which multilayer formed.Dummy gate heap Folded 30 may pass through single a or a plurality of protrusion fins 24 ' and/or shallow trench isolation regions 22.Dummy gate, which stacks 30, also to be had Perpendicular to the longitudinal direction of the longitudinal direction of protrusion fin 24 '.
Then, grid gap wall 38 is formed on the side wall that dummy gate stacks 30.Some embodiments, grid are disclosed according to this Clearance between poles wall 38 is to be formed by dielectric material (such as silicon nitride, carbonitride of silicium or the like), and grid gap wall 38 can have There is simple layer structure or includes the multilayered structure of a plurality of dielectric layers.Disclose some embodiments according to this, grid gap wall 38 it In be do not have oxygen atom.
Then, it is etched step (be expressed as source/drain later and inside contract step), not with etching protrusion fin 24 ' The part covered by dummy gate stacking 30 and grid gap wall 38, structure shown in Fig. 4 is made.It can be non-etc. to inside contract step Isotropic etch, therefore, directly the dummy gate of the beneath portions of fin 24 ' stack 30 and grid gap wall 38 be protected and It is not etched.According to some embodiments, the top surface for inside contracting semiconductor bar 24 is less than the top surface of shallow trench isolation regions 22 22A.Therefore, recess 40 is formed between shallow trench isolation regions 22.Recess 40 is the opposite side for being located at dummy gate and stacking 30 On.
Then, epitaxy region (regions and source/drain) 42 be by selective growing semiconductor materials recess 40 in institute It is formed, structure shown in Fig. 5 A is made.Corresponding step is depicted in the step 206 in flow chart 200 as shown in figure 18. According to some illustrative embodiments, epitaxy region 42 includes SiGe or silicon.It is p-type fin field according to manufactured fin field-effect transistor Transistor or N-shaped fin field-effect transistor are imitated, epitaxy is can proceed with, with doped p type impurity in situ or p-type impurity.Citing and Speech, when manufactured fin field-effect transistor is p-type fin field-effect transistor, can grow up SiGe boron (silicon germanium Boron, SiGeB).On the contrary, when manufactured fin field-effect transistor is N-shaped fin field-effect transistor, can grow up phosphatization silicon (silicon phosphorous, SiP) or carbon phosphatization silicon (silicon carbon phosphorous, SiCP).According to originally taking off Reveal other embodiments, epitaxy region 42 be by Group III-V compound semiconductor (such as：GaAs,InP,GaN,InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, it is above-mentioned combination or in which multilayer) formed.It is complete in epitaxy region 42 After filling recess 40, epitaxy region 42 starts flatly to expand, and forms crystal face.
After epitaxy step, epitaxy region 42 can further implant n-type impurity or p-type impurity, to form source electrode and drain electrode Similar number 42 can be used to indicate for region.Other embodiments are disclosed according to this, when epitaxy region 42 is in epitaxy with shape At original position doped p type impurity or p-type impurity when regions and source/drain, then implant step can be omitted.Epitaxy regions and source/drain 42 include lower part and upper part, and lower middle portion is formed in shallow trench isolation regions 22, and upper part be formed in it is shallow On the top surface of trench isolation regions 22.
Fig. 5 B be painted according to this disclose other embodiments regions and source/drain 42 formation.According to these implementations Example, protrusion fin 24 ' shown in Fig. 3 do not inside contract, and epitaxy region 41 is grown up on protrusion fin 24 '.Epitaxy region 41 Material be similar to the material of epitaxy semi-conducting material 42 shown in Fig. 5 A, be depend on manufactured fin field-effect transistor For p-type fin field-effect transistor or N-shaped fin field-effect transistor.Therefore, regions and source/drain 42 include protrusion fin 24 ' and Epitaxy region 41.Implant is carried out, with implant p-type impurity or n-type impurity.
Fig. 6 is to be painted contact etch stop (Contact Etch Stop Layer, CESL) 47 and interlayer dielectric The see-through view of structure after the formation of (Inter-Layer Dielectric, ILD) 46.Corresponding step is depicted in such as Figure 18 Shown in step 208 in flow chart 200.According to some embodiments, contact etch stop 47 can be omitted, and is contacted when being formed Etch stop 47 is formed by silicon nitride, carbonitride of silicium or the like.Some embodiments, contact erosion are disclosed according to this It is not have oxygen to carve the interior of suspension layer 47.Contact etch stop 47 is to utilize conformal deposition method (such as atomic layer deposition or change Learn vapor deposition) it is formed.Interlayer dielectric 46 may include dielectric material, be using such as flow-type chemical vapor deposition, Rotary coating, chemical vapor deposition or other deposition methods are formed.Interlayer dielectric 46 can also be formed by oxygen-containing dielectric material, Wherein oxygen-containing dielectric material can be based on silica tetraethoxysilane (tetraethyl orthosilicate, TEOS) oxide, plasma-assisted chemical vapour deposition (Plasma-Enhanced CVD, PECVD) oxide (SiO2), phosphorus Silica glass (Phospho-Silicate Glass, PSG), Pyrex (Boro-Silicate Glass, BSG), boron doping phosphorus Silica glass (Boron-Doped Phospho-Silicate Glass, BPSG) or the like.Such as chemical machinery can be carried out to grind Grind the planarization step of (Chemical Mechanical Polish, CMP) or mechanical lapping (mechanical grinding) Suddenly, so that the top surface of interlayer dielectric 46, dummy gate stacking 30 and grid gap wall 38 is each other in sustained height.
The cross section view of structure shown in fig. 6 is depicted in Fig. 7, and wherein cross section view is the line A-A from comprising Fig. 6 Vertical plane is obtained.
Then, as can be seen from figures 8 and 9, including hard mask layer 36, dummy gate electrode 34 and dummy gate dielectric medium 32 Dummy gate, which stacks, to be replaced by the substitution gate stack comprising metal gates and substitution gate dielectric.What Fig. 8 and Fig. 9 showed Cross section view and subsequent cross section view are that the vertical plane of the line A-A equally from comprising Fig. 6 is obtained.In cross section view, It is painted the height of the top surface 22A of shallow trench isolation regions 22, and semiconductor fin 24 ' is on top surface 22A.
Hard mask layer as shown in Figure 7 is removed with one or a plurality of etching step first when forming substitution gate stack 36, dummy gate electrode 34 and dummy gate dielectric medium 32, to form irrigation canals and ditches/opening 48 shown in Fig. 8.Corresponding step is to paint The step 210 being shown in flow chart 200 as shown in figure 18.The top surface and side wall for protruding semiconductor fin 24 ' are exposed to Irrigation canals and ditches 48.
Then, referring to Fig. 9, forming (substitution) gate dielectric 52, extended in irrigation canals and ditches 48 (Fig. 8).According to this Some embodiments are disclosed, gate dielectric 52 is comprising the boundary layer (Interfacial Layer, IL) for being considered as lower part 54.Boundary layer 54 is formed on the surface of the exposure of protrusion fin 24 '.Boundary layer 54 may include the oxidation of such as silicon oxide layer Layer is formed through to the protrusion progress of fin 24 ' thermal oxide, chemical oxidation processing procedure or deposition manufacture process.Gate dielectric 52 Also it may include the high k dielectric layer 56 being formed on boundary layer 54.High k dielectric layer 56 includes high-k dielectric material, such as titanium dioxide Hafnium, lanthana, aluminium oxide, zirconium dioxide, silicon nitride or the like.The dielectric constant (k values) of high-k dielectric material is above 3.9, And 7.0 can be higher than.High k dielectric layer 56 is and the accessible boundary layer 54 on boundary layer 54.High k dielectric layer 56 is created as Conforma layer, and extend on the side wall of protrusion fin 24 ' and the side wall of grid gap wall 38.Some embodiments are disclosed according to this, High k dielectric layer 56 is formed using atomic layer deposition or chemical vapor deposition.
Please continue to refer to Fig. 9, stack layer 58 is deposited.Sublayer in stack layer 58 is not painted separately, under realistic situation, Sublayer is distinguishable each other.Deposition is carried out using conformal deposition method (such as atomic layer deposition or chemical vapor deposition), with Make the thickness of vertical component of stack layer 58 (and each sublayer) and the thickness of horizontal component be substantially be equal to each other.It is heavy Long-pending gate dielectric 52 and stack layer 58 extends in irrigation canals and ditches 48 (Fig. 8), and some being included in interlayer dielectric 46 Part.
Stack layer 58 may include diffused barrier layer and (or multiple) work-function layer on diffused barrier layer.Diffusion resistance Barrier layer is formed by titanium nitride (titanium nitride, TiN), wherein titanium nitride can (or can not) adulterated by silicon.Work content The work function of several layers of decision grid, and include at least one layer or be formed by multilayer by different materials.The material of work-function layer is It is N-shaped fin field-effect transistor or p-type fin field-effect transistor to be selected according to corresponding fin field-effect transistor.Citing For, when fin field-effect transistor is N-shaped fin field-effect transistor, work-function layer may include tantalum nitride (TaN) layer and in nitrogen Change titanium aluminium (TiAl) layer on tantalum layer.When fin field-effect transistor is p-type fin field-effect transistor, work-function layer may include nitrogen Change tantalum layer, the titanium nitride layer on tantalum nitride layer and the titanium aluminium layer on titanium nitride layer.After the deposition of work-function layer, resistance is formed Barrier layer can be other titanium nitride layer.
Then, deposited metal material 60, metal material 60 can be to be formed by such as tungsten or cobalt.Metal material 60 is filled out completely Fill remaining irrigation canals and ditches 48 (Fig. 8).In subsequent step shown in Fig. 9, the flat of such as chemical mechanical grinding or mechanical lapping is carried out Change step, to remove the part of the layer 56 in interlayer dielectric 46, layer 58 and layer 60.Therefore, metal gate electrode 62 is formed, It is the remainder comprising layer 58 and layer 60.The remainder of layer 52, layer 58 and layer 60 is being as substitution grid pile later Folded 64.As shown in figure 9, metal gates 62, grid gap wall 38, contact etch stop 47 and interlayer dielectric 46 are at this moment It is substantially coplanar.
Figure 10 to Figure 12 A is the formation for being painted autoregistration hard mask in accordance with some embodiments.The material of interlayer dielectric 46 Material is different from contact etch stop 47, grid gap wall 38 and the material of gate electrode 62.For example, interlayer dielectric 46 can be oxygen-containing dielectric matter, such as oxide, and it is not have to contact etch stop 47, grid gap wall 38 and gate electrode 62 It is aerobic.Therefore, in Figure 10 to Figure 12 A, to interlayer dielectric 46, contact etch stop 47, grid gap wall 38 and grid The surface of electrode 62 is handled, so that the selective deposition of follow-up hard mask is carried out.
Referring to Fig. 10, carrying out pre-treatment, such as can be dilute hydrofluoric acid aqueous solution using acid.Corresponding step is The step 212 being illustrated in flow chart 200 as shown in figure 18.Pre-treatment is indicated using arrow 65 in figure.Pre-treatment Using ammonia (NH3) and Nitrogen trifluoride (NF3) mixed gas carry out.
According to some embodiments, pre-treatment can influence to etch, and be the recess for causing interlayer dielectric 46.Cup depth D1 It can be about 10 nanometers to about 50 nanometers.Therefore, side wall (or the side of grid gap wall 38 of contact etch stop 47 is exposed Wall, if do not form contact etch stop 47).
Then, as shown in figure 11, it is further processed wafer 10, and the bond generated on the surface of interlayer dielectric 46 (in preceding processing) is to be terminated, to generate inhibition layer 63.Corresponding step is depicted in flow chart 200 as shown in figure 18 Step 214.For example, it can be handled, so as to generate some hydrophobicitys bond with oxygen atom in interlayer dielectric 46. According to some embodiments, the bond for being connected to oxygen atom may include Si (CH3)3.The correspondence processing procedure of connection bond may include silanization (silylation) processing procedure, wherein corresponding process gas may include bis- (trimethyl silicon substrate) amine [bis (trimethylsilyl) Amine], hexamethyldisilazane (hexamethyldisilazane, HMDS), tetramethyl-disilazane (tetramethyldisilazane, TMDS), trim,ethylchlorosilane (trimethylchlorosilane, TMCS), dimethyl Dichlorosilane (dimethyldichlorosilane, DMDCS), methyl trichlorosilane (methyltrichlorosilane, MTCS) or the like.According to other embodiment, because the material of interlayer dielectric 46 is and contact etch stop 47, grid The material of clearance wall 38 and gate electrode 62 is different, and alternative deposition of organic thin film (also referred to as film 63) is situated between in interlayer On the surface of electric matter 46, but not on the exposed surface of contact etch stop 47, grid gap wall 38 and gate electrode 62.Cause This, either through bond or throughout curve deposition is terminated, the property on the surface of interlayer dielectric 46 is to be transformed into and contact The property of etch stop 47, grid gap wall 38 and gate electrode 62 is different.
Then, as illustrated in fig. 12, selective deposition autoregistration hard mask 66 is on substitution gate stack 64.Corresponding step Suddenly the step 216 being depicted in flow chart 200 as shown in figure 18.Hard mask 66 is as autoregistration hard mask, due to it It is the position of autoregistration extremely contact etch stop 47, grid gap wall 38 and gate electrode 62.Hard mask 66 is by dielectric material Material (such as silicon nitride, carbonitride of silicium or the like) is formed.In deposition, since the surface of interlayer dielectric 46 has been changed Become, it is difficult to it is nucleated on the surface of interlayer dielectric 46, thus hard mask 66 is will not to be initially formed from interlayer dielectric 46.Separately Outside, deposition hard mask 66 is on the surface of contact etch stop 47, grid gap wall 38 and gate electrode 62.Directly in grid The mainly growth upwards of the part of hard mask 66 on electrode 62, and from contact etch stop 47 (or grid gap wall 38, if Contact etch stop 47 is not formed) the part of hard mask 66 of side wall growth mainly flatly grow up.
In gate dielectric 56 containing in aerobic embodiment, according to the composition of gate dielectric 56, hard mask 66 can or can Do not grow up from the top surface of gate dielectric 56.However, since gate dielectric 56 is thin, and the exposure of gate dielectric 56 Surface is narrow, even if hard mask 66 is not fine from 56 place of growing up of gate dielectric, from gate electrode 62 and grid gap wall 38 The part of the hard mask 66 of growth can be bonded to each other, to form main body hard mask 66.According to some embodiments, hole (do not paint by figure Show) can (or can not) it is formed on region 67A and/or region 67B, since the growth in these regions is bad, and according to some examples Show that embodiment, hole can cause hard mask 66 to be slightly physically separated with interlayer dielectric 46 and/or gate dielectric 56.
Figure 12 B are the see-through views for being painted wafer 10 as illustrated in fig. 12.Figure 12 B are to be painted hard mask 66 to form covering Gate electrode 62, grid gap wall 38 and the strip for contacting etch stop 47.As illustrated in fig. 12,66 sideways diffusion of hard mask To the external margin for contacting etch stop 47 is exceeded, hard mask 66 can have width W2 be greater than distance W1, middle-range whereby It is between the external margin of the adjacent vertical component of contact etch stop 47 from W1.Hard mask 66 also has circular (arcuation) side wall and top surface.According to some embodiments of this exposure, the thickness T1 of hard mask 66 is greater than about 10 nanometers, and The range of thickness T1 is between being about 10 nanometers to about 100 nanometers.
It after the formation of hard mask 66, is post-processed, to optimize the film quality of hard mask 66.It is real according to some illustrations Example is applied, through rapid thermal annealing (Rapid Thermal Anneal, RTA) of the temperature between about 800 DEG C and about 1200 DEG C It is post-processed.It according to other embodiments, is post-processed through plasma treatment, wherein the process gas of plasma treatment It includes such as nitrogen, hydrogen, argon gas, helium and/or analog to be.Post-processing is to remove the suspension key of hard mask 66 (dangling bond) becomes less hole and compared with can resist subsequent manufacturing process for cleaning.
According to the method for post-processing and the composition of inhibition film 63, post-processing may or may not lead to the removal for inhibiting film 63.If Inhibit film 63 not to be removed because of post-processing, after the formation of hard mask 66, and before or after post-processing, carries out volume Outer processing procedure inhibits film 63 to remove, makes the deposition above interlayer dielectric that can carry out.According to some embodiments, etching It is removed in gas or etching solution and inhibits film 63, depend on the type for inhibiting film.According to other embodiments, moved using plasma There can be slight collision effect except film, wherein plasma is inhibited.
Then, as shown in figure 13, interlayer dielectric 68 is formed.Corresponding step is depicted in flow chart as shown in figure 18 Step 218 in 200.The material for forming interlayer dielectric 68 is the mutually of the same clan of the candidate material selected from interlayer dielectric 46 Group, and the material of interlayer dielectric 68 can be with the material identical or difference of interlayer dielectric 46.The top that interlayer dielectric 68 has Surface is above the top surface of hard mask 66, so that hard mask 66 is in embedment interlayer dielectric 68.In interlayer dielectric 46 and It can be with or without visual interface between interlayer dielectric 68.
Figure 14 A and Figure 14 B be painted the cross section view after planarisation steps of wafer 10 and see-through view respectively, wherein Planarisation step can be carried out using chemical mechanical grinding or mechanical lapping.Figure 14 B are be painted wafer 10 shown in figure 14 A saturating Depending on view.Corresponding step is depicted in the step 220 in flow chart 200 as shown in figure 18.It is hard to hide because of planarisation step The top surface of cover 66 is flattened, and the top surface of hard mask 66 is coplanar with the top surface of interlayer dielectric 68.It is surplus Under hard mask 66 still there is the curved surface sidewall that is contacted with interlayer dielectric 68.
After planarization, additional post-processing can be carried out, with the film quality of more optimized hard mask 66.Additional post-processing There is similar function with the previous post-processing carried out before the formation of interlayer dielectric 68, and can be removed due to planarization And the suspension key that newly exposes of hard mask 66 of exposure, and more make hard mask 66 become less hole and compared with can resist it is subsequent clearly Wash processing procedure.The method for carrying out additional post-processing is selected from the mutually of the same clan of the candidate material and method previously processed with progress Group.
Figure 15 to Figure 17 is the formation for being painted source/drain contact plunger and gate contact plug.It is real in the illustration being painted It applies in example, show three regions and source/drains 42, and the processing procedure being painted is one source/drain contact plunger connection of display To the formation of leftmost regions and source/drain 42.In real processing procedure, source/drain contact plunger is also formed, to be connected to The regions and source/drain 42 of center and rightmost.However, these source/drain plugs are formed in the Different Plane being painted, And it is not shown in the plane being painted.Similarly, although a gate contact plug is depicted as being formed directly on the right side of attached drawing Substitution gate stack 64 on, can also form gate contact plug directly on the gate stack on the left side 64, and be painted Different Plane, and figure is not painted.
Figure 15 be painted source/drain suicide areas domain 70, metal layer 72, conductive barrier layer 74 and metallic region 76 shape At.Corresponding step is depicted in the step 222 in flow chart 200 as shown in figure 18.According to some embodiments, metal layer 72 (such as titanium coating) is to be deposited as blanket layer, and nitridation process is then carried out on the top section of metal layer 72, to form gold Belong to nitride layer (such as 74).The bottom part of metal layer 72 is not nitrogenized.Then, annealed (can be that fast speed heat is moved back Fire) so that metal layer 72 is reacted with the top section of regions and source/drain 42, to form silicide regions 70.In interlayer dielectric The part of metal layer 72 on the side wall of matter 46 does not react.Then, the metal nitride layer 74 being previously formed can be left, with As the conductive barrier layer 74 being painted, or the metal nitride layer 74 being previously formed is removed, followed by the new nitride metal of deposition Nitride layer (such as titanium nitride, also referential data 74 is utilized to indicate), and it is that more removed metal nitride layer is thin.Then, shape It is for example then, to be planarized by filling tungsten, cobalt or the like at metallic region 76, to remove extra material, Lower source/drain contact plunger 78 is made.
6 are please referred to Fig.1, according to some embodiments of this exposure, forms etch stop 80.According to some embodiments, erosion It is by silicon nitride (SiN), carbonitride of silicium (SiCN), silicon carbide (SiC), nitrogen silicon oxide carbide (SiOCN) or other Jie to carve suspension layer Electric material is formed.The thickness of etch stop 80 may range from about 2 nanometers to about 4 nanometers.Forming method may include etc. from Sub- assistant chemical vapor deposition, atomic layer deposition, chemical vapor deposition or the like.Then, interlayer dielectric 82 is formed to exist In etch stop 80.The material of interlayer dielectric 82 is to can be selected from and form interlayer dielectric 46 and 68 phase of interlayer dielectric Same candidate material (and method), and interlayer dielectric 46, interlayer dielectric 68 and interlayer dielectric 82 are by identical or different Dielectric material formed.According to some embodiments, interlayer dielectric 82 is using plasma-assisted chemical vapour deposition, flowing Formula chemical vapor deposition, rotary coating or the like are formed, and may include silica (SiO2).The thickness of interlayer dielectric 82 The range of degree is between aboutPeace treatyBetween.
Interlayer dielectric 82 and etch stop 80 are etched, to form opening 83 and opening 84.Using for example reactive Ion(ic) etching (Reactive Ion Etch, RIE) is etched.In subsequent step, as shown in figure 17, plug/interlayer is formed Window 86 and plug/interlayer hole 88.Corresponding step is depicted in the step 224 in flow chart 200 as shown in figure 18.According to this Some embodiments disclosed, plug/interlayer hole 86 and plug/interlayer hole 88 include barrier layer 90 and contain gold on barrier layer 90 Belong to material 92.According to some embodiments of this exposure, the formation of plug/interlayer hole 86 and plug/interlayer hole 88 includes to form blanket Cover barrier layer 90 and cover the metal-containing material 92 on barrier layer 90 in blanket, and planarized, with remove blanket cover barrier layer 90 and The redundance of metal-containing material 92.Barrier layer 90 can be formed by metal nitride (such as titanium nitride or tantalum nitride).Containing gold Belonging to material 92 can be formed by tungsten, cobalt, copper or the like.
In final fin field-effect transistor 100, gate contact plug 88 passes through corresponding hard mask, remaining hard mask 66 have the part in the opposite side of gate contact plug 88.Hard mask 66 is extended laterally to more than corresponding substitution grid 64 And contact etch stop 47, and with curved surface (or can be circular) side wall contacted with interlayer dielectric 68.
The embodiment of this exposure has the feature of some advantages.By using selective deposition on metal gates, rather than Within the mode of receding metal grid form hard mask, be subsequently formed hard mask in recess, metal gates are not necessary in interior contraction journey Shi Kaoliang height loss, and can not have to form higher height.Therefore, hole, which is filled in the formation of metal gates, becomes relatively to hold Easily.Also the pattern load effect that metal gates inside contract can be reduced, wherein pattern load effect is that final metal gates is caused to have Different height.
According to some embodiments of this exposure, a kind of method include formed metal gates in the first interlayer dielectric, It handled on metal gates and the first interlayer dielectric, selectively grow up hard mask on metal gates, and not from first layer Between dielectric medium growth hard mask, deposition the second interlayer dielectric on hard mask and the first interlayer dielectric, planarization the second layer Between dielectric medium and hard mask, and formed gate contact plug pass through hard mask, with electrical couplings metal gates.
In one embodiment, grid gap wall is to contact the vertical component of etch stop on the side wall of metal gates It is hard mask of growing up again on the side wall of grid gap wall, and certainly in the side wall of the vertical component of contact etch stop.
In one embodiment, hard mask is grown into curved surface sidewall and curved surface top surface.
In one embodiment, above-mentioned processing is comprising with low-kappa number metal gates and the first interlayer dielectric and shape At film is inhibited on the exposed surface of the first interlayer dielectric, inhibit film on metal gates without being formed.
In one embodiment, after the above method is also included in the operation of selectivity growth hard mask, after being carried out to hard mask Processing.
In one embodiment, post-processing includes thermal annealing.
In one embodiment, after planarizing the operation of the second interlayer dielectric and hard mask, hard mask is carried out additional Post-processing.
According to some embodiments of this exposure, a kind of method include formed metal gates in the first interlayer dielectric, it is interior Contract the first interlayer dielectric, so that the top surface of the first interlayer dielectric is hard less than the top surface of metal gates, selectivity growth Shade is on metal gates.Hard mask includes the sidewall sections of the top section and horizontal growth grown up upwards.Method also includes The second interlayer dielectric is deposited on hard mask and the first interlayer dielectric, planarization hard mask, makes the bottom part of hard mask Maintain covering metal gates.It forms gate contact plug and passes through the second interlayer dielectric, with electrical couplings metal gates.
In one embodiment, gate contact plug also extends through hard mask, and hard mask includes still in gate contact plug Part on side.
In one embodiment, grid gap wall is grown up on the side wall of metal gates, and from the side wall of grid gap wall The sidewall sections of hard mask.
In one embodiment, hard mask is grown into curved surface sidewall and curved surface top surface.
In one embodiment, the above method also includes with low-kappa number metal gates and the first interlayer dielectric and shape At film is inhibited on the top surface of the first interlayer dielectric, inhibit film on metal gates without being formed.
In one embodiment, after the selectively operation of growth hard mask, hard mask is post-processed.
In one embodiment, post-processing includes thermal annealing.
In one embodiment, post-processing includes plasma treatment.
According to some embodiments of this exposure, a kind of device includes the first interlayer dielectric, has in the first interlayer dielectric The gate stack of metal gates in matter, first comprising the first part overlapped with gate stack and with the first interlayer dielectric The hard mask of the overlapping second part in part.Second interlayer dielectric has the side wall contacted with the side wall of hard mask.The second layer Between dielectric medium and the second part of the first interlayer dielectric it is overlapping.Gate contact plug be across hard mask, with gate stack Contact.
In one embodiment, the side wall of hard mask is curved surface.
In one embodiment, gate stack includes gate dielectric, and gate dielectric includes vertical component, and device also wraps Containing hole, hole is at the top of the vertical component of gate dielectric.
In one embodiment, the top surface of the first interlayer dielectric is less than the top surface of gate stack, and hard mask Second part is less than the top surface of gate stack.
In one embodiment, above-mentioned apparatus also includes contact etch stop, and contact etch stop includes and first layer Between dielectric medium overlapping bottom part and the vertical component that is contacted with side wall and with the first interlayer dielectric, wherein hard mask The side wall of vertical component of the second part also with contact etch stop contact.
The feature of the above-mentioned many embodiments of abstract, therefore one skilled in the art can know more about the state of this exposure Sample.One skilled in the art should be understood that using can design or modify other processing procedures and structure based on this exposure with reality Now purpose identical with the embodiment and/or reach identical advantage.One skilled in the art is it will also be appreciated that same with this Deng framework without departing from the spirit and scope of this exposure, and can be made under the spirit and scope without departing from this exposure each Kind variation exchanges and replaces.

Claims (10)

1. a kind of manufacturing method of transistor unit, which is characterized in that include：
A metal gates are formed in one first interlayer dielectric；
A processing is carried out on the metal gates and first interlayer dielectric；
Selectivity one hard mask of growth is not grown up the hard mask on the metal gates from first interlayer dielectric；
One second interlayer dielectric is deposited on the hard mask and first interlayer dielectric；
Planarize second interlayer dielectric and the hard mask；And
A gate contact plug is formed, wherein the gate contact plug passes through the hard mask, with the electrical couplings metal gates.
2. the manufacturing method of transistor unit according to claim 1, which is characterized in that a grid gap wall is in the gold Belong to grid one side wall on, one contact etch stop a vertical component be in the one side wall of the grid gap wall, and from Grow up again in the one side wall of the vertical component of the contact etch stop hard mask, which grown into a song Surface side wall and a curved surface top surface.
3. the manufacturing method of transistor unit according to claim 1, which is characterized in that the processing includes：
With the low-kappa number metal gates and first interlayer dielectric；And
Forming one inhibits film on an exposed surface of first interlayer dielectric, without forming the inhibition film in the metal gates On.
4. the manufacturing method of transistor unit according to claim 1, which is characterized in that also include,
The selection grow up the hard mask operation after, to the hard mask carry out one post-processing；And
After the operation of the planarization second interlayer dielectric and the hard mask, an additionally post-processing is carried out to the hard mask.
5. a kind of manufacturing method of transistor unit, which is characterized in that it is characterized in that, comprising：
A metal gates are formed in one first interlayer dielectric；
First interlayer dielectric is inside contracted, so that a top table of the top surface of first interlayer dielectric less than the metal gates Face；
Selectivity one hard mask of growth is on the metal gates, and wherein the hard mask includes the top section grown up upwards, and The side wall part of horizontal growth；
One second interlayer dielectric is deposited on the hard mask and first interlayer dielectric；
The hard mask is planarized, a bottom part of the hard mask is made still to cover the metal gates；And
It forms a gate contact plug and passes through second interlayer dielectric, with the electrical couplings metal gates.
6. the manufacturing method of transistor unit according to claim 5, which is characterized in that the gate contact plug also extends through The hard mask, and the hard mask includes the part still on the side of the gate contact plug.
7. the manufacturing method of transistor unit according to claim 5, which is characterized in that also include, the selection at After the operation of the long hard mask, a post-processing is carried out to the hard mask, and the post-processing includes at a thermal annealing or a plasma Reason.
8. a kind of transistor unit, which is characterized in that include：
One first interlayer dielectric；
One gate stack, the metal gates being included in first interlayer dielectric；
One hard mask, including the first part overlapped with the gate stack, and one first with first interlayer dielectric Divide an overlapping second part；
One second interlayer dielectric has one side wall, which contacts with the one side wall of the hard mask, and second interlayer dielectric One second part of matter and first interlayer dielectric is overlapping；And
One gate contact plug passes through the hard mask, to contact the gate stack.
9. transistor unit according to claim 8, which is characterized in that the gate stack includes a gate dielectric, should Gate dielectric includes a vertical component, which also includes a hole, the vertical component of the hole in the gate dielectric A top, a top surface of first interlayer dielectric is less than a top surface of the gate stack, the hard mask this Two parts are less than the top surface of the gate stack, and the side wall of the hard mask is curved surface.
10. transistor unit according to claim 8, which is characterized in that also include a contact etch stop, the contact Etch stop include with first interlayer dielectric overlap a bottom part and with one side wall and with first interlayer Dielectric medium contact a vertical component, wherein the second part of the hard mask also with the vertical component effect of the contact etch stop The side wall contact divided.
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