CN106847697A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN106847697A CN106847697A CN201510894481.XA CN201510894481A CN106847697A CN 106847697 A CN106847697 A CN 106847697A CN 201510894481 A CN201510894481 A CN 201510894481A CN 106847697 A CN106847697 A CN 106847697A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of fin formula field effect transistor, including：Offer includes the substrate of first area and second area, and substrate surface has fin and the first separation layer, top surface of first insulation surface less than fin；The first doped layer, top surface of the first doping layer surface less than fin are formed in the first insulation surface；The first barrier layer is formed in the side wall and top surface of the first doping layer surface and fin；Removal exposes the part fin side wall of second area positioned at the barrier layer of part first of the doping layer surface of second area first and the first doped layer of second area；The fin sidewall surfaces for being exposed in second area afterwards form the second doped layer；Carry out annealing process；The first doped layer, the first barrier layer and the second doped layer are removed afterwards；Afterwards the second separation layer, top surface of second insulation surface less than fin are formed in the first insulation surface.The fin formula field effect transistor performance improvement of formation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of shape of fin formula field effect transistor
Into method.
Background technology
With developing rapidly for semiconductor fabrication, semiconductor devices towards component density higher, with
And the direction of integrated level higher is developed.Transistor is just extensive at present as most basic semiconductor devices
Using, thus the component density and integrated level with semiconductor devices raising, the grid of planar transistor
Size is also shorter and shorter, and traditional planar transistor dies down to the control ability of channel current, produces short ditch
Channel effect, produces leakage current, the electric property of final influence semiconductor devices.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes fin effect
Transistor (Fin FET) is answered, fin formula field effect transistor is a kind of common multi-gate device.Fin effect
Answering the structure of transistor includes：Positioned at the fin and dielectric layer of semiconductor substrate surface, the dielectric layer covers
The side wall of fin described in cover, and dielectric layer surface is less than fin top；Positioned at dielectric layer surface, with
And top and the grid structure of sidewall surfaces of fin；Source in the fin of the grid structure both sides
Area and drain region.
However, as the size of semiconductor devices constantly reduces, the manufacturing process of fin formula field effect transistor
It is challenged, it is difficult to ensure the stable performance of fin formula field effect transistor.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of fin formula field effect transistor, is formed
Fin formula field effect transistor performance improvement.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
Substrate is provided, the substrate includes first area and second area, the first area of the substrate and second
Region surface has fin respectively, and the substrate surface has the first separation layer, and first separation layer covers
The side wall of cover fin, and first insulation surface is less than the top surface of the fin；Institute
State the first insulation surface formed the first doped layer, the side wall of the first doped layer covering part fin,
And the first doping layer surface is less than the top surface of the fin, have the in first doped layer
One types of ion；First is formed in the side wall and top surface of the described first doping layer surface and fin to hinder
Barrier；Removal is positioned at part first barrier layer of the doping layer surface of second area first and second area
First doped layer, retains positioned at the barrier layer of part first of second area fin sidewall surfaces, and expose
The part fin side wall of second area；In the barrier layer of part first of removal second area and the first doped layer
Afterwards, the fin sidewall surfaces for being exposed in second area form the second doped layer, second doped layer
It is interior with Second Type ion；Annealing process is carried out, drives the first kind ion in the first doped layer to expand
Spill into the fin of first area, drive the Second Type ion in the second doped layer to diffuse into second area
Fin in；After the annealing process, the first doped layer of removal, the first barrier layer and the second doping
Layer；After the first doped layer, the first barrier layer and the second doped layer is removed, in first separation layer
Surface formed the second separation layer, the side wall of the second separation layer covering part fin, and described second every
Top surface of the absciss layer surface less than the fin.
Optionally, the forming step of first doped layer includes：In first insulation surface and
The side wall and top surface of fin form the first doping；Planarize first doping；In planarization
Afterwards, it is etched back to first doping untill the side wall and top surface for exposing fin.
Optionally, removal is positioned at the barrier layer of part first and second of the doping layer surface of second area first
The step of first doped layer in region, includes：The first barrier layer surface in first area forms patterned layer；
With the patterned layer as mask, first barrier layer is etched using anisotropic dry etch process,
Untill the first doping layer surface for exposing second area；After first barrier layer is etched,
First doped layer is etched using isotropic etching technics, until exposing the first of second area
Untill the part fin sidewall surfaces of insulation surface and second area.
Optionally, the forming step of second doped layer includes：In first barrier layer surface,
The fin that the sidewall surfaces of one doped layer, the first insulation surface of second area, second area expose
Side wall and top surface form the second doping；Second doping is etched back to until exposing the secondth area
Untill first insulation surface in domain.
Optionally, the forming step of first separation layer includes：In the substrate surface and fin
Side wall and top surface form the first barrier film；Planarize first barrier film；After planarization,
First barrier film is etched back to untill the side wall and top surface for exposing fin.
Optionally, the formation process of first barrier film is fluid chemistry gas-phase deposition.
Optionally, also include：Before first separation layer is formed, in the substrate surface and fin
The side wall and top surface in portion form boundary layer；First separation layer is formed at the interface layer surfaces；
After the first doped layer of removal second area, the boundary layer that removal fin sidewall surfaces expose.
Optionally, the material of the boundary layer is silica.
Optionally, also include：The second doping layer surface forms the second barrier layer.
Optionally, the forming step of second separation layer includes：In first insulation surface and
The side wall and top surface of fin form the second barrier film；Planarize second barrier film；In planarization
Afterwards, it is etched back to second barrier film untill the side wall and top surface for exposing fin.
Optionally, the formation process of second barrier film is high density plasma CVD work
Skill.
Optionally, the top surface of the fin also has mask layer.
Optionally, after first doped layer, the first barrier layer and the second doped layer is removed, removal
The mask layer.
Optionally, the first kind ion is p-type ion；The Second Type ion is N-type ion.
Optionally, the material of first doped layer is Pyrex；The material of second doped layer is
Phosphorosilicate glass.
Optionally, the first kind ion is N-type ion；The Second Type ion is p-type ion.
Optionally, the material of first doped layer is phosphorosilicate glass；The material of second doped layer is
Pyrex.
Optionally, the annealing process is rapid thermal annealing；The temperature of the annealing process is 1000 DEG C
~1100 DEG C, annealing time is 1 second~5 seconds.
Optionally, having in the substrate of the first area in the first well region, first well region has the
One types of ion；Having in the substrate of the second area in the second well region, second well region has the
Two types of ion.
Optionally, also include：After the first doped layer, the first barrier layer and the second doped layer is removed,
The grid structure of the fin is developed across, the grid structure covers partial sidewall and the top of the fin
Portion surface；Source region and drain region are formed in the fin of the grid structure both sides.
Compared with prior art, technical scheme has advantages below：
In forming method of the invention, the first doped layer covering part fin of the first insulation surface is formed at
The side wall in portion, first doped layer is used not only for mixing the part fin side wall of first area
Miscellaneous and form anti-reach through region, first doped layer can also be in second area as sacrifice layer；In removal
After first doped layer of second area, part fin of the second area higher than the first separation layer can be exposed
Portion side wall so that the fin sidewall surfaces that the second doped layer for being formed can expose positioned at second area.
By annealing process, the first kind ion in the first doped layer can spread in the fin being in contact,
Second Type ion in second doped layer can spread in the fin being in contact such that it is able to exist respectively
The first area anti-reach through region different with formation Doped ions in the fin of second area.Firstly, since
Before forming the first doped layer, the first separation layer is formed in substrate surface, in annealing process, first mixes
The Second Type ion in first kind ion and the second doped layer in diamicton will not expand in substrate
Dissipate, be conducive to making boundary line between the well region in the well region and second area substrate in the substrate of first area
It is more clearly demarcated, it is to avoid because the diffusion of first kind ion or Second Type ion and caused by first area and
There is the problem of break-through in second area substrate between well region.Secondly as directly with the described first doping
Layer as second area sacrifice layer, and, it is only necessary to carry out a patterning process to remove second area
The first doped layer, the number of times of patterning process can be reduced, advantageously reduce processing step, save into
This.Again, before the second separation layer is formed, i.e., the fin by annealing in first area and second area
Anti- reach through region is formed in portion respectively, and removes first doped layer, the first barrier layer and the second doped layer,
The distance between adjacent fin can be expanded, groove depth-to-width ratio reduces between making adjacent fin, described second
The material of separation layer is more easy to be filled in the groove, advantageously forms the second separation layer of dense uniform.
Therefore, the performance improvement of the fin formula field effect transistor for being formed.
Brief description of the drawings
Fig. 1 to Fig. 4 is a kind of cross-sectional view of the forming process of semiconductor structure；
Fig. 5 to Figure 13 is the cross-section structure of the forming process of the fin formula field effect transistor of the embodiment of the present invention
Schematic diagram.
Specific embodiment
As stated in the Background Art, as the size of semiconductor devices constantly reduces, fin formula field effect transistor
Manufacturing process it is challenged, it is difficult to ensure the stable performance of fin formula field effect transistor.
Found by research, constantly reduced with for forming the fin size of fin formula field effect transistor,
The source region and drain region bottom being formed in fin are susceptible to bottom break-through (punch through) phenomenon, i.e.,
There is break-through between the source region and the bottom in drain region, leakage current is produced in the bottom in the source region and drain region.
In order to overcome the bottom punch through, a kind of method is that anti-break-through injection is carried out in fin, described
Transoid ion is injected in region between source region and drain region bottom, to isolate source region and drain region bottom.However,
Due in larger distance at the top of source region and drain region bottom to fin, then the depth of the anti-break-through injection also compared with
Greatly so that the anti-break-through injection easily causes implant damage to fin portion surface and inside, can still reduce
The performance of fin formula field effect transistor.
For the implant damage problem for overcoming above-mentioned anti-break-through injection to cause, Fig. 1 to Fig. 4 is that one kind is partly led
The cross-sectional view of the forming process of body structure.
Refer to Fig. 1, there is provided substrate 100, the surface of the substrate 100 has fin 101, the substrate
100 and the surface of fin 101 there is doping 102, there are Doped ions in the doping 102.
Fig. 2 is refer to, deielectric-coating 103 is formed on the surface of the doping 102.
Fig. 3 is refer to, the deielectric-coating 103 (as shown in Figure 2) is etched back to form dielectric layer 103a,
Top surface of the dielectric layer 103a surfaces less than the fin 101.
Fig. 4 is refer to, removal is higher than the doping 102 (as shown in Figure 3) on dielectric layer 103a surfaces, shape
Into doped layer 102a；Annealing process is carried out, the Doped ions in doped layer 102a is diffused into fin 101
It is interior.
However, as the density of semiconductor devices is improved so that the groove dimensions between adjacent fin 101
It is corresponding to reduce, accordingly increase the groove depth-to-width ratio between adjacent fin 101.Due to the substrate 100
Deielectric-coating 103 is re-formed after forming doping with the surface of fin 101, then the meeting of doping 102 for being formed
Further increase the depth-to-width ratio of groove, cause subsequently to be difficult to fill the deielectric-coating of dense uniform in groove
103.Secondly as the groove depth-to-width ratio between the adjacent fin 101 of the fin is larger, easily make described
Doping 102 itself is the sidewall surfaces for being difficult to closely fit in the surface of substrate 100 and fin 101,
Especially the corner on the side wall of fin 101 and the surface of substrate 100 is difficult to be brought into close contact doping 102.
In order to solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, bag
Include：There is provided substrate, the substrate include first area and second area, the first area of the substrate and
Second area surface has fin respectively, and the substrate surface has the first separation layer, first isolation
The side wall of layer covering part fin, and first insulation surface is less than the top surface of the fin；
The first doped layer, the side of the first doped layer covering part fin are formed in first insulation surface
Wall, and the first doping layer surface is less than the top surface of the fin, tool in first doped layer
There is first kind ion；The is formed in the side wall and top surface of the described first doping layer surface and fin
One barrier layer；Removal is positioned at the barrier layer of part first and the secondth area of the doping layer surface of second area first
First doped layer in domain, retains positioned at the barrier layer of part first of second area fin sidewall surfaces, and cruelly
Expose the part fin side wall of second area；Mixed on the barrier layer of part first and first of removal second area
After diamicton, the fin sidewall surfaces exposed in second area form the second doped layer, and described second mixes
There is Second Type ion in diamicton；Carry out annealing process, drive the first kind in the first doped layer from
Son is diffused into the fin of first area, drives the Second Type ion in the second doped layer to diffuse into second
In the fin in region；After the annealing process, the first doped layer of removal, the first barrier layer and second
Doped layer；After the first doped layer, the first barrier layer and the second doped layer is removed, described first every
Absciss layer surface forms the second separation layer, the side wall of the second separation layer covering part fin, and described the
Top surface of two insulation surfaces less than the fin.
Wherein, the side wall of the first doped layer covering part fin of the first insulation surface is formed at, it is described
First doped layer is used not only for that the part fin side wall of first area is doped and forms anti-break-through
Area, first doped layer can also be in second area as sacrifice layer；The first of removal second area
After doped layer, part fin side wall of the second area higher than the first separation layer can be exposed so that institute
The fin sidewall surfaces that the second doped layer for being formed can expose positioned at second area.By annealing process,
First kind ion in first doped layer can spread in the fin being in contact, in the second doped layer
Second Type ion can spread in the fin being in contact such that it is able to respectively in first area and second
The different anti-reach through region of Doped ions is formed in the fin in region.Firstly, since forming the first doped layer
Before, the first separation layer, in annealing process, the first kind in the first doped layer are formed in substrate surface
Second Type ion in type ion and the second doped layer will not spread in substrate, be conducive to making position
Boundary line is more clearly demarcated between the well region in the well region in the substrate of first area and second area substrate, it is to avoid
Because of the diffusion of first kind ion or Second Type ion and caused by first area and second area substrate
There is the problem of break-through between well region.Secondly as directly using first doped layer as second area
Sacrifice layer, and, it is only necessary to carry out a patterning process to remove the first doped layer of second area,
The number of times of patterning process can be reduced, processing step, cost-effective is advantageously reduced.Again, in shape
Into before the second separation layer, i.e., form anti-respectively in the fin of first area and second area by annealing
Reach through region, and first doped layer, the first barrier layer and the second doped layer are removed, can expand adjacent
The distance between fin, groove depth-to-width ratio reduces between making adjacent fin, the material of second separation layer
It is more easy to be filled in the groove, advantageously forms the second separation layer of dense uniform.Therefore, formed
Fin formula field effect transistor performance improvement.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 5 to Figure 13 is the cross-section structure of the forming process of the fin formula field effect transistor of the embodiment of the present invention
Schematic diagram.
Refer to Fig. 5, there is provided substrate 200, the substrate 200 includes first area 210 and second area
220, the first area 210 and the surface of second area 220 of the substrate 200 have fin 201 respectively,
The surface of the substrate 200 has the first separation layer 202, the covering part fin of first separation layer 202
201 side wall, and the surface of the first separation layer 202 is less than the top surface of the fin 201.
The surface of substrate 200 of the first area 210 has one or more fins 201 respectively；Described
The surface of substrate 200 in two regions 220 has one or more fins 201 respectively.In the present embodiment,
The distance between adjacent fin 201 is less than or equal to 50 nanometers in one region 210 or second area 220.
In the present embodiment, the first area 210 is used to form PMOS transistor；Secondth area
Domain 220 is used to form nmos pass transistor.In other embodiments, the first area 210 is used for shape
Into nmos pass transistor, the second area 220 is used to form PMOS transistor.
Also there is the first well region, described first in the fin 201 and substrate 200 of the first area 210
There is first kind ion in well region；Also have in the fin 201 and substrate 200 of the second area 220
Having has Second Type ion in the second well region, second well region.
In the present embodiment, the first kind ion is N-type ion；The Second Type ion is P
Type ion.The follow-up anti-break-through ion being doped into the fin 201 of first area 210 is N-type ion,
The anti-break-through ion being doped into the fin 201 of second area 220 is p-type ion.The anti-break-through from
Son is avoided relative to being subsequently formed in the Doped ions transoid in the source region and drain region in fin 201 with this
There is break-through between source region and the bottom in drain region.
In the present embodiment, the top surface of the fin 201 also has mask layer 204, the mask layer
204 masks that fin 201 is formed as etching, and the mask layer 204 can also be in subsequent technique mistake
Cheng Zhong, the top surface for protecting fin 201.In other embodiments, the top of the fin 201
Portion surface can also not have mask layer 204.
In the present embodiment, the fin 201 and substrate 200 are formed by etching semiconductor substrate.Institute
The forming step for stating fin 201 includes：Semiconductor base is provided；In the part table of the semiconductor base
Face forms mask layer 202；With the mask layer 202 as mask, the semiconductor base is etched, form institute
State substrate 200 and the fin 201 positioned at the surface of substrate 200.The semiconductor base is silicon substrate, germanium
Substrate and silicon-Germanium substrate.In the present embodiment, the semiconductor base is monocrystalline substrate, i.e., described fin
The material of portion 201 and substrate 200 is monocrystalline silicon.
The forming step of the substrate 200 and fin 201 includes：Semiconductor base is provided；Described half
The part surface of conductor substrate forms mask layer 204；With the mask layer 204 as mask, described half is etched
Conductor substrate, forms the substrate 200 and fin 201.
In one embodiment, first well region and the second well region shape before the semiconductor base is etched
Into.In another embodiment, first well region and the second well region are forming the substrate 200 and fin
After 201, formed using ion implantation technology.
The forming step of the mask layer 204 includes：Mask material is formed in the semiconductor substrate surface
Film；Patterned layer is formed on the mask material film surface；Mask described in patterned layer as mask etching
Material membrane forms the mask layer 204 untill semiconductor substrate surface is exposed.
In one embodiment, the patterned layer is patterned photoresist layer, and the patterned layer is used
Coating process and photoetching process are formed.In another embodiment, in order to reduce the feature of the fin 201
The distance between size and adjacent fin 201, the patterned layer use multiple graphical mask work
Skill is formed.The multiple graphical masking process includes：Self-alignment duplex pattern (Self-aligned
Double Patterned, SaDP) technique, autoregistration be triple graphical (Self-aligned Triple Patterned)
Technique or autoregistration quadruple are graphical (Self-aligned Double Double Patterned, SaDDP)
Technique.
In one embodiment, the formation process of the patterned layer is self-alignment duplex pattern chemical industry skill, bag
Include：In mask material film surface deposited sacrificial film；Patterned photoresist is formed on the expendable film surface
Layer；With the photoresist layer as mask, etch the expendable film is up to exposing mask material film surface
Only, sacrifice layer is formed, and removes photoresist layer；It is graphical in mask material film and sacrificial layer surface deposition
Film；The graphic film is etched back to untill sacrifice layer and mask material film surface is exposed, is being sacrificed
The semiconductor substrate surface of layer both sides forms patterned layer；It is described be etched back to technique after, removal is described
Sacrifice layer.
The technique for etching the semiconductor base is anisotropic dry etch process.The fin 201
Side wall it is vertical relative to the surface of substrate 200 or incline, and when the fin 201 side wall relative to
When the surface of substrate 200 inclines, the bottom size of the fin 201 is more than top dimension.In the present embodiment
In, the side wall of the fin 201 is inclined relative to the surface of substrate 200.
In another embodiment, the fin is formed by the semiconductor layer that etching is formed at substrate surface；
The semiconductor layer is formed at the substrate surface using selective epitaxial depositing operation.The substrate is silicon
Substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass lined
Bottom or III-V substrate, such as gallium nitride substrate or gallium arsenide substrate etc.；The semiconductor layer
Material is silicon, germanium, carborundum or SiGe.The selection of the substrate and semiconductor layer is unrestricted, energy
Enough selection is suitable to process requirements or the substrate that is easily integrated and is suitable to the material of fin.And, it is described
The thickness of semiconductor layer can be controlled by epitaxy technique, so that the fin that is formed of precise control
Highly.
In the present embodiment, also include：Before first separation layer 202 is formed, in the substrate
The side wall and top surface of 200 surfaces and fin 201 form boundary layer 203；First separation layer 202
It is formed at the surface of the boundary layer 203.The material of the boundary layer 203 is silica；The boundary layer
203 formation process is oxidation technology；The thickness of the boundary layer 203 is 5 nanometers~50 nanometers.It is described
Oxidation technology includes situ steam generation (In-Situ Steam Generation, abbreviation ISSG) technique, goes
Coupling plasma oxidation (Decoupled Plasma Oxidation, abbreviation DPO) technique, free radical oxygen
Change (Radical Oxidation) technique or wet process oxidation technology.
In one embodiment, the formation process of the boundary layer 203 is situ steam generation technique.It is described
The parameter of situ steam generation technique includes：Temperature is 700 DEG C~1200 DEG C, and gas includes hydrogen and oxygen,
Oxygen flow is 1slm~50slm, and hydrogen flowing quantity is 1slm~10slm, and the time is 20 seconds~10 minutes.
The boundary layer 203 that the situ steam generation technique is formed has good gradient coating performance, can make
The boundary layer 203 for being formed closely is covered in the sidewall surfaces of fin 201, and the interface for being formed
The thickness of layer 203 is uniform.
By forming the boundary layer 203, the substrate 200 and the surface of fin 201 can be repaired in preamble
What is be subject to during etching technics and ion implantation technology damages.And, the boundary layer 203 can also
The surface of fin 201 and substrate 200 is protected in successive process.In the present embodiment, the mask layer
204 side wall and top surface also forms the boundary layer 203.
The forming step of first separation layer 202 includes：In the surface of the substrate 200 and fin 201
Side wall and top surface formed the first barrier film；Planarize first barrier film；After planarization,
First barrier film is etched back to untill the side wall and top surface for exposing fin 201.
In the present embodiment, the material of first separation layer 202 is silica；First separation layer
202 thickness is 5 nanometers~15 nanometers.The formation process of first barrier film is heavy for fluid chemistry gas phase
Product technique (FCVD, Flowable Chemical Vapor Deposition).In other embodiments, institute
Stating the first barrier film can also be formed using other chemical vapor deposition methods or physical gas-phase deposition；
Described other chemical vapor deposition methods include plasma enhanced chemical vapor deposition technique (PECVD)
Or high-aspect-ratio chemical vapor deposition method (HARP).
In the present embodiment, the step of fluid chemistry gas-phase deposition includes：The substrate 200,
Fin 201 and the surface of mask layer 204 form forerunner's deielectric-coating；Annealing process is carried out, makes forerunner's deielectric-coating
Solidification, forms first barrier film.
The material of forerunner's deielectric-coating is siliceous flowable materials；The flowable materials can be containing
One or more condensate of polymerization in Si -- H bond, Si-N keys and Si-O keys.Forerunner's deielectric-coating
Formation process parameter includes：Technological temperature is 60 DEG C~70 DEG C, is 65 DEG C in the present embodiment.
Annealing process in the fluid chemistry gas-phase deposition can be that wet method annealing process or dry method are moved back
Ignition technique；The parameter of the annealing process includes：Temperature is less than or equal to 600 DEG C, and anneal gas include
H2、O2、N2, one or more combination in Ar and He, annealing time is 5 seconds~1 minute.Wherein,
When anneal gas include H2And O2When, the annealing process is wet method annealing process.
The flatening process is CMP process (CMP)；In the present embodiment, describedization
Mechanical polishing process is learned using the mask layer 204 as stop-layer.It is etched back to the work of first barrier film
Skill is isotropic dry etch process, anisotropic dry etch process or wet-etching technology.
It is follow-up to form the first doped layer, first doped layer and lining on the surface of the first separation layer 202
Can be mutually isolated by first separation layer 202 between bottom 200, then the first kind in the first doped layer
Type ion is not diffused into substrate 200, so as to avoid the first well region in substrate 200 and the second trap
Between area because of the diffusion of the first kind ion blur boundary problem, prevent the first well region and the second well region
Between there is break-through, reduce leakage current.
Fig. 6 is refer to, the first doped layer 205, described first are formed on the surface of the first separation layer 202
The side wall of the covering part fin 201 of doped layer 205, and the surface of the first doped layer 205 is less than described
There is first kind ion in the top surface of fin 201, first doped layer 205.
In the present embodiment, first doped layer 205 is used for being carried out in the fin of first area 210
Adulterate to form anti-reach through region.Also there is first kind ion, when follow-up in first doped layer 205
After driving the first kind ion to diffuse into fin 201 by annealing process, can be in first area
Form anti-reach through region in 210 fin 201, and the anti-reach through region is relative to being subsequently formed in first area
Source region and drain region transoid in 210 fins 201, suppress source region and drain region bottom and are sent out because ion spreads with this
The problem of raw break-through (punch through) short circuit.
The forming step of first doped layer 205 includes：On the surface of the first separation layer 202 and
The side wall and top surface of fin 201 form the first doping；Planarize first doping；Flat
After smoothization, first doping is etched back to until the side wall and top surface that expose fin 201 are
Only.
In the present embodiment, the first area 210 is used to form PMOS transistor, then and described first
Types of ion is N-type ion, and the N-type ion is phosphonium ion or arsenic ion.In other embodiments,
The first area is used to form nmos pass transistor, then the first kind ion is p-type ion, institute
The material for stating the first doped layer is Pyrex.
In the present embodiment, the material of first doped layer 205 is phosphorosilicate glass (PSG) or the phosphorus that adulterates
Non-crystalline silicon or polycrystalline silicon material.First kind ion doping concentration in first doped layer 205 is
1E15atoms/cm3~1E23atoms/cm3, the thickness of first doped layer 205 is 10 nanometers~20
Nanometer.The formation process of first doping is chemical vapor deposition method, physical gas-phase deposition
Or atom layer deposition process.When non-crystalline silicon or polysilicon material that the material of first doping is doping phosphorus
During material, in the depositing operation, first kind ion doping can be entered by doping with doping process in situ
In film.
First doped layer 205 can also be as the sacrifice layer of second area 220, due to described first
Doped layer 205 covers the side wall of part fin 201 of second area 220, follow-up removal second area 220
The first doped layer 205 after, the side wall of part fin 201 can be exposed, by second area 220
The fin 201 for exposing is doped, and anti-break-through can be formed in the fin 201 of second area 220
Area.Therefore, because sacrifice layer need not be additionally formed to define the anti-reach through region of second area 220, simplify
Manufacturing process, save process time and cost.
Fig. 7 is refer to, in the surface of the first doped layer 205 and the side wall and top surface of fin 201
Form the first barrier layer 206.
First barrier layer 206 is used to protect the fin 201 higher than the side wall of the first doped layer 205
Surface, the ion in the second doped layer that prevention is subsequently formed is to the fin 201 higher than the first doped layer 205
Interior diffusion.
The material on first barrier layer 206 is the one kind or many in silicon nitride, silica or silicon oxynitride
Kind, the material on first barrier layer 206 is required to prevent the first kind in the doped layer that is subsequently formed
Type ion spreads.In the present embodiment, the material on first barrier layer 205 is silicon nitride.
The formation process on first barrier layer 206 includes chemical vapor deposition method, physical vapour deposition (PVD)
Technique or atom layer deposition process, are in the present embodiment atom layer deposition process.
Fig. 8 is refer to, removal stops positioned at the part first on the surface of 220 first doped layer of second area 205
First doped layer 205 of layer 206 and second area 220, retains and is located at the fin 201 of second area 220
First barrier layer of part 206 of sidewall surfaces, and expose the side wall of part fin 201 of second area 220.
Removal positioned at the surface of 220 first doped layer of second area 205 the first barrier layer of part 206 and
The step of first doped layer 205 of second area 220, includes：On the first barrier layer of first area 210
206 surfaces form patterned layer 207；With the patterned layer 207 as mask, using anisotropic dry
Method etching technics etches first barrier layer 206, until exposing the first doped layer of second area 220
Untill 205 surfaces；After first barrier layer 206 is etched, carved using isotropic etching technics
First doped layer 205 is lost, until exposing the surface of the first separation layer 202 and of second area 220
Untill the sidewall surfaces of part fin 201 in two regions 220.
In the present embodiment, the patterned layer 207 includes patterned photoresist layer；Described first covers
Film layer 207 is formed using coating process and photoetching process.
The technique for etching first barrier layer 206 is anisotropic dry etch process；It is described it is each to
The parameter of the dry etch process of the opposite sex includes：Gas includes carbon fluorine gas and carrier gas, the carbon fluorine gas
Including CF4、CHF3、CH2F2、CH3F, the carrier gas is inert gas, such as He, gas flow
It is 50sccm~1000sccm, pressure is 2 millitorr~10 millitorrs, 150 watts~800 watts of bias power.
Because the etching direction of the anisotropic dry etch process is perpendicular to the surface of substrate 200, position
In the first barrier layer 206 of the sidewall surfaces of fin 201 with etching direction it is parallel or with etching direction angle
Smaller, the first barrier layer 206 therefore in the sidewall surfaces of fin 201 will not be carved by etching gas
Erosion, and be retained in the etching technics.
The technique for removing the first doped layer 205 of the second area 220 is dry etch process or wet method
Etching technics；Wherein, the dry etch process can be isotropic dry etch process.At this
In embodiment, the technique for removing the first doped layer 205 of the second area 220 is isotropic dry
Method etching technics.
In the present embodiment, after the first doped layer 205 of removal second area 220, fin is removed
The boundary layer 203 that 201 sidewall surfaces expose, is close to the fin 201 that this exposes second area 220
The sidewall surfaces of the first separation layer 202, the wall doping that can be subsequently exposed to the fin 201 is prevented
Break-through ion.
The technique of the boundary layer 203 exposed described in removal is isotropic dry etch process or wet method
Etching technics.In the present embodiment, the technique of the boundary layer 203 for being exposed described in removal is SICONI
Technique；The parameter of the SICONI techniques includes：Power 10W~100W, frequency is less than 100kHz,
Etching temperature is 40 degrees Celsius~80 degrees Celsius, and pressure is 0.5 support~50 support, and etching gas include NH3、
NF3, He, wherein, NH3Flow be 0sccm~500sccm, NF3Flow be 20sccm~200sccm,
The flow of He is 400sccm~1200sccm, NF3With NH3Flow-rate ratio be 1:20~5:1.
SICONI techniques etch rate in all directions is uniform, it is easy to go deep into adjacent fin 201
Between perform etching, even if the groove depth-to-width ratio between adjacent fin 201 is larger.And, using SICONI
When technique is performed etching, the sidewall surfaces to the fin 201 damage smaller.
Subsequently after part first barrier layer 206 of removal second area 220 and the first doped layer 205,
The sidewall surfaces of fin 201 exposed in second area 200 form the second doped layer, second doping
There is Second Type ion in layer.The forming step of the second doped layer is illustrated below with reference to accompanying drawing.
Refer to Fig. 9, the surface of the first barrier layer 206, the sidewall surfaces of the first doped layer 205,
The side wall of fin 201 that the surface of first separation layer 202 of second area 220, second area 202 expose
The second doping 208 is formed with top surface.
In the present embodiment, before the second doping 208 is formed, also including removal patterned layer 207.
The technique for removing the patterned layer 207 includes wet-etching technology or cineration technics.
There is Second Type ion, second doping 208 and second in second doping 208
The side wall of fin 201 that region 202 exposes is in contact, subsequently through annealing process can drive second from
Son is diffused into the fin 201 of second area 220, forms anti-in the fin 201 of second area 220
Reach through region.And the side wall of fin 201 for exposing be located at the first barrier layer 206 and the first separation layer 202 it
Between, therefore be subsequently formed in the anti-reach through region in the fin 201 of second area 220 positioned at the described first stop
Between the separation layer 202 of layer 206 and first.
In the present embodiment, the second area is used to form nmos pass transistor, the Second Type from
Son is p-type ion, and the p-type ion includes boron ion or indium ion；It is subsequently formed in second area 220
Source region and drain region and anti-reach through region transoid in fin 201, source region and drain region bottom are suppressed because of ion with this
Spread and the problem of break-through short circuit occurs.
In the present embodiment, the material of second doping 208 is Pyrex or the non-crystalline silicon of doping boron
Or polycrystalline silicon material.The formation process of second doping 208 is chemical vapor deposition method, physics
Gas-phase deposition or atom layer deposition process；In the depositing operation, can be with doping process in situ
Second Type ion doping is entered in the second doping 208.Boron ion in second doping 208
Concentration is 3E20atoms/cm3~5E21atoms/cm3, the thickness of second doping 208 is
In another embodiment, the second area is used to form PMOS transistor, the Second Type
Ion is N-type ion, and the material of second doping is phosphorosilicate glass.
In the present embodiment, also include：The second barrier film 209 is formed on the surface of the second doping 208；
The material of second barrier film 209 is silicon nitride.In other embodiments, second barrier film 209
Material can also be silica or silicon oxynitride.Second barrier film 209 is used in subsequent anneal work
In skill, prevent adulterated Second Type ion to surface loss, with ensure adulterated Second Type from
Son can be diffused into the fin 201 of second area 220 completely.
Figure 10 is refer to, second doping 208 (as shown in Figure 9) is etched back to until exposing the
Untill the surface of first separation layer 202 in two regions 220, the second doped layer 208a is formed.
In the present embodiment, the technique that is etched back to also includes the of removal on the first separation layer 202
Two barrier films, and form the second barrier layer 209a on the second doped layer 208a surfaces.
The technique that is etched back to is for anisotropic dry etch process；The anisotropic dry etching
The parameter of technique includes：Gas includes carbon fluorine gas and carrier gas, and the carbon fluorine gas include CF4、CHF3、
CH2F2、CH3F, the carrier gas is inert gas, and such as He, gas flow is 50sccm~1000
Sccm, pressure is 2 millitorr~10 millitorrs, 150 watts~800 watts of bias power.
Because the etching direction of the anisotropic dry etch process is perpendicular to the surface of substrate 200, position
Etching gas are not easily susceptible in second doping 208 and the second barrier film 209 of the sidewall surfaces of fin 201
Etching such that it is able in the etching technics be retained, formed the second doped layer 208a surfaces shape
Into the second barrier layer 209a.
In the present embodiment, it is described be etched back to technique also remove on the first doped layer 205, Yi Jiwei
Part the second doping 208 and the second barrier film 209 on fin top.
By removing second doping 208 on the surface of the first separation layer 202 of second area 220, can keep away
Exempting from follow-up annealing process drives Second Type ion to diffuse into first separation layer 202, it is to avoid institute
The dielectric constant for stating the first separation layer 202 is changed, and the electricity of first separation layer 202 is ensured with this
Stable performance and meet technical need.
In other embodiments, additionally it is possible to be not etched back to second doping 208, directly carry out follow-up
Annealing process.
Figure 11 is refer to, annealing process is carried out, drives the first kind ion in the first doped layer 205 to expand
Spill into the fin 201 of first area 210, drive the Second Type ion in the second doped layer 208a to expand
Spill into the fin 201 of second area 220.
In the present embodiment, the annealing process is rapid thermal annealing；The temperature of the annealing process is 1000
DEG C~1100 DEG C, annealing time is 1 second~5 seconds.
The annealing process is used to drive the first kind ion in first doped layer 205 to diffuse into the
In the fin 201 in one region 210, anti-reach through region is formed in the fin 201 of first area 210；Together
When, the annealing process is used to drive the Second Type ion in the second doped layer 208a to diffuse into the secondth area
In the fin 201 in domain 220, anti-reach through region is formed in the fin 201 of the second area 220.
Figure 12 is refer to, after the annealing process, the first doped layer 205 (as shown in figure 11) of removal,
First barrier layer 206 (as shown in figure 11) and the second doped layer 208a (as shown in figure 11).
In the present embodiment, also include：Remove the second barrier layer 209a and higher than the first separation layer 202
The boundary layer 203 on surface.
Remove the boundary layer 203, the first doped layer 205, the first barrier layer 206, the second doped layer 208a
Be wet-etching technology or dry etch process with the technique of the second barrier layer 209a, in the present embodiment for
Wet-etching technology.In other embodiments, the etching technics is dry etch process, then described dry
Method etching technics is isotropic dry etch process.
In the present embodiment, remove the boundary layer 203, the first doped layer 205, the first barrier layer 206,
After second doped layer 208a and the second barrier layer 209a, the groove between adjacent fin 201 can be increased
Depth-to-width ratio.The surface of the substrate 200 is additionally, since with the first separation layer 202, first separation layer
202 can also reduce the groove depth-to-width ratio between adjacent fin 201.
When dielectric layer is subsequently formed, the material of dielectric layer is easy to be filled in the groove, helps to make
The dielectric layer dense uniform for being formed, and cause the dielectric layer and fin 201 and the surface of substrate 200
With reference to tightr such that it is able to reduce the leakage current of formed fin formula field effect transistor, device is improved
Yield.
Figure 13 is refer to, the first doped layer 205 (as shown in figure 11), the first barrier layer 206 is being removed
After (as shown in figure 11) and the second doped layer 208a (as shown in figure 11), in the described first isolation
202 surface of layer form the second separation layer 230, the side of the covering part fin 201 of second separation layer 230
Wall, and the surface of the second separation layer 230 is less than the top surface of the fin 201.
After first doped layer, the first barrier layer and the second doped layer is removed, also including removal institute
State mask layer 204 (as shown in figure 12).In the present embodiment, second separation layer 230 is being formed
Afterwards, the mask layer 204 (as shown in figure 12) is removed.
First separation layer 205 is with the second separation layer 230 collectively as the isolation junction between adjacent fin
Structure.In the present embodiment, the surface of second separation layer 230 is higher than the anti-reach through region in fin 201
Top.In other embodiments, the surface of second separation layer 230 is flush in fin 201
The top of anti-reach through region.
The forming step of second separation layer 230 includes：On the surface of the first separation layer 202 and
The side wall and top surface of fin 201 form the second barrier film；Planarize second barrier film；Flat
After smoothization, second barrier film is etched back to until the side wall and top surface that expose fin 201 are
Only.
In the present embodiment, the material of second separation layer 230 be silica, formed described second every
It is high-density plasma deposition (High Density Plasma, abbreviation HDP) technique from the technique of film；Institute
The parameter for stating higli density plasma deposition process includes：Gas includes SiH4And O2, the SiH4Flow
It is 60sccm~130sccm, the O2Flow be 100sccm~300sccm, radio-frequency power is
2000W~5000W, air pressure is 2 millitorr~8 millitorrs.
The the second isolation film density formed using higli density plasma deposition process is higher, is conducive to follow-up
Flatening process in holding surface it is flat.
In other embodiments, the formation process of second barrier film can also be plasma enhancing
Learn gas-phase deposition (PECVD) or high-aspect-ratio chemical vapor deposition method (HARP).
The flatening process is CMP process (CMP).In the present embodiment, describedization
Mechanical polishing process is learned using the mask layer 204 as stop-layer.
The technique for being etched back to the deielectric-coating is isotropic dry etch process, anisotropic dry method
Etching technics or wet-etching technology.In the present embodiment, the technique that is etched back to is done for isotropic
Method etching technics；Isotropic dry etch process is SICONI techniques.
SICONI techniques etch rate in all directions is uniform, it is easy to go deep into adjacent fin 201
Between perform etching, even if the groove depth-to-width ratio between adjacent fin 201 is larger, it is also possible to after making etching
The surface of the second separation layer 230 for being formed is flat.
In the present embodiment, after second separation layer 230 is formed, it is developed across the fin 201
Grid structure, the grid structure covers the partial sidewall and top surface of the fin 201；Institute
State and source region and drain region are formed in the fin 201 of grid structure both sides.
The grid structure includes：Positioned at the pseudo- gate oxide on the surface of fin 201 and positioned at pseudo- grid oxygen
Change the dummy gate layer of layer and insulation surface.The material of the pseudo- gate oxide is silica, formation process
It is thermal oxidation technology or situ steam generation (ISSG) technique；The material of the dummy gate layer is polysilicon,
Formation process includes chemical vapor deposition method and CMP process.
The grid structure can also include being located at the side wall of pseudo- gate oxide and dummy gate layer sidewall surfaces.
The material of the side wall is one or more combination in silica, silicon nitride, silicon oxynitride.The side
Wall is used to define the relative position between source region and drain region and dummy gate layer.
In one embodiment, the forming step in the source region and drain region includes：In the grid structure both sides
Fin 201 in formed opening；Stressor layers are formed in the opening using selective epitaxial depositing operation；
Doped p-type ion or N-type ion in the stressor layers.The material of the stressor layers is carborundum or silicon
Germanium.
After source region and drain region is formed, also include：In second separation layer 230 and the table of fin 201
Face forms interlayer dielectric layer, and the interlayer dielectric layer covers the side wall of the grid structure, and the grid are situated between
Matter layer exposes the dummy gate layer；The dummy gate layer and pseudo- gate oxide are removed, in interlayer dielectric layer
Interior formation gate trench；Gate dielectric layer is formed in the inner wall surface of the gate trench；In the gate medium
Layer surface forms the grid layer of the full gate trench of filling.Wherein, the material of the gate dielectric layer is k high
Dielectric material (dielectric constant is more than 3.9)；The material of the grid layer be metal, the metal include copper,
Tungsten, aluminium or silver.
In one embodiment, also have between the gate dielectric layer and the side wall and top surface of fin 201
Interface oxide layer；The material of the interface oxide layer is silica；The formation process of the interface oxide layer
It can be thermal oxidation technology；The interface oxide layer is used to strengthen the gate dielectric layer and the surface of fin 201
Between bond strength.
In other embodiments, between the grid layer and gate dielectric layer, additionally it is possible to formed work-function layer,
One or more combination in coating (cap layer) and barrier layer (barrier layer).
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
There is provided substrate, the substrate include first area and second area, the first area of the substrate and
Second area surface has fin respectively, and the substrate surface has the first separation layer, first isolation
The side wall of layer covering part fin, and first insulation surface is less than the top surface of the fin；
The first doped layer, the first doped layer covering part fin are formed in first insulation surface
Side wall, and it is described first doping layer surface less than the fin top surface, first doped layer
It is interior with first kind ion；
The first barrier layer is formed in the side wall and top surface of the described first doping layer surface and fin；
Removal positioned at the barrier layer of part first of the doping layer surface of second area first and second area the
One doped layer, retains positioned at the barrier layer of part first of second area fin sidewall surfaces, and exposes the
The part fin side wall in two regions；
After the barrier layer of part first of removal second area and the first doped layer, in second area exposure
The fin sidewall surfaces for going out are formed has Second Type ion in the second doped layer, second doped layer；
Annealing process is carried out, drives the first kind ion in the first doped layer to diffuse into the fin of first area
In portion, the Second Type ion in the second doped layer is driven to diffuse into the fin of second area；
After the annealing process, the first doped layer of removal, the first barrier layer and the second doped layer；
After the first doped layer, the first barrier layer and the second doped layer is removed, in first separation layer
Surface formed the second separation layer, the side wall of the second separation layer covering part fin, and described second every
Top surface of the absciss layer surface less than the fin.
2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
The forming step of one doped layer includes：In the side wall and top of first insulation surface and fin
Surface forms the first doping；Planarize first doping；After planarization, it is etched back to institute
The first doping is stated untill the side wall and top surface for exposing fin.
3. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that removal position
In the barrier layer of part first of the doping layer surface of second area first and the first doped layer of second area
The step of include：The first barrier layer surface in first area forms patterned layer；With described graphical
Layer is mask, and first barrier layer is etched using anisotropic dry etch process, until exposure
Untill going out the first doping layer surface of second area；After first barrier layer is etched, using each
First doped layer is etched to the etching technics of the same sex, until exposing the first isolation of second area
Untill the part fin sidewall surfaces of layer surface and second area.
4. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
The forming step of two doped layers includes：In first barrier layer surface, the side wall table of the first doped layer
Fin side wall and top surface that face, the first insulation surface of second area, second area expose
Form the second doping；Second doping is etched back to until exposing the first isolation of second area
Untill layer surface.
5. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
The forming step of one separation layer includes：In the substrate surface and the side wall and top surface shape of fin
Into the first barrier film；Planarize first barrier film；After planarization, it is etched back to described first
Barrier film is untill the side wall and top surface for exposing fin.
6. the forming method of fin formula field effect transistor as claimed in claim 5, it is characterised in that described
The formation process of one barrier film is fluid chemistry gas-phase deposition.
7. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：
Before first separation layer is formed, in the substrate surface and the side wall and top surface of fin
Form boundary layer；First separation layer is formed at the interface layer surfaces；In removal second area
After first doped layer, the boundary layer that removal fin sidewall surfaces expose.
8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that the boundary
The material of surface layer is silica.
9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：
The second doping layer surface forms the second barrier layer.
10. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described
The forming step of two separation layers includes：In the side wall and top of first insulation surface and fin
Surface forms the second barrier film；Planarize second barrier film；After planarization, it is etched back to institute
The second barrier film is stated untill the side wall and top surface for exposing fin.
The forming method of 11. fin formula field effect transistors as claimed in claim 10, it is characterised in that described
The formation process of two barrier films is high density plasma CVD technique.
The forming method of 12. fin formula field effect transistors as claimed in claim 1, it is characterised in that the fin
The top surface in portion also has mask layer.
The forming method of 13. fin formula field effect transistors as claimed in claim 12, it is characterised in that in removal
After first doped layer, the first barrier layer and the second doped layer, the mask layer is removed.
The forming method of 14. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
One types of ion is p-type ion；The Second Type ion is N-type ion.
The forming method of 15. fin formula field effect transistors as claimed in claim 14, it is characterised in that described
The material of one doped layer is Pyrex；The material of second doped layer is phosphorosilicate glass.
The forming method of 16. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
One types of ion is N-type ion；The Second Type ion is p-type ion.
The forming method of 17. fin formula field effect transistors as claimed in claim 16, it is characterised in that described
The material of one doped layer is phosphorosilicate glass；The material of second doped layer is Pyrex.
The forming method of 18. fin formula field effect transistors as claimed in claim 1, it is characterised in that described to move back
Ignition technique is rapid thermal annealing；The temperature of the annealing process be 1000 DEG C~1100 DEG C, annealing time
It is 1 second~5 seconds.
The forming method of 19. fin formula field effect transistors as claimed in claim 1, it is characterised in that described
Having in the substrate in one region has first kind ion in the first well region, first well region；It is described
Having in the substrate of second area has Second Type ion in the second well region, second well region.
The forming method of 20. fin formula field effect transistors as claimed in claim 1, it is characterised in that also include：
After the first doped layer, the first barrier layer and the second doped layer is removed, the fin is developed across
Grid structure, the grid structure covers the partial sidewall and top surface of the fin；In the grid
Source region and drain region are formed in the fin of pole structure both sides.
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| CN111200011A (en) * | 2018-11-20 | 2020-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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