CN108732542B - Ultra-wideband radar receiving and transmitting front end - Google Patents
Ultra-wideband radar receiving and transmitting front end Download PDFInfo
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- CN108732542B CN108732542B CN201810860567.4A CN201810860567A CN108732542B CN 108732542 B CN108732542 B CN 108732542B CN 201810860567 A CN201810860567 A CN 201810860567A CN 108732542 B CN108732542 B CN 108732542B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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Abstract
The invention discloses an ultra-wideband radar receiving and transmitting front end, and belongs to the technical field of frequency synthesis. The ultra-wideband radar receiving and transmitting front end comprises a receiving down-conversion module, an up-conversion module, a frequency source module and a power supply control module; the frequency source module is used for providing local oscillation signals for the receiving down-conversion module and providing local oscillation signals and ultra-bandwidth linear frequency modulation signals for the up-conversion module; the receiving down-conversion module is used for receiving the echo signals and performing down-conversion processing on the echo signals to obtain sampling intermediate frequency signals; the up-conversion module is used for carrying out up-conversion processing on the signals generated by the frequency source module to obtain radio frequency signals; the power supply control module is used for controlling the receiving down-conversion module, the up-conversion module and the frequency source module according to the power supply control signal and supplying power to the receiving down-conversion module, the up-conversion module and the frequency source module; the problem that the instantaneous working bandwidth of the existing receiving and transmitting front end remains within 300MH is solved; the functions of ultra-wide full-time operation bandwidth and instantaneous operation bandwidth are realized.
Description
Technical Field
The embodiment of the invention relates to the field of frequency synthesis, in particular to an ultra-wideband radar receiving and transmitting front end.
Background
The receiving and transmitting front end is a core component of the radar system and is used for completing the generation and receiving functions of radar radio frequency signals.
Through years of research, china has a major breakthrough in the spread spectrum technology of radar systems, but the common instantaneous working bandwidth still stays within 300 MHz. Due to the limitation of indexes such as strays, the rapid popularization of the ultra-large instantaneous bandwidth of more than 1GHz has certain difficulty.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiment of the invention provides an ultra-wideband radar receiving and transmitting front end. The technical scheme is as follows:
in a first aspect, an ultra-wideband radar transceiver front end is provided, including a receiving down-conversion module, an up-conversion module, a frequency source module, and a power control module;
the frequency source module comprises a DDS chip, a crystal oscillator, a harmonic generator, a filter, a switch, a power divider, a coupler, an amplifier and a mixer, wherein the local oscillator signal output end and the ultra-bandwidth linear frequency modulation signal end of the frequency source are connected with the up-conversion module, and the local oscillator signal output end of the frequency source module is connected with the down-conversion module;
the up-conversion module comprises a filter, a mixer, an amplifier and a switch;
the receiving down-conversion module comprises a limiter, a numerical control attenuator, a mixer, a filter, an amplifier and a switch;
the power supply control module is respectively connected with the up-conversion module, the down-conversion module and the frequency source module;
the frequency source module is used for providing local oscillation signals for the receiving down-conversion module and providing local oscillation signals and ultra-bandwidth linear frequency modulation signals for the up-conversion module;
the receiving down-conversion module is used for receiving the echo signals and performing down-conversion processing on the echo signals to obtain sampling intermediate frequency signals;
the up-conversion module is used for carrying out up-conversion processing on the signals generated by the frequency source module to obtain radio frequency signals;
the power control module is used for controlling the receiving down-conversion module, the up-conversion module and the frequency source module according to the power control signal and supplying power to the receiving down-conversion module, the up-conversion module and the frequency source module;
the frequency source module outputs local oscillation signals, the local oscillation signals comprise a local oscillation signal and two local oscillation signals, the frequency of the local oscillation signal is 11-18GHz, the minimum frequency hopping step of the local oscillation signal is 0.84Hz, and the frequency of the two local oscillation signals is 3.6GHz; the frequency of the ultra-wideband linear frequency modulation signal is 0.1-1.1GHz.
Optionally, in the frequency source module, the 100M crystal oscillator is connected with a first harmonic generator, the first harmonic generator is connected with a first power divider, a first output end of the first power divider is connected with a first two-choice one-switch filter bank, and the first two-choice one-switch filter bank is connected with the first mixer through an amplifier;
the first DDS chip is connected with the first mixer through a filter;
the first mixer is connected with a first four-way switch filter bank, and the first four-way switch filter bank is connected with the second mixer through an amplifier;
the second output end of the first power divider is connected with a second harmonic generator through a filter and an amplifier, the output end of the second harmonic generator is connected with a second four-way switch filter bank, and the second four-way switch filter bank is connected with a second mixer through the amplifier;
the second mixer is connected with a second alternative switch filter bank, the second alternative switch filter bank is connected with a first single-pole double-throw switch through an amplifier, a first branch of the first single-pole double-throw switch is connected with a third mixer through the amplifier, and a second branch of the first single-pole double-throw switch is connected with a second branch of the second single-pole double-throw switch;
the third output end of the first power divider is connected with the second power divider through a filter and an amplifier, and the first output end of the second power divider is connected with the first DDS chip;
the second output end of the second power divider is connected with the third mixer;
the third mixer is connected with a third alternative switch filter bank, and the third alternative switch filter bank is connected with the first branch of the second single-pole double-throw switch through an amplifier;
the second single-pole double-throw switch is connected with a coupler through an amplifier, and the coupler outputs a local oscillation signal and a detection signal;
the third output end of the second power divider is connected with a coupler through an amplifier, and the coupler outputs a second local oscillation signal and a detection signal;
the fourth output end of the second power divider is connected with a second DDS chip, and the second DDS chip outputs an ultra-wideband linear frequency modulation signal;
the method comprises the steps of converting 100MHz crystal oscillator frequency multiplication into a first comb spectrum signal by using a first harmonic generator, and converting the first comb spectrum signal into a plurality of low local oscillator signals by using a switch filter bank, wherein the low local oscillator signals comprise 1GHz signals, 3.6GHz signals and 2.7/3.2GHz signals;
converting the 1GHz signal into a second comb spectrum signal by using a second harmonic generator, and converting the second comb spectrum signal into a plurality of high local oscillator signals by using a switch filter bank, wherein the high local oscillator signals are 10/11/15/16GHz signals;
with one path of 3.6GHz signal as a reference clock, the DDS chip is pushed to generate an intermediate frequency signal, the frequency of the intermediate frequency signal is 300-800MHz, and the minimum step is 0.84Hz;
mixing the intermediate frequency signal with a 2.7/3.2GHz signal, and generating a 3-4GHz signal through a switch filter;
mixing the 3-4GHz signal with the 10/11/15/16GHz signal, and generating an 11-15GHz signal through a switch filter;
mixing the 11-15GHz signals with the 3.6GHz signals, and generating a local oscillation signal through a switch filter;
and the other 3.6GHz signal is used as two local oscillation signals, and the two local oscillation signals are used as reference clocks to drive the DDS chip to generate ultra-wideband linear frequency modulation signals.
Optionally, the up-conversion module inputs the ultra-wideband linear frequency modulation signal output by the frequency source module into a first filter, and the first filter is connected with a fourth mixer;
the second local oscillation signal output by the frequency source module is input into a fourth mixer, and the fourth mixer is connected with a fifth mixer through an amplifier and a second filter;
a local oscillation signal output by the frequency source module is input into a fifth mixer, and the fifth mixer is connected with a nine-choice switch filter bank;
the nine-selection one-switch filter bank is connected with a coupler through an amplifier, and the coupler outputs radio frequency signals and detection signals;
the ultra-bandwidth linear frequency modulation signal and the two local oscillation signals are mixed and filtered to generate a 2.5-3.5GHz signal;
the 2.5-3.5GHz signal is mixed with a local oscillation signal, a radio frequency signal is generated through a nine-selection one-switch filter bank, the radio frequency signal is any section of linear frequency modulation signal with the instantaneous bandwidth of 1GHz in 8-18GHz, and the minimum interval of the radio frequency signal is 0.84Hz.
Optionally, the frequency conversion module, upon receiving the down-conversion module,
the echo signal is connected with a three-in-one switch filter bank through a limiter and an amplifier, and the three-in-one switch filter bank is connected with a sixth mixer through a numerical control attenuator;
a local oscillation signal output by the frequency source module is connected with the sixth mixer;
the sixth mixer is connected with the seventh mixer through a filter, an amplifier and a numerical control attenuator, and the second local oscillation signal output by the frequency source module is connected with the seventh mixer;
the seventh mixer is connected with a coupler through an amplifier and a numerical control attenuator, and the coupler outputs a detection signal and adopts an intermediate frequency signal;
the echo signal and a local oscillation signal are mixed to take off sidebands, and a 2.5-3.5GHz signal is obtained;
mixing and filtering the 2.5-3.5GHz signal and the two local oscillation signals to obtain a sampling intermediate frequency signal of 0.1-1 GHz.
Optionally, the power control module comprises a voltage stabilizer, a power filter, a level converter and an FPGA;
the voltage stabilizer is used for converting the input voltage into the voltage required by the receiving down-conversion module, the up-conversion module and the frequency source module;
the level converter is connected with the FPGA, and the FPGA is used for controlling the receiving down-conversion module, the up-conversion module and the frequency source module.
The technical scheme provided by the embodiment of the invention has the beneficial effects that:
the ultra-wideband radar receiving and transmitting front end comprises a receiving down-conversion module, an up-conversion module, a frequency source module and a power supply control module, wherein the frequency source module is used for receiving the down-conversion module and providing local oscillation signals and providing the up-conversion module with the local oscillation signals and ultra-wideband linear frequency modulation signals of 0.1-1.1GHz; the up-conversion module generates a radio frequency signal with 1GHz of any section of instantaneous bandwidth in 8-18GHz according to the local oscillation signal and the ultra-wideband linear frequency modulation signal with 0.1-1.1GHz, and the receiving down-conversion module can receive any section of linear frequency modulation signal with 1GHz bandwidth in the range of 10GHz of the full-time working bandwidth; the problem that the instantaneous working bandwidth of the existing receiving and transmitting front end remains within 300MH is solved by utilizing the broadband sweep frequency technology and the frequency synthesis technology of the latest high-speed DDS chip; the ultra-wide full-time working bandwidth and the instantaneous working bandwidth are realized, the spurious suppression index of 60dBc can still be achieved, and the index requirements of communication equipment of each large platform can be met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram illustrating a configuration of an ultra-wideband radar transceiver front-end in accordance with an exemplary embodiment;
FIG. 2 is a schematic diagram of a frequency source module according to an exemplary embodiment;
FIG. 3 is a schematic diagram of an up-conversion module according to an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating a receive down conversion module according to an exemplary embodiment;
fig. 5 is a functional block diagram of a power control module according to another exemplary embodiment.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, a block diagram of an ultra wideband radar transceiver front end according to an embodiment of the present invention is shown. As shown in fig. 1, the ultra-wideband radar transceiver front-end includes a receiving down-conversion module 110, an up-conversion module 130, a frequency source module 120, and a power control module 140.
The local oscillator signal output end and the ultra-bandwidth chirp signal end of the frequency source module 120 are connected with the up-conversion module 130, and the local oscillator signal output end of the frequency source module 120 is connected with the down-conversion module 110.
The local oscillation signal output end of the frequency source module 120 outputs a local oscillation signal LO1 and two local oscillation signals LO2; the ultra-wideband chirp signal terminal of the frequency source module 120 outputs an ultra-wideband chirp signal L1.
The power control module 140 is connected to the up-conversion module 130, the receiving down-conversion module 110, and the frequency source module 120, respectively.
The frequency source module 120 is configured to provide local oscillation signals LO1 and LO2 to the receiving down-conversion module 110, and provide local oscillation signals LO1 and LO2 and ultra-wideband chirp signal L1 to the up-conversion module 130.
The receiving down-conversion module 110 is configured to receive the echo signal S1, and perform down-conversion processing on the echo signal S1 to obtain a sampled intermediate frequency signal L2.
The up-conversion module 130 is configured to up-convert the signal generated by the frequency source module 120 to obtain a radio frequency signal RF.
The power control module 140 is configured to control the receiving down-conversion module 110, the up-conversion module 130, and the frequency source module 120 according to the power control signal, and to supply power to the receiving down-conversion module 110, the up-conversion module 130, and the frequency source module 120.
The frequency source module outputs local oscillation signals, the local oscillation signals comprise a local oscillation signal LO1 and two local oscillation signals LO2, the frequency of the local oscillation signals is 11-18GHz, and the minimum frequency hopping step of the local oscillation signals is 0.84Hz; the frequency of the two local oscillation signals LO2 is 3.6GHz; the frequency of the ultra-wideband linear frequency modulation signal L1 is 0.1-1.1GHz.
The frequency source module comprises a DDS chip, a crystal oscillator, a harmonic generator, a filter, a switch, a power divider, a coupler, an amplifier and a mixer.
The up-conversion module comprises a filter, a mixer, an amplifier and a switch.
The receiving down-conversion module comprises a limiter, a numerical control attenuator, a mixer, a filter, an amplifier and a switch.
In order to ensure optimal frequency hopping time and phase noise indexes, a frequency source module adopts a direct frequency synthesis mode.
In the frequency source module, as shown in fig. 2, a 100M crystal oscillator is connected with a first harmonic generator, the first harmonic generator is connected with a first power divider, a first output end of the first power divider is connected with a first two-by-one switch filter bank, and the first two-by-one switch filter bank is connected with a first mixer through an amplifier; the first DDS chip is connected with the first mixer through a filter; the first mixer is connected with a first four-way switch filter bank, and the first four-way switch filter bank is connected with the second mixer through an amplifier; the second output end of the first power divider is connected with a second harmonic generator through a filter and an amplifier, the output end of the second harmonic generator is connected with a second four-way switch filter bank, and the second four-way switch filter bank is connected with a second mixer through the amplifier; the second mixer is connected with a second alternative switch filter bank, the second alternative switch filter bank is connected with a first single-pole double-throw switch through an amplifier, a first branch of the first single-pole double-throw switch is connected with a third mixer through the amplifier, and a second branch of the first single-pole double-throw switch is connected with a second branch of the second single-pole double-throw switch; the third output end of the first power divider is connected with the second power divider through a filter and an amplifier, and the first output end of the second power divider is connected with the first DDS chip; the second output end of the second power divider is connected with the third mixer; the third mixer is connected with a third alternative switch filter bank, and the third alternative switch filter bank is connected with the first branch of the second single-pole double-throw switch through an amplifier; the second single-pole double-throw switch is connected with a coupler through an amplifier, and the coupler outputs a local oscillation signal and a detection signal; the third output end of the second power divider is connected with a coupler through an amplifier, and the coupler outputs a second local oscillation signal and a detection signal; the fourth output end of the second power divider is connected with a second DDS chip, and the second DDS chip outputs an ultra-wideband linear frequency modulation signal.
The first harmonic generator is utilized to convert the frequency multiplication of the 100MHz crystal oscillator into a first comb spectrum signal, and the switch filter bank is utilized to convert the first comb spectrum signal into a plurality of low local oscillation signals, wherein the low local oscillation signals comprise 1GHz signals, 3.6GHz signals and 2.7/3.2GHz signals.
The 1GHz signal is converted into a second comb spectrum signal by using a second resonance generator, and the second comb spectrum signal is converted into a plurality of high local oscillator signals by using a switch filter bank, wherein the high local oscillator signals are 10/11/15/16GHz signals.
And a 3.6GHz signal is taken as a reference clock, a DDS (Direct Digital Synthesizer, direct digital frequency synthesizer) chip is pushed to generate an intermediate frequency signal, the frequency of the intermediate frequency signal is 300-800MHz, and the minimum step is 0.84Hz.
Mixing the intermediate frequency signal with a 2.7/3.2GHz signal, and generating a 3-4GHz signal through a switch filter; mixing the 3-4GHz signal with the 10/11/15/16GHz signal, and generating an 11-15GHz signal through a switch filter; mixing the 11-15GHz signals with the 3.6GHz signals, and generating a local oscillation signal LO1 through a switch filter;
the other 3.6GHz signal is taken as two local oscillation signals LO2, and the two local oscillation signals LO2 are taken as a reference clock to push the DDS chip to generate an ultra-wideband linear frequency modulation signal L1.
It should be noted that, the bandwidth of the switch filter bank and the filter selected in the frequency source module is shown in fig. 2, and will not be described here again.
The up-conversion module, as shown in fig. 3, inputs the ultra-wideband linear frequency modulation signal output by the frequency source module into a first filter, and the first filter is connected with a fourth mixer; the second local oscillation signal output by the frequency source module is input into a fourth mixer, and the fourth mixer is connected with a fifth mixer through an amplifier and a second filter; a local oscillation signal output by the frequency source module is input into a fifth mixer, and the fifth mixer is connected with a nine-choice switch filter bank; the nine-one switch filter group is connected with a coupler through an amplifier, and the coupler outputs radio frequency signals and detection signals.
The up-conversion module mixes and filters the ultra-wideband linear frequency modulation signal L1 input by the frequency source module and the two local oscillation signals LO2 to generate 2.5-3.5GHz signals; the 2.5-3.5GHz signal is mixed with a local oscillator signal LO1 and a radio frequency signal RF is generated through a nine-switch filter bank.
The RF signal is a linear frequency modulation signal with the instantaneous bandwidth of 1GHz in any section of 8-18GHz, and the minimum interval of the RF signal is 0.84Hz.
Since the minimum step of a local oscillation signal LO1 is 0.84Hz, the bandwidth of the ultra-wideband chirp signal L1 is 1GHz, and the segment bit of the switch filter bank is nine-selected: 8-10G, 9-11G, 10-12G, 11-13G, 12-14G, 13-15G, 14-16G, 15-17G and 16-18G, so that the up-conversion module can output any section of linear frequency modulation signal with the instantaneous bandwidth of 1GHz in the range of 8-18GHz finally, and the minimum interval is 0.84Hz.
It should be noted that, the bandwidth of the switch filter bank and the filter selected by the up-conversion module is shown in fig. 3, and will not be described here again.
In the receiving down-conversion module, as shown in fig. 4, the echo signal is connected with a three-one switch filter bank through a limiter and an amplifier, and the three-one switch filter bank is connected with a sixth mixer through a numerical control attenuator; a local oscillation signal output by the frequency source module is connected with the sixth mixer; the sixth mixer is connected with the seventh mixer through a filter, an amplifier and a numerical control attenuator, and the second local oscillation signal output by the frequency source module is connected with the seventh mixer; the seventh mixer is connected with a coupler through an amplifier and a numerical control attenuator, and the coupler outputs a detection signal and adopts an intermediate frequency signal.
The receiving down-conversion module receives an echo signal S1, wherein the echo signal is an 8-18GHz signal, and the bandwidth is 10GHz; mixing the echo signal S1 with a local oscillation signal LO1 to remove the lower sideband and obtain a 2.5-3.5GHz signal; mixing and filtering the 2.5-3.5GHz signal and the two local oscillation signals LO2 to obtain the sampling intermediate frequency signal L2 of 0.1-1 GHz.
The one-out-of-three switching filter bank in fig. 4 is used for image reject filtering; STC and MGC are realized by a digital control attenuator; the LNA is a low noise amplifier.
It should be noted that, the bandwidths of the switch filter bank and the filter selected by the receiving down-conversion module are shown in fig. 4, and are not described herein.
In the power module, as shown in fig. 5, the power module includes a voltage regulator, a power filter, a level shifter, and an FPGA.
The voltage stabilizer is used for converting the input voltage into power required by the receiving down-conversion module, the up-conversion module and the frequency source module.
In fig. 5, LDO is a linear regulator chip, and DCDC is a switching power supply.
The +15V voltage is input, and the +15V voltage is converted into +12V, +5V, -5V, +3.3, +1.8V voltage by using a voltage stabilizer.
The level converter is connected with the FPGA, and the FPGA is used for controlling the receiving down-conversion module, the up-conversion module and the frequency source module.
The voltage required by the level shifter and the FPGA is obtained by converting +15V voltage.
The level converter converts the control signal and sends the control signal to the FPGA, the control signal is output after logic processing of the FPGA, and then the control signal is sent to the frequency source module, the up-conversion module and the receiving down-conversion module after the level converter, so that the control of DDS chip waveforms, channel switching of a switch filter bank, self-adaption of STC and MGC, gain and automatic power compensation in the frequency source module, the up-conversion module and the receiving down-conversion module is realized.
As shown in fig. 2, 3 and 4, the frequency source module, the up-conversion module and the down-conversion module all have detection signals, the detection signals are sent to the FPGA in the power control module, and the detection signals are used as a basis for logic judgment of the FPGA.
It should be noted that, in order to reduce intermodulation products, the mixer IF port power needs to be as low as possible, about-15 dBm, so that the post-stage gain should be ensured.
In summary, the ultra-wideband radar receiving and transmitting front end provided by the embodiment of the invention comprises a receiving down-conversion module, an up-conversion module, a frequency source module and a power supply control module, wherein the frequency source module is used for receiving the down-conversion module and providing local oscillation signals and providing the up-conversion module with the local oscillation signals and ultra-wideband linear frequency modulation signals of 0.1-1.1GHz; the up-conversion module generates a radio frequency signal with 1GHz of any section of instantaneous bandwidth in 8-18GHz according to the local oscillation signal and the ultra-wideband linear frequency modulation signal with 0.1-1.1GHz, and the receiving down-conversion module can receive any section of linear frequency modulation signal with 1GHz bandwidth in the range of 10GHz of the full-time working bandwidth; the problem that the instantaneous working bandwidth of the existing receiving and transmitting front end remains within 300MH is solved; the ultra-wide full-time working bandwidth and the instantaneous working bandwidth are realized, the spurious suppression index of 60dBc can still be achieved, and the index requirements of communication equipment of each large platform can be met.
It should be noted that, if other wideband requirements need to be satisfied, the frequency of the filter may be changed based on the schematic diagrams of the up-conversion module, the receiving down-conversion module and the frequency source module provided in the embodiment of the present invention, for example, the frequency of the filter is changed to implement the working frequency bands of 6-24GHz and 0.3-18 GHz.
It should be noted that: the foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (3)
1. The ultra-wideband radar receiving and transmitting front end is characterized by comprising a receiving down-conversion module, an up-conversion module, a frequency source module and a power supply control module;
the frequency source module comprises a DDS chip, a crystal oscillator, a harmonic generator, a filter, a switch, a power divider, a coupler, an amplifier and a mixer, wherein the local oscillator signal output end and the ultra-bandwidth linear frequency modulation signal end of the frequency source are connected with the up-conversion module, and the local oscillator signal output end of the frequency source module is connected with the receiving down-conversion module;
the up-conversion module comprises a filter, a mixer, an amplifier and a switch;
the receiving down-conversion module comprises a limiter, a numerical control attenuator, a mixer, a filter, an amplifier and a switch;
the power supply control module is respectively connected with the up-conversion module, the down-conversion module and the frequency source module;
the frequency source module is used for providing local oscillation signals for the receiving down-conversion module and providing local oscillation signals and ultra-bandwidth linear frequency modulation signals for the up-conversion module;
the receiving down-conversion module is used for receiving echo signals and performing down-conversion processing on the echo signals to obtain sampling intermediate frequency signals;
the up-conversion module is used for carrying out up-conversion processing on the signals generated by the frequency source module to obtain radio frequency signals;
the power control module is used for controlling the receiving down-conversion module, the up-conversion module and the frequency source module according to a power control signal and supplying power to the receiving down-conversion module, the up-conversion module and the frequency source module;
the frequency source module outputs local oscillation signals, the local oscillation signals comprise a local oscillation signal and two local oscillation signals, the frequency of the local oscillation signal is 11-18GHz, the minimum frequency hopping step of the local oscillation signal is 0.84Hz, and the frequency of the two local oscillation signals is 3.6GHz; the frequency of the ultra-bandwidth linear frequency modulation signal is 0.1-1.1GHz;
at the point of the frequency source module,
the 100M crystal oscillator is connected with a first harmonic generator, the first harmonic generator is connected with a first power divider, a first output end of the first power divider is connected with a first two-by-one switch filter bank, and the first two-by-one switch filter bank is connected with a first mixer through an amplifier;
the first DDS chip is connected with the first mixer through a filter;
the first mixer is connected with a first four-way switch filter bank, and the first four-way switch filter bank is connected with a second mixer through an amplifier;
the second output end of the first power divider is connected with a second harmonic generator through a filter and an amplifier, the output end of the second harmonic generator is connected with a second four-way switch filter bank, and the second four-way switch filter bank is connected with a second mixer through the amplifier;
the second mixer is connected with a second alternative switch filter bank, the second alternative switch filter bank is connected with a first single-pole double-throw switch through an amplifier, a first branch of the first single-pole double-throw switch is connected with a third mixer through the amplifier, and a second branch of the first single-pole double-throw switch is connected with a second branch of the second single-pole double-throw switch;
the third output end of the first power divider is connected with the second power divider through a filter and an amplifier, and the first output end of the second power divider is connected with the first DDS chip;
the second output end of the second power divider is connected with the third mixer;
the third mixer is connected with a third alternative switch filter bank, and the third alternative switch filter bank is connected with the first branch of the second single-pole double-throw switch through an amplifier;
the second single-pole double-throw switch is connected with a coupler through an amplifier, and the coupler outputs the local oscillation signal and the detection signal;
the third output end of the second power divider is connected with a coupler through an amplifier, and the coupler outputs two local oscillation signals and a detection signal;
the fourth output end of the second power divider is connected with a second DDS chip, and the second DDS chip outputs an ultra-bandwidth linear frequency modulation signal;
the first harmonic generator is used for converting 100MHz crystal oscillator frequency multiplication into a first comb spectrum signal, and the switch filter bank is used for converting the first comb spectrum signal into a plurality of low local oscillation signals, wherein the low local oscillation signals comprise 1GHz signals, 3.6GHz signals and 2.7/3.2GHz signals;
converting the 1GHz signal into a second comb spectrum signal by using the second harmonic generator, and converting the second comb spectrum signal into a plurality of high local oscillator signals by using a switch filter bank, wherein the high local oscillator signals are 10/11/15/16GHz signals;
a 3.6GHz signal is taken as a reference clock, the DDS chip is pushed to generate an intermediate frequency signal, the frequency of the intermediate frequency signal is 300-800MHz, and the minimum step is 0.84Hz;
the intermediate frequency signal is mixed with a 2.7/3.2GHz signal, and a 3-4GHz signal is generated through a switch filter;
the 3-4GHz signal is mixed with the 10/11/15/16GHz signal, and 11-15GHz signal is generated through a switch filter;
the 11-15GHz signal is mixed with the 3.6GHz signal, and the local oscillation signal is generated through a switch filter;
the other 3.6GHz signal is used as two local oscillation signals, and the two local oscillation signals are used as a reference clock to push a DDS chip to generate the ultra-bandwidth linear frequency modulation signal;
at the level of the up-conversion module,
the ultra-bandwidth linear frequency modulation signal output by the frequency source module is input into a first filter, and the first filter is connected with a fourth mixer;
the second local oscillation signal output by the frequency source module is input into the fourth mixer, and the fourth mixer is connected with the fifth mixer through an amplifier and a second filter;
a local oscillation signal output by the frequency source module is input into the fifth mixer, and the fifth mixer is connected with a nine-selection one-switch filter bank;
the nine-one switch filter bank is connected with a coupler through an amplifier, and the coupler outputs radio frequency signals and detection signals;
the ultra-bandwidth linear frequency modulation signal and the two local oscillation signals are mixed and filtered to generate a 2.5-3.5GHz signal;
the 2.5-3.5GHz signal is mixed with the local oscillation signal, a radio frequency signal is generated through a nine-selection switch filter bank, the radio frequency signal is a linear frequency modulation signal with an instantaneous bandwidth of 1GHz in 8-18GHz, and the minimum interval of the radio frequency signal is 0.84Hz.
2. The ultra-wideband radar transceiver front end of claim 1, wherein, at the receive down-conversion module,
the echo signal is connected with a three-in-one switch filter bank through a limiter and an amplifier, and the three-in-one switch filter bank is connected with a sixth mixer through a numerical control attenuator;
a local oscillation signal output by the frequency source module is connected with the sixth mixer;
the sixth mixer is connected with a seventh mixer through a filter, an amplifier and a numerical control attenuator, and the two local oscillation signals output by the frequency source module are connected with the seventh mixer;
the seventh mixer is connected with a coupler through an amplifier and a numerical control attenuator, and the coupler outputs detection signals and adopts intermediate frequency signals;
mixing the echo signal with the local oscillation signal to remove sidebands, and obtaining a 2.5-3.5GHz signal;
and mixing and filtering the 2.5-3.5GHz signal and the two local oscillation signals to obtain a sampling intermediate frequency signal of 0.1-1 GHz.
3. The ultra-wideband radar transceiver front-end of claim 1, wherein the power control module comprises a voltage regulator, a power filter, a level shifter, and an FPGA;
the voltage stabilizer is used for converting input voltage into voltage required by the receiving down-conversion module, the up-conversion module and the frequency source module;
the level shifter is connected with the FPGA, and the FPGA is used for controlling the receiving down-conversion module, the up-conversion module and the frequency source module.
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| CN114401019B (en) * | 2021-11-29 | 2023-09-12 | 北京无线电计量测试研究所 | High-bandwidth high-sensitivity receiving front-end circuit |
| CN114389636B (en) * | 2022-01-13 | 2024-01-05 | 中国人民解放军96901部队25分队 | Multi-band high-performance signal processing platform |
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