CN108682726B - Light emitting diode, chip thereof, manufacturing method thereof and light emitting method of chip - Google Patents
Light emitting diode, chip thereof, manufacturing method thereof and light emitting method of chip Download PDFInfo
- Publication number
- CN108682726B CN108682726B CN201810478979.1A CN201810478979A CN108682726B CN 108682726 B CN108682726 B CN 108682726B CN 201810478979 A CN201810478979 A CN 201810478979A CN 108682726 B CN108682726 B CN 108682726B
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- transparent conductive
- type semiconductor
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 claims abstract description 171
- 238000002161 passivation Methods 0.000 claims abstract description 126
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 238000010030 laminating Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 8
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 446
- 239000011241 protective layer Substances 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 22
- 230000008569 process Effects 0.000 description 17
- 230000000903 blocking effect Effects 0.000 description 13
- 238000009826 distribution Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a light emitting diode, a chip thereof, a manufacturing method thereof and a light emitting method of the chip, wherein the chip comprises a substrate, an N-type semiconductor layer, an active region, a P-type semiconductor layer, a transparent conducting layer and a passivation protective layer which are sequentially stacked, wherein the passivation protective layer is provided with a plurality of holes which respectively correspond to different positions of the transparent conducting layer, a part of a P-type electrode is electrically connected to the transparent conducting layer after penetrating through the holes, and an N-type electrode is electrically connected to the N-type semiconductor layer.
Description
Technical Field
The present invention relates to an LED chip, and more particularly, to an LED, a chip thereof, a method for manufacturing the LED, and a method for emitting light from the chip.
Background
Since Light-Emitting diodes (LEDs) have the advantages of high brightness, long lifetime, small volume, and low energy consumption, they are considered as a new generation of lighting tools. However, at present, the chip of the light emitting diode still has a problem of low light emitting efficiency, and therefore, how to improve the light emitting efficiency of the chip of the light emitting diode and solve a series of problems generated in the process of improving the light emitting efficiency of the chip of the light emitting diode have become one of the most important research topics.
Fig. 1 to 7B show a conventional led chip, wherein the chip includes a substrate 10P, an epitaxial structure 20P, a current blocking layer 30P, a transparent conductive layer 40P, a metal electrode set 50P and a passivation protection layer 60P, and has an N-type layer exposed portion 70P. The epitaxial structure 20P includes an N-type semiconductor layer 21P, an active region 22P and a P-type semiconductor layer 23P, wherein the N-type semiconductor layer 21P, the active region 22P and the P-type semiconductor layer 23P are sequentially grown from the substrate 10P, so that the substrate 10P and the N-type semiconductor layer 21P, the active region 22P and the P-type semiconductor layer 23P of the epitaxial structure 20P are sequentially stacked. The existing manufacturing process of the chip is as follows:
(a) forming a first photoresist layer on the P-type semiconductor layer 23P of the epitaxial structure 20P, performing dry etching on the epitaxial structure 20P to form the N-type layer exposed portion 70P extending from the P-type semiconductor layer 23P to the N-type semiconductor layer 21P through the active region 22P, so as to expose a portion of the N-type semiconductor layer 21P, and removing the first photoresist layer, referring to fig. 3A and 3B;
(b) forming a second photoresist layer on the P-type semiconductor layer 23P of the epitaxial structure 20P, performing wet etching on the epitaxial structure 20P, forming the current blocking layer 30P stacked on the P-type semiconductor layer 23P on the epitaxial structure 20P, and removing the second photoresist layer, with reference to fig. 4A and 4B;
(c) forming the P-type semiconductor layer 23P stacked on the epitaxial structure 20P and the transparent conductive layer 40P covering the current blocking layer 30P, forming a third photoresist layer on the transparent conductive layer 40P, etching the transparent conductive layer 40P to remove a partial region of the transparent conductive layer 40P, thereby exposing a portion of the current blocking layer 30P, and removing the third photoresist layer, referring to fig. 5A and 5B;
(d) forming a fourth photoresist layer on the transparent conductive layer 40P, and forming a P-type electrode 51P and an N-type electrode 52P of the metal electrode group 50P on the transparent conductive layer 40P and the N-type semiconductor layer 21P, respectively, wherein the P-type electrode 51P is electrically connected to the transparent conductive layer 40P, the N-type electrode 52P is electrically connected to the N-type semiconductor layer 21P, and removing the fourth photoresist layer, referring to fig. 6A and 6B; and
(e) fabricating the passivation protection layer 60P on the P-type electrode 51P and the N-type electrode 52P, forming a fifth photoresist layer on the passivation protection layer 60P, etching the passivation protection layer 60P to expose a portion of the P-type electrode 51P and a portion of the N-type electrode 52P, and removing the fifth photoresist layer to obtain the chip, referring to fig. 7A and 7B.
There are still a number of drawbacks that are carried in the existing chips. First, the chip needs to grow the current blocking layer 30P on the P-type semiconductor layer 23P of the epitaxial structure 20P, which not only increases the material manufacturing and size thickness of the chip, but also prolongs the manufacturing process of the chip to affect the productivity of the chip, thereby increasing the production cost of the chip. Secondly, the adhesion between the P-type electrode 51P and the transparent conductive layer 40P is weak, and the P-type electrode 51P and the transparent conductive layer 40P cannot be in complete contact with each other, and it is necessary to design openings for the P-type electrode 51P and the transparent conductive layer 40P, resulting in an increase in the cost of the chip. In addition, at the edge of the chip, the current blocking layer 30P isolates the P-type electrode 51P from the transparent conductive layer 40P, so that almost no current is injected at the edge of the chip, and further, the edge of the chip emits weak light to affect the light emitting efficiency of the chip.
Disclosure of Invention
An object of the present invention is to provide a light emitting diode and a chip thereof, a method of manufacturing the same, and a method of emitting light from the chip, in which the light emitting efficiency of the chip can be greatly improved.
An object of the present invention is to provide a light emitting diode, a chip thereof, a method of manufacturing the same, and a method of emitting light from the chip, wherein a current of the chip can be uniformly distributed, which is advantageous for improving reliability of the chip.
An object of the present invention is to provide a light emitting diode and a chip thereof, a method for manufacturing the same, and a method for emitting light from the chip, wherein the photolithography process of the chip can be reduced, thereby facilitating the improvement of the productivity of the chip and the reduction of the production cost of the chip.
An object of the present invention is to provide a light emitting diode, a chip thereof, a method for manufacturing the same, and a method for emitting light from the chip, wherein a first photolithography process is performed after a transparent conductive substrate is stacked on an epitaxial structure of the chip, so that the transparent conductive substrate forms a transparent conductive layer stacked on the epitaxial structure, and in this way, the formation of the transparent conductive layer and the exposure of an N-type semiconductor layer of the epitaxial structure can be performed in the same photolithography process, and the chip of the present invention has a lower production cost compared to the prior art chip processes.
An object of the present invention is to provide a light emitting diode, a chip thereof, a method for manufacturing the same, and a method for emitting light from the chip, wherein the chip provides a passivation layer, and the passivation layer is stacked on the transparent conductive layer, wherein the passivation layer not only can block current, but also can improve a lateral current spreading effect, so that the current distribution of the chip is more uniform, thereby facilitating to improve the light efficiency of the chip.
An object of the present invention is to provide a light emitting diode, a chip thereof, a method for manufacturing the same, and a method for emitting light from the chip, wherein an electrode of the chip is formed after a passivation layer is formed, so that the passivation layer has an effect of blocking current due to being directly stacked on a transparent conductive layer, and thus, compared with a chip in the prior art, the chip of the present invention does not need a specially configured current blocking layer, which is not only beneficial to reducing the material cost of the chip, but also beneficial to reducing a photolithography process and shortening a production line of the chip, thereby being beneficial to reducing the production cost of the chip and reducing the thickness dimension of the chip.
An object of the present invention is to provide a light emitting diode, a chip thereof, a method for manufacturing the same, and a method for emitting light from the chip, wherein the passivation layer provides an array of holes to allow electrodes to be electrically connected to the transparent conductive layer, so that the chip can emit light in a dot manner at the holes of the passivation layer, thereby improving the brightness of the chip.
An object of the present invention is to provide a light emitting diode, a chip and a method for manufacturing the same, and a method for emitting light from the chip, wherein a P-type electrode of the chip has an array-type finger, and the fingers of the P-type electrode are formed in the hole of the passivation layer when the P-type electrode is formed on the passivation layer, so that when an operating voltage is applied to the P-type electrode, a current can be supplied to the transparent conductive layer from different positions of the transparent conductive layer through the fingers of the P-type electrode, thereby facilitating a more uniform current distribution of the chip.
According to one aspect of the present invention, the present invention provides a chip of a light emitting diode, comprising:
a substrate;
an epitaxial structure, wherein the epitaxial structure comprises an N-type semiconductor layer, an active region and a P-type semiconductor layer, wherein the substrate, the N-type semiconductor layer, the active region and the P-type semiconductor layer are sequentially stacked;
a transparent conductive layer, wherein the transparent conductive layer is laminated on the P-type semiconductor layer of the epitaxial structure;
a passivation layer, wherein the passivation layer has a plurality of holes, wherein the passivation layer is stacked on the transparent conductive layer, and the holes of the passivation layer correspond to different positions of the transparent conductive layer respectively; and
an electrode assembly, wherein said electrode assembly comprises an N-type electrode and a P-type electrode, wherein said N-type electrode is electrically connected to said N-type semiconductor layer of said epitaxial structure, and a portion of said P-type electrode is electrically connected to said transparent conductive layer of said epitaxial structure after passing through said holes of said passivation layer.
According to an embodiment of the invention, the chip has an N-type layer exposed portion, and the N-type layer exposed portion extends from the passivation protection layer to the N-type semiconductor layer of the epitaxial structure through the transparent conductive layer and the P-type semiconductor layer and the active region of the epitaxial structure, so that a portion of the N-type semiconductor layer is exposed at the N-type layer exposed portion.
According to an embodiment of the present invention, the N-type electrode of the electrode group is electrically connected to the N-type semiconductor layer in such a manner that the N-type electrode is formed on the N-type semiconductor layer of the epitaxial structure.
According to an embodiment of the present invention, the P-type electrode of the electrode group is electrically connected to the P-type semiconductor layer of the epitaxial structure in such a manner that the P-type electrode is formed on the passivation protection layer.
According to an embodiment of the present invention, the P-type electrode has a plurality of fingers, wherein the fingers of the P-type electrode are formed in the holes of the passivation layer, and the fingers of the P-type electrode are electrically connected to the transparent conductive layer at different positions of the transparent conductive layer, respectively.
According to one embodiment of the invention, the fingers of the P-type electrode include a first set of fingers and a second set of fingers, the first and second sets of fingers extending from the second end to the first end of the chip, respectively, along the edge of the chip.
According to one embodiment of the invention, the fingers of the P-type electrode include a first set of fingers, a second set of fingers, and a third set of fingers, the first and second sets of fingers extending along the edge of the chip from the second end to the first end of the chip, respectively, the third set of fingers being held at the second end of the chip.
According to an embodiment of the invention, the substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate.
According to an embodiment of the present invention, the N-type semiconductor layer and the P-type semiconductor layer of the epitaxial structure are each a gallium nitride layer.
In another aspect of the present invention, the present invention further provides a light emitting diode, including:
a package body;
an electrode pin group, wherein the electrode pin group comprises an N-type electrode pin and a P-type electrode pin; and
at least one chip, wherein the chip further comprises:
a substrate;
an epitaxial structure, wherein the epitaxial structure comprises an N-type semiconductor layer, an active region and a P-type semiconductor layer, wherein the substrate, the N-type semiconductor layer, the active region and the P-type semiconductor layer are sequentially stacked;
a transparent conductive layer, wherein the transparent conductive layer is laminated on the P-type semiconductor layer of the epitaxial structure;
a passivation layer, wherein the passivation layer has a plurality of holes, wherein the passivation layer is stacked on the transparent conductive layer, and the holes of the passivation layer correspond to different positions of the transparent conductive layer respectively; and
an electrode assembly, wherein said electrode assembly comprises an N-type electrode and a P-type electrode, wherein said N-type electrode is electrically connected to said N-type semiconductor layer of said epitaxial structure, and a portion of said P-type electrode is electrically connected to said transparent conductive layer of said epitaxial structure after passing through said holes of said passivation layer;
the chip is packaged in the package body, the N-type electrode pin and the P-type electrode pin are electrically connected to the N-type electrode and the P-type electrode of the chip respectively, and the N-type electrode pin and the P-type electrode pin extend from the inside to the outside of the package body respectively.
According to an embodiment of the present invention, the size of the P-type electrode pin is gradually decreased from the connection end to the free end of the P-type electrode pin.
According to another aspect of the present invention, the present invention further provides a method for manufacturing a chip of a light emitting diode, wherein the method for manufacturing the chip comprises the following steps:
(a) sequentially growing an N-type semiconductor layer, an active region and a P-type semiconductor layer on a substrate;
(b) forming a transparent conductive layer laminated on the P-type semiconductor layer, and forming an N-type hole extending from the transparent conductive layer to the N-type semiconductor layer through the P-type semiconductor layer and the active region;
(c) laminating a passivation protection layer with a plurality of holes on the transparent conductive layer, so that the holes of the passivation protection layer respectively correspond to different positions of the transparent conductive layer; and
(d) and electrically connecting an N-type electrode to the N-type semiconductor layer, and electrically connecting a P-type electrode to the P-type semiconductor layer through the holes of the passivation protective layer.
According to an embodiment of the present invention, the step (b) further comprises the steps of:
laminating a transparent conductive base layer on the P-type semiconductor layer;
laminating a first photoresist layer on the transparent conductive base layer; and
and etching the preset positions of the first photoresist layer, the transparent conductive base layer, the P-type semiconductor layer and the active region to simultaneously form the N-type hole and the transparent conductive layer.
According to an embodiment of the present invention, the step (b) further comprises the steps of:
laminating a transparent conductive base layer on the P-type semiconductor layer;
laminating a first photoresist layer on the transparent conductive base layer; and
etching the first photoresist layer, the transparent conductive base layer, the P-type semiconductor layer, the active region and the preset position of the N-type semiconductor layer to simultaneously form the N-type hole and the transparent conductive layer.
According to an embodiment of the present invention, in the above method, the transparent conductive base layer is stacked on the P-type semiconductor layer by evaporation.
According to an embodiment of the present invention, in the step (c), while forming a passivation protection layer stacked on the transparent conductive layer, an N-type layer exposed portion extending from the passivation protection layer to the N-type semiconductor layer through the transparent conductive layer, the P-type semiconductor layer and the active region is formed at a position corresponding to the N-type hole.
According to an embodiment of the present invention, the step (c) further comprises the steps of:
laminating a passivation protection base layer on the transparent conductive layer;
laminating a second photoresist layer on the passivation protection base layer; and
and removing the positions of the second photoresist layer and the passivation protection base layer corresponding to the N-type hole so as to simultaneously form the passivation protection layer and the exposed part of the N-type layer.
According to an embodiment of the present invention, in the step (d), a plurality of fingers extending from one side to the other side of the passivation layer through the holes of the passivation layer are formed at the same time when the P-type electrode is formed on the passivation layer, wherein the fingers are electrically connected to the transparent conductive layer at different positions of the transparent conductive layer.
According to another aspect of the present invention, the present invention further provides a light emitting method of a chip of a light emitting diode, wherein the light emitting method comprises the steps of:
(A) providing current to a transparent conductive layer at a plurality of different positions respectively so as to enable the current to be uniformly distributed on the transparent conductive layer; and
(B) and applying voltage to the active region through a P-type semiconductor layer and an N-type semiconductor layer at two sides of the active region respectively to enable the active region to generate light and emit light, wherein the transparent conductive layer is laminated on the P-type semiconductor layer.
According to an embodiment of the present invention, in the above method, currents are respectively supplied to the transparent conductive layer at both sides of the chip so that the currents are uniformly distributed in the transparent conductive layer.
According to an embodiment of the present invention, in the above method, currents are respectively supplied to the transparent conductive layer at both sides and one end portion of the chip so that the currents are uniformly distributed in the transparent conductive layer.
Drawings
Fig. 1 is a schematic view of a substrate of a chip of the prior art, illustrating a cross-sectional state of the substrate.
Fig. 2 is a schematic diagram of one of the chip manufacturing processes of the prior art, which illustrates a cross-sectional state after an epitaxial structure is grown on the substrate.
Fig. 3A is a schematic diagram of a second manufacturing process of the chip in the prior art, which illustrates a cross-sectional view of an N-type layer exposed on the epitaxial structure.
Fig. 3B is a schematic diagram of a second manufacturing process of the chip in the prior art, which illustrates a top view of the N-type layer exposed portion formed on the epitaxial structure.
Fig. 4A is a schematic diagram of a third process of manufacturing the chip in the prior art, which illustrates a cross-sectional view of a current blocking layer formed on the epitaxial structure.
Fig. 4B is a schematic diagram of a third manufacturing process of the chip in the prior art, which illustrates a top view of the current blocking layer formed on the epitaxial structure.
Fig. 5A is a diagram illustrating a fourth process of manufacturing the chip in the prior art, which shows a cross-sectional view of a transparent conductive layer formed on the epitaxial structure.
Fig. 5B is a diagram illustrating a fourth manufacturing process of the chip in the prior art, which illustrates a top view of the transparent conductive layer formed on the epitaxial structure.
Fig. 6A is a schematic diagram of a fifth manufacturing process of the chip in the prior art, which illustrates a cross-sectional view of forming a P-type electrode on the transparent conductive layer and forming an N-type electrode on the epitaxial structure.
Fig. 6B is a schematic diagram of a fifth manufacturing process of the chip in the prior art, which illustrates a top view of forming the P-type electrode on the transparent conductive layer and forming the N-type electrode on the epitaxial structure.
Fig. 7A is a schematic diagram of a sixth manufacturing process of the chip in the prior art, which illustrates a cross-sectional view of a passivation layer formed on the P-type electrode and the N-type electrode.
Fig. 7B is a schematic diagram of a sixth manufacturing process of the chip in the prior art, which illustrates a top view state of forming the passivation protection layer on the P-type electrode and the N-type electrode.
FIG. 8 is a schematic diagram of one of the processes for manufacturing a chip according to a preferred embodiment of the invention, showing a cross-sectional view of a substrate of the chip.
Fig. 9 is a schematic diagram of a second manufacturing process of the chip according to the above preferred embodiment of the invention, which illustrates a cross-sectional view of stacking an epitaxial structure on the substrate.
Fig. 10 is a schematic diagram of a third process of manufacturing the chip according to the above preferred embodiment of the present invention, which illustrates a cross-sectional view of a transparent conductive substrate layer laminated on the epitaxial structure.
Fig. 11 is a schematic diagram of a fourth process of manufacturing the chip according to the above preferred embodiment of the invention, which illustrates a cross-sectional view of a first photoresist layer laminated on the transparent conductive base layer.
Fig. 12A is a schematic diagram of a fifth manufacturing process of the chip according to the above preferred embodiment of the invention, which illustrates a cross-sectional view of a transparent conductive layer and an N-type layer exposed portion formed on the epitaxial structure, at which time the first photoresist layer is removed.
Fig. 12B is a schematic diagram of a fifth manufacturing process of the chip according to the above preferred embodiment of the invention, which illustrates a top view of the transparent conductive layer and the exposed portion of the N-type layer formed on the epitaxial structure, at which time the first photoresist layer is removed.
Fig. 13 is a schematic diagram of a sixth manufacturing process of the chip according to the above preferred embodiment of the present invention, which illustrates a cross-sectional view of a passivation protection base layer stacked on the transparent conductive layer and the epitaxial structure.
Fig. 14 is a schematic view of a seventh process for manufacturing the chip according to the above preferred embodiment of the present invention, which illustrates a cross-sectional view of a second photoresist layer laminated on the passivation protection base layer.
Fig. 15A is a schematic view of an eighth manufacturing process of the chip according to the above preferred embodiment of the present invention, which illustrates a cross-sectional view of a passivation layer formed on the transparent conductive layer and the epitaxial structure, wherein the second photoresist layer is removed.
Fig. 15B is a schematic diagram of an eighth manufacturing process of the chip according to the above preferred embodiment of the present invention, which illustrates a top view of the passivation layer formed on the transparent conductive layer and the epitaxial structure, at which time the second photoresist layer is removed.
Fig. 16A is a diagram illustrating a ninth process of manufacturing the chip according to the above preferred embodiment of the present invention, which shows a cross-sectional view of forming a P-type electrode and an N-type electrode on the passivation layer and the epitaxial structure, respectively.
Fig. 16B is a diagram illustrating a ninth manufacturing process of the chip according to the above preferred embodiment of the invention, which illustrates a top view of the P-type electrode and the N-type electrode formed on the passivation layer and the epitaxial structure, respectively.
Fig. 17A is a schematic cross-sectional view of the chip according to the above preferred embodiment of the invention, which illustrates the current flow direction of the chip.
Fig. 17B is a top view of the chip according to the above preferred embodiment of the present invention, which illustrates the current flow direction of the chip.
Fig. 18A is a schematic cross-sectional view of a chip according to a modified implementation of the above preferred embodiment of the invention.
Fig. 18B is a schematic top view of the chip according to the above modified embodiment of the preferred embodiment of the present invention.
Fig. 19A is a schematic cross-sectional view of the chip according to the above modified implementation of the above preferred embodiment of the invention, which illustrates the current flow direction of the chip.
Fig. 19B is a schematic top view of the chip according to the above modified embodiment of the preferred embodiment of the present invention, which illustrates the current flow direction of the chip.
FIG. 20 is a schematic diagram of a light emitting diode according to a preferred embodiment of the invention.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be constructed and operated in a particular orientation and thus are not to be considered limiting.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
Referring to fig. 8 to 17B of the drawings of the present specification, a chip 100 of a light emitting diode according to a preferred embodiment of the present invention is disclosed and described in the following description, wherein the chip 100 includes a substrate 10, an epitaxial structure 20, a transparent conductive layer 30, a passivation layer 40 and an electrode assembly 50.
Specifically, the epitaxial structure 20 includes an N-type semiconductor layer 21, an active region 22, and a P-type semiconductor layer 23, wherein the substrate 10, the N-type semiconductor layer 21, the active region 22, the P-type semiconductor layer 23, the transparent conductive layer 30, and the passivation layer 40 are sequentially stacked, and the transparent conductive layer 30 is electrically connected to the P-type semiconductor layer 23 of the epitaxial structure 20. The electrode set 50 includes an N-type electrode 51 and a P-type electrode 52, wherein the N-type electrode 51 is electrically connected to the N-type semiconductor layer 21 of the epitaxial structure 20, and the P-type electrode 52 is electrically connected to the transparent conductive layer 30. An external voltage can be applied to the N-type semiconductor layer 21 and the P-type semiconductor layer 23 through the N-type electrode 51 and the P-type electrode 52 of the electrode group 50, respectively, so that a current can generate light while flowing through the active region 22 of the epitaxial structure 20. Preferably, the active region 22 is a quantum well light emitting layer. At least one of the N-type semiconductor layer 21 and the P-type semiconductor layer 23 may be, but is not limited to, a gallium nitride layer.
In this preferred example of the chip 100 of the present invention, the N-type electrodes 51 and the P-type electrodes 52 of the electrode group 50 are located on the same side of the chip 100. That is, an external voltage can be applied to the N-type semiconductor layer 21 and the P-type semiconductor layer 23 through the N-type electrode 51 and the P-type electrode 52 of the electrode group 50 on the same side of the chip 100, respectively, so that a current can generate light while flowing through the active region 22 of the epitaxial structure 20. Specifically, the chip 100 has an N-type layer exposed portion 60, wherein the N-type layer exposed portion 60 extends from the passivation layer 40 to the N-type semiconductor layer 21 through the transparent conductive layer 30, the P-type semiconductor layer 23 and the active region 22, and the N-type electrode 51 is electrically connected to the N-type semiconductor layer 21 in such a manner that the N-type electrode 51 is held in the N-type layer exposed portion 60.
Referring to fig. 16A and 16B, the passivation layer 40 has a set of holes 41, the holes 41 are distributed in an array, and the holes 41 of the passivation layer 40 correspond to different positions of the transparent conductive layer 30 respectively. Accordingly, the P-type electrode 52 of the electrode assembly 50 has a set of fingers 521, and the fingers 521 of the P-type electrode 52 are formed in the holes 41 of the passivation layer 40 when the P-type electrode 52 is formed on the passivation layer 40. That is, the fingers 521 of the P-type electrode 52 can extend from one side of the passivation layer 40 to the other side of the passivation layer 40 through the holes 41 of the passivation layer 40, and the fingers 521 of the P-type electrode 52 are electrically connected to the transparent conductive layer 30, respectively, in such a way that the chip 100 can realize point-type light emission at the holes 41 of the passivation layer 40, thereby improving the brightness of the chip 100.
More importantly, the P-type electrode 52 is electrically connected to the transparent conductive layer 30 by providing the finger elements 521, so that when an operating voltage is applied to the P-type electrode 52 and the N-type electrode 51, a current can be supplied to the transparent conductive layer 30 from different positions of the transparent conductive layer 30 through the finger elements 521 of the P-type electrode 52, and in this way, the current distribution of the chip 100 is more uniform, which is particularly advantageous for improving the uniformity of light emission at various positions of the active region 22 of the chip 100 and particularly advantageous for improving the light emission efficiency of the chip 100.
Fig. 8 to 16B further illustrate the manufacturing process of the chip 100. In particular, at the stage illustrated in fig. 8, the substrate 10 is provided, wherein the type of the substrate 10 is not limited in the chip 100 of the invention, which is selected as required. For example, the substrate 10 of the chip 100 may be, but is not limited to, a sapphire substrate, a silicon carbide substrate, or the like.
At the stage shown in fig. 9, the N-type semiconductor layer 21, the active region 22, and the P-type semiconductor layer 23 of the epitaxial structure 20 are sequentially grown on the substrate 10, so that the substrate 10 and the N-type semiconductor layer 21, the active region 22, and the P-type semiconductor layer of the epitaxial structure 20 are sequentially stacked.
It should be noted that the manner of sequentially growing the N-type semiconductor layer 21, the active region 22 and the P-type semiconductor layer 23 of the epitaxial structure 20 on the substrate 10 is not limited in the chip 100 of the present invention, for example, in a preferred example of the chip 100 of the present invention, the N-type semiconductor layer 21, the active region 22 and the P-type semiconductor layer 23 of the epitaxial structure 20 may be sequentially grown on the substrate 10 by using a Metal-organic Chemical Vapor Deposition (MOCVD), so that the N-type semiconductor layer 21 is stacked on the substrate 10, the active region 22 is stacked on the N-type semiconductor layer 21 and the P-type semiconductor layer 23 is stacked on the active region 22.
At the stage shown in fig. 10 to fig. 12B, the transparent conductive layer 30 is first stacked on the P-type semiconductor layer 23 of the epitaxial structure 20, and then the transparent conductive layer 30 and the P-type semiconductor layer 23 and the active region 22 of the epitaxial structure 20 are etched to form an N-type hole 101, so that the N-type semiconductor layer 21 of the epitaxial structure 20 is exposed to the N-type hole 101.
It should be noted that, in a preferred example of the chip 100 of the present invention, only predetermined positions of the transparent conductive layer 30 and the P-type semiconductor layer 23 and the active region 22 of the epitaxial structure 20 are etched to form the N-type hole 101, so as to expose the N-type semiconductor layer 21 of the epitaxial structure 20 to the N-type hole 101. In another preferred example of the chip 100 of the present invention, the transparent conductive layer 30 and the P-type semiconductor layer 23, the active region 22 and the N-type semiconductor layer 21 of the epitaxial structure 20 are etched at predetermined positions, and only a portion of the thickness of the N-type semiconductor layer 21 is etched to form the N-type hole 101, so that the N-type semiconductor layer 21 of the epitaxial structure 20 is exposed to the N-type hole 101.
Specifically, at the stage shown in fig. 10, a transparent conductive base layer 102 is first stacked on the P-type semiconductor layer 23 of the epitaxial structure 20, at the stage shown in fig. 11, a first photoresist layer 103 is stacked on the transparent conductive base layer 102, and at the stage shown in fig. 12A and 12B, the first photoresist layer 103, the transparent conductive base layer 102, the P-type semiconductor layer 23, the active region 22, and a portion of the N-type semiconductor layer 21 are sequentially etched to form the N-type hole 101, so as to expose a portion of the N-type semiconductor layer 21, at which time, the transparent conductive base layer 102 forms the transparent conductive layer 30 stacked on the P-type semiconductor layer 23. It is understood that the N-type hole 101 extends from the transparent conductive layer 30 to the N-type semiconductor layer 21 through the P-type semiconductor layer 23 and the active region 22, so that a portion of the N-type semiconductor layer 21 is exposed. After the N-type hole 101 is formed, the first photoresist layer 103 is removed.
In a preferred example of the chip 100 of the present invention, at the stage shown in fig. 10, the transparent conductive base layer 102 is stacked on the P-type semiconductor layer 23 of the epitaxial structure 20 by evaporation. Of course, it should be understood by those skilled in the art that the manner of laminating the transparent conductive base layer 102 on the P-type semiconductor layer 23 of the epitaxial structure 20 is not limited to an evaporation process, for example, in other possible examples of the chip 100 of the present invention, the transparent conductive base layer 102 may also be laminated on the P-type semiconductor layer 23 of the epitaxial structure 20 in a deposition manner.
Unlike the prior art process of manufacturing the chip 100 in which the epitaxial structure is etched to expose the N-type semiconductor layer and then the transparent conductive layer is stacked on the P-type semiconductor layer of the epitaxial structure, in the manufacturing process of the chip 100 of the present invention, the transparent conductive base layer 102 is first stacked on the P-type semiconductor layer 23 of the epitaxial structure 20, and then the transparent conductive base layer 102 and the P-type semiconductor layer 23, the active region 22 and the N-type semiconductor layer 21 of the epitaxial structure 20 are etched to simultaneously form the N-type hole 101 for exposing a portion of the N-type semiconductor layer 21 and the transparent conductive layer 30 stacked on the P-type semiconductor layer 23, the photolithographic process of the chip 100 during its fabrication may be reduced, in this way, the production line of the chip 100 may be shortened to improve the production of the chip 100 and reduce the production cost of the chip 100.
At the stage shown in fig. 13 to fig. 15B, the passivation layer 40 is first stacked on the transparent conductive layer 30 and the N-type semiconductor layer 21, and then the predetermined position of the passivation layer 40 is removed to form the N-type exposed portion 60 and the holes 41 in the form of an array of the passivation layer 40. That is, the N-type layer exposed portion 60 extends from the passivation protection layer 40 to the N-type semiconductor layer 21 through the transparent conductive layer 30, the P-type semiconductor layer 23 and the active region 22, so that a portion of the N-type semiconductor layer 21 is exposed.
Specifically, a passivation protection base layer 104 is first stacked on the transparent conductive layer 30 and the N-type semiconductor layer 21 at the stage shown in fig. 13, a second photoresist layer 105 is stacked on the passivation protection base layer 104 at the stage shown in fig. 14, and then a predetermined position of the passivation protection base layer 104 is removed at the stage shown in fig. 15A and 15B to form the passivation protection layer 40 stacked on the transparent conductive layer 30, the N-type layer exposed portion 60 for exposing the N-type semiconductor layer 21, and the holes 41 in the form of an array of the passivation protection layer 40. After the passivation layer 40, the hole 41 of the passivation layer 40, and the N-type layer exposed portion 60 are formed, the second photoresist layer 105 is removed.
Unlike the prior art chip 100 in which the passivation layer is stacked on the P-type electrode and the P-type electrode separates the passivation layer from the transparent conductive layer, in the chip 100 of the present invention, the passivation layer 40 is directly stacked on the transparent conductive layer 30, so that the passivation layer 40 can not only block current, but also improve the lateral current spreading effect, thereby making the current distribution of the chip 100 more uniform, which is particularly important for improving the light emitting uniformity of each part of the chip 100 and improving the light efficiency of the chip 100.
In addition, in the chip 100 of the present invention, the passivation layer 40 is directly stacked on the transparent conductive layer 30, so that the passivation layer 40 can be used for blocking current, and thus, the chip 100 of the present invention does not need to have a specific current blocking layer as in the conventional chip 100, and thus, the manner that the chip 100 of the present invention directly stacks the passivation layer 40 on the transparent conductive layer 30 to block current can not only reduce the material manufacturing of the chip 100, but also reduce a photolithography process for manufacturing the current blocking layer and shorten a production line of the chip 100, thereby facilitating to improve the productivity of the chip 100, reduce the production cost of the chip 100, and reduce the thickness dimension of the chip 100.
At the stage shown in fig. 16A and 16B, the N-type electrode 51 is formed on the N-type layer exposed portion 60 of the chip 100, so that the N-type electrode 51 is electrically connected to the N-type semiconductor layer 21 of the epitaxial structure 20. The P-type electrode 52 is fabricated on the transparent conductive layer 30 and the passivation protection layer 40 such that the P-type electrode 52 is electrically connected to the transparent conductive layer 30, thereby fabricating the chip 100.
It should be noted that when the P-type electrode 52 is fabricated on the transparent conductive layer 30 and the passivation layer 40, the P-type electrode 52 forms the finger elements 521 in the holes 41 of the passivation layer 40, so that the finger elements 521 of the P-type electrode 52 are electrically connected to different positions of the transparent conductive layer 30 by extending from one side of the passivation layer 40 to the other side of the passivation layer 40 through the holes 41 of the passivation layer 40. Since the holes 41 of the passivation layer 40 are arranged in an array, and thus the fingers 521 of the P-type electrode 52 are also arranged in an array, when an operating voltage is applied to the P-type electrode 52 and the N-type electrode 51, a current can be supplied to the transparent conductive layer 30 from different positions of the transparent conductive layer 30 through the fingers 521 of the P-type electrode 52, in this way, the current distribution of the chip 100 is more uniform, which is particularly advantageous for improving the light emitting uniformity of the chip 100 at various positions of the active region 22 and particularly advantageous for improving the light emitting efficiency of the chip 100. Fig. 17A and 17B show the current trend after the operating voltage is applied to the P-type electrode 52 and the N-type electrode 51, wherein when the current flows along the P-type electrode 52 from the left side to the right side of fig. 17A and 17B, the current also flows along the fingers 521 of the P-type electrode 52 from the top of fig. 17A to the bottom of the transparent conductive layer 30, because the fingers 521 of the P-type electrode 52 are distributed in an array, so that the current can flow to the transparent conductive layer 30 at different positions of the transparent conductive layer 30, and thus, the chip 100 can realize dot light emission at the holes 41 of the passivation layer 40, which is beneficial for improving the brightness of the chip 100.
Fig. 18A and 18B show a modified embodiment of the chip 100, different from the chip 100 shown in fig. 16A and 16B, in the preferred example of the chip 100 shown in fig. 18A and 18B, some of the holes 41 of the passivation layer 40 are formed at the edge position of the chip 100, for example, some of the holes 41 of the passivation layer 40 are formed at the left side of fig. 18A and 18B, so that some of the fingers 521 of the P-type electrode 52 are also formed at the edge position of the chip 100, so that in fig. 19A and 19B, when an operating voltage is applied to the P-type electrode 52 and the N-type electrode 51, a current flows along the P-type electrode 52 from the left side to the right side of fig. 19A and 19B, a current also flows along the fingers 521 of the P-type electrode 52 from the upper side of fig. 17A to the lower side of the transparent conductive layer 30, since the fingers 521 of the P-type electrode 52 are arranged in an array, on one hand, current can flow to the transparent conductive layer 30 at different positions of the transparent conductive layer 30, and on the other hand, since the P-type electrode 52 also forms the fingers 521 at the edge of the transparent conductive layer 30, current can be provided to the transparent conductive layer 30 at the edge of the transparent conductive layer 30, in this way, current can be provided to the transparent conductive layer 30 at the middle and edge of the transparent conductive layer 30, so as to improve the uniformity of light emission of the chip 100 at various positions, and the chip 100 can realize point light emission at the holes 41 of the passivation layer 40, so as to improve the brightness of the chip 100.
More specifically, in the preferred example of the chip 100 shown in fig. 16A and 16B, the N-type electrode 51 extends from the first end to the second end of the chip 100 in the middle of the chip 100, and the finger elements 521 of the P-type electrode 52 form a first group of finger elements 5211 and a second group of finger elements 5212, wherein the first group of finger elements 5211 and the second group of finger elements 5212 extend from the second end to the first end of the chip 100 at the edge of the chip 100, respectively. Whereas in this preferred example of the chip 100 shown in fig. 18A and 18B, the N-type electrode 51 extends from the first end to the second end of the chip 100 in the middle of the chip 100, the fingers 521 of the P-type electrode 52 form the first group 5211, the second group 5212 and a third group 5213 of fingers, wherein the first group 5211 and the second group 5212 of fingers extend from the second end to the first end of the chip 100 at the edge of the chip 100, respectively, and the third group 5213 of fingers is held at the second end of the chip 100.
According to another aspect of the present invention, the present invention further provides a method for manufacturing a chip 100 of a light emitting diode, wherein the method for manufacturing the chip 100 comprises the following steps:
(a) growing the N-type semiconductor layer 21, the active region 22 and the P-type semiconductor layer 23 on the substrate 10 in sequence;
(b) forming the N-type hole 101 extending from the transparent conductive layer 30 to the N-type semiconductor layer 21 through the P-type semiconductor layer 23 and the active region 22 while forming the transparent conductive layer 30 laminated on the P-type semiconductor layer 23;
(c) laminating the passivation layer 40 having a plurality of holes 41 on the transparent conductive layer 30, so that the holes 41 of the passivation layer 40 respectively correspond to different positions of the transparent conductive layer 30; and
(d) the N-type electrode 51 is electrically connected to the N-type semiconductor layer 21, and the P-type electrode 52 is electrically connected to the P-type semiconductor layer 23 through the holes 41 of the passivation layer 40.
In a preferred example of the method for manufacturing the chip 100 of the present invention, the step (b) further includes the steps of:
laminating the transparent conductive base layer 102 on the P-type semiconductor layer 23;
laminating the first photoresist layer 103 on the transparent conductive base layer 102; and
etching the first photoresist layer 103, the transparent conductive base layer 102, the P-type semiconductor layer 23, and the active region 22 to form the N-type hole 101 and the transparent conductive layer 30 at the same time.
In another preferred example of the method for manufacturing the chip 100 of the present invention, the step (b) further includes the steps of:
laminating the transparent conductive base layer 102 on the P-type semiconductor layer 23;
laminating the first photoresist layer 103 on the transparent conductive base layer 102; and
etching the first photoresist layer 103, the transparent conductive base layer 102, the P-type semiconductor layer 23, the active region 22, and the N-type semiconductor layer 21 at predetermined positions to simultaneously form the N-type hole 101 and the transparent conductive layer 30.
Further, in the step (c), while the passivation layer 40 stacked on the transparent conductive layer 30 is formed, the N-type layer exposed portion 60 extending from the passivation layer 40 to the N-type semiconductor layer 21 through the transparent conductive layer 30, the P-type semiconductor layer 23 and the active region 22 is formed at a position corresponding to the N-type hole 101.
Specifically, the step (c) further comprises the steps of:
laminating the passivation protection base layer 104 to the transparent conductive layer 30;
laminating the second photoresist layer 105 on the passivation protection base layer 104; and
the second photoresist layer 105 and the passivation protection base layer 104 are removed at positions corresponding to the N-type hole 101, so as to simultaneously form the passivation protection layer 50 and the N-type layer exposed portion 60.
Further, in the step (d), a plurality of fingers 521 extending from one side to the other side of the passivation layer 40 through the holes 41 of the passivation layer 40 are formed at the same time when the P-type electrode 52 is formed on the passivation layer 50, wherein the fingers 521 are electrically connected to the transparent conductive layer 30 at different positions of the transparent conductive layer 30.
In another aspect of the present invention, the present invention further provides a light emitting method of a chip 100 of a light emitting diode, wherein the light emitting method comprises the following steps:
(A) providing current to the transparent conductive layer 30 at a plurality of different positions, respectively, so that the current is uniformly distributed on the transparent conductive layer 30; and
(B) voltages are applied to the active region 22 through the P-type semiconductor layer 23 and the N-type semiconductor layer 21 on two sides of the active region 22, respectively, so that the active region 22 generates light to emit light, wherein the transparent conductive layer 30 is stacked on the P-type semiconductor layer 23.
In a preferred example of the light emitting method of the chip 100 of the present invention, currents are respectively provided to the transparent conductive layer 30 at both sides of the chip 100, so that the currents are uniformly distributed in the transparent conductive layer 30. In yet another preferred example of the light emitting method of the chip 100 of the present invention, currents are respectively supplied to the transparent conductive layer 30 at both sides and one end of the chip 100 so that the currents are uniformly distributed in the transparent conductive layer 30.
Fig. 20 shows a light emitting diode according to a preferred embodiment of the present invention, wherein the light emitting diode comprises at least one of the chip 100, a package body 200 and an electrode pin set 300, wherein the electrode pin set 300 comprises an N-type electrode pin 301 and a P-type electrode pin 302, the chip 100 is packaged inside the package body 100, the N-type electrode pin 301 and the P-type electrode pin 302 are electrically connected to the N-type electrode 51 and the P-type electrode 52 of the chip 100, respectively, and the N-type electrode pin 301 and the P-type electrode pin 302 extend from the inside to the outside of the package body 200, respectively. When electric power is supplied to the chip 100 through the N-type electrode pin 301 and the P-type electrode pin 302, the chip 100 can generate light, wherein the light generated by the chip 100 is radiated to the outside of the light emitting diode after passing through the package 200.
Preferably, the size of the P-type electrode pin 302 is gradually reduced from the connection end of the P-type electrode pin 302 to the free end, so that the problem that the welding part of the P-type electrode 52 and the P-type electrode pin 302 is easily burned when the light emitting diode is used due to pulse aging can be avoided, thereby ensuring the reliability of the light emitting diode.
It will be appreciated by persons skilled in the art that the above embodiments are only examples, wherein features of different embodiments may be combined with each other to obtain embodiments which are easily conceivable in accordance with the disclosure of the invention, but which are not explicitly indicated in the drawings.
It will be appreciated by persons skilled in the art that the embodiments of the invention described above and shown in the drawings are given by way of example only and are not limiting of the invention. The objects of the invention have been fully and effectively accomplished. The functional and structural principles of the present invention have been shown and described in the examples, and any variations or modifications of the embodiments of the present invention may be made without departing from the principles.
Claims (18)
1. A chip for a light emitting diode, comprising:
a substrate;
an epitaxial structure, wherein the epitaxial structure comprises an N-type semiconductor layer, an active region and a P-type semiconductor layer, wherein the substrate, the N-type semiconductor layer, the active region and the P-type semiconductor layer are sequentially stacked;
a transparent conductive layer, wherein the transparent conductive layer is laminated on the P-type semiconductor layer of the epitaxial structure;
a passivation layer, wherein the passivation layer has a plurality of holes, wherein the passivation layer is stacked on the transparent conductive layer, and the holes of the passivation layer correspond to different positions of the transparent conductive layer respectively; and
an electrode assembly, wherein the electrode assembly comprises an N-type electrode and a P-type electrode, wherein the N-type electrode is connected to the N-type semiconductor layer in a manner of being formed on and laminated on the N-type semiconductor layer, and the N-type electrode extends from the first end to the second end of the chip in the middle of the chip, wherein the P-type electrode is formed on and laminated on the passivation layer, and the P-type electrode has a first group of fingers and a second group of fingers, the first group of fingers and the second group of fingers are respectively formed on the holes of the passivation layer, and the first group of fingers and the second group of fingers extend from the second end to the first end of the chip in the edge of the chip;
the P-type electrode has a third set of fingers formed in the holes of the passivation layer, and the third set of fingers extends from the second end of the chip toward the end of the N-type electrode.
2. The chip of claim 1, wherein the chip has an N-type layer exposure extending from the passivation protection layer through the transparent conductive layer and the P-type semiconductor layer and the active region of the epitaxial structure to the N-type semiconductor layer of the epitaxial structure such that a portion of the N-type semiconductor layer is exposed at the N-type layer exposure.
3. The chip of claim 1 or 2, wherein the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.
4. The chip of claim 1 or 2, wherein the N-type semiconductor layer and the P-type semiconductor layer of the epitaxial structure are both gallium nitride layers.
5. The chip of claim 4, wherein the N-type semiconductor layer and the P-type semiconductor layer of the epitaxial structure are both gallium nitride layers.
6. A light emitting diode, comprising:
a package body;
an electrode pin group, wherein the electrode pin group comprises an N-type electrode pin and a P-type electrode pin; and
the chip according to at least one of claims 1 to 5, wherein the chip is packaged inside the package body, the N-type electrode pin and the P-type electrode pin are electrically connected to the N-type electrode and the P-type electrode of the chip, respectively, and the N-type electrode pin and the P-type electrode pin extend from the inside to the outside of the package body, respectively.
7. The light emitting diode of claim 6, wherein the P-type electrode pin is tapered in size from the connection end toward the free end of the P-type electrode pin.
8. A method of manufacturing a chip for a light emitting diode, the method comprising the steps of:
(a) sequentially growing an N-type semiconductor layer, an active region and a P-type semiconductor layer on a substrate;
(b) forming a transparent conductive layer laminated on the P-type semiconductor layer, and forming an N-type hole extending from the transparent conductive layer to the N-type semiconductor layer through the P-type semiconductor layer and the active region;
(c) laminating a passivation protection layer with a plurality of holes on the transparent conductive layer, so that the holes of the passivation protection layer respectively correspond to different positions of the transparent conductive layer; and
(d) electrically connecting an N-type electrode to the N-type semiconductor layer, and electrically connecting a P-type electrode to the P-type semiconductor layer through the holes of the passivation layer, wherein the N-type electrode is connected to the N-type semiconductor layer in such a manner as to be formed on and laminated on the N-type semiconductor layer, and the N-type electrode extends from the first end part of the chip to the second end part of the chip in the middle part of the chip, wherein the P-type electrode is formed on and laminated to the passivation layer and has a first set of fingers and a second set of fingers, the first set of finger elements and the second set of finger elements are respectively formed in the holes of the passivation protection layer, and the first and second sets of fingers extend from the second end of the chip in a direction toward the first end at the edge of the chip, respectively;
the P-type electrode has a third set of fingers formed in the holes of the passivation layer, and the third set of fingers extends from the second end of the chip toward the end of the N-type electrode.
9. The method for manufacturing a chip according to claim 8, wherein the step (b) further comprises the steps of:
laminating a transparent conductive base layer on the P-type semiconductor layer;
laminating a first photoresist layer on the transparent conductive base layer; and
and etching the preset positions of the first photoresist layer, the transparent conductive base layer, the P-type semiconductor layer and the active region to simultaneously form the N-type hole and the transparent conductive layer.
10. The method for manufacturing a chip according to claim 8, wherein the step (b) further comprises the steps of:
laminating a transparent conductive base layer on the P-type semiconductor layer;
laminating a first photoresist layer on the transparent conductive base layer; and
etching the first photoresist layer, the transparent conductive base layer, the P-type semiconductor layer, the active region and the preset position of the N-type semiconductor layer to simultaneously form the N-type hole and the transparent conductive layer.
11. The method for manufacturing a chip according to claim 9 or 10, wherein the transparent conductive base layer is laminated on the P-type semiconductor layer by evaporation in the above method.
12. The method for manufacturing a chip as claimed in claim 8, wherein in the step (c), an N-type layer exposed portion extending from the passivation layer to the N-type semiconductor layer through the transparent conductive layer, the P-type semiconductor layer and the active region is formed at a position corresponding to the N-type hole while forming a passivation layer stacked on the transparent conductive layer.
13. The method for manufacturing a chip as claimed in claim 10, wherein in the step (c), an N-type layer exposed portion extending from the passivation layer to the N-type semiconductor layer through the transparent conductive layer, the P-type semiconductor layer and the active region is formed at a position corresponding to the N-type hole while forming a passivation layer stacked on the transparent conductive layer.
14. The method for manufacturing a chip according to claim 12, wherein the step (c) further comprises the steps of:
laminating a passivation protection base layer on the transparent conductive layer;
laminating a second photoresist layer on the passivation protection base layer; and
and removing the positions of the second photoresist layer and the passivation protection base layer corresponding to the N-type hole so as to simultaneously form the passivation protection layer and the exposed part of the N-type layer.
15. The method for manufacturing a chip according to claim 13, wherein the step (c) further comprises the steps of:
laminating a passivation protection base layer on the transparent conductive layer;
laminating a second photoresist layer on the passivation protection base layer; and
and removing the positions of the second photoresist layer and the passivation protection base layer corresponding to the N-type hole so as to simultaneously form the passivation protection layer and the exposed part of the N-type layer.
16. A method of emitting light from a chip of a light emitting diode, the chip being as claimed in any one of claims 1 to 5, wherein the method comprises the steps of:
(A) providing current to the transparent conductive layer at a plurality of different positions respectively so as to enable the current to be uniformly distributed on the transparent conductive layer; and
(B) and applying voltage to the active region through the P-type semiconductor layer and the N-type semiconductor layer on two sides of the active region respectively to enable the active region to generate light and emit light, wherein the transparent conductive layer is laminated on the P-type semiconductor layer.
17. The method of claim 16, wherein in the method, current is supplied to the transparent conductive layer on both sides of the chip, respectively, so that the current is uniformly distributed in the transparent conductive layer.
18. The light emitting method of a chip according to claim 16, wherein in the above method, currents are supplied to the transparent conductive layer at both sides and one end portion of the chip, respectively, so that the currents are uniformly distributed in the transparent conductive layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810478979.1A CN108682726B (en) | 2018-05-18 | 2018-05-18 | Light emitting diode, chip thereof, manufacturing method thereof and light emitting method of chip |
| PCT/CN2018/097727 WO2019218484A1 (en) | 2018-05-18 | 2018-07-30 | Light-emitting diode, and chip and manufacturing method therefor, and light emitting method for chip |
| US16/624,930 US11456399B2 (en) | 2018-05-18 | 2018-07-30 | Light emitting diode (LED) chip and manufacturing method and light emitting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810478979.1A CN108682726B (en) | 2018-05-18 | 2018-05-18 | Light emitting diode, chip thereof, manufacturing method thereof and light emitting method of chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108682726A CN108682726A (en) | 2018-10-19 |
| CN108682726B true CN108682726B (en) | 2021-04-13 |
Family
ID=63806878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810478979.1A Active CN108682726B (en) | 2018-05-18 | 2018-05-18 | Light emitting diode, chip thereof, manufacturing method thereof and light emitting method of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108682726B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473527A (en) * | 2018-11-13 | 2019-03-15 | 厦门乾照光电股份有限公司 | The semiconductor chip and current expansion method of light emitting diode |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3691951B2 (en) * | 1998-01-14 | 2005-09-07 | 東芝電子エンジニアリング株式会社 | Gallium nitride compound semiconductor light emitting device |
| US6693306B2 (en) * | 2002-07-22 | 2004-02-17 | United Epitaxy Company, Ltd. | Structure of a light emitting diode and method of making the same |
| CN100595937C (en) * | 2002-08-01 | 2010-03-24 | 日亚化学工业株式会社 | Semiconductor light emitting device and light emitting device |
| KR101813891B1 (en) * | 2010-12-09 | 2018-01-02 | 엘지이노텍 주식회사 | Light emitting diode |
| CN203503695U (en) * | 2013-09-27 | 2014-03-26 | 长兴科迪光电有限公司 | Novel structure of direct inserting LED |
| KR20160051394A (en) * | 2014-11-03 | 2016-05-11 | 엘지이노텍 주식회사 | Light emitting device and lighting system |
| CN104377219B (en) * | 2014-11-20 | 2017-03-29 | 厦门乾照光电股份有限公司 | A kind of high-voltage LED of high-luminous-efficiency |
| CN105789400B (en) * | 2016-03-14 | 2018-08-14 | 聚灿光电科技股份有限公司 | A kind of LED chip and its manufacturing method of parallel-connection structure |
| CN107808913B (en) * | 2017-10-27 | 2019-06-04 | 江西乾照光电有限公司 | A kind of light emitting diode and production method |
| CN107808914A (en) * | 2017-10-27 | 2018-03-16 | 厦门乾照光电股份有限公司 | A kind of light emitting diode and preparation method thereof |
| CN208596701U (en) * | 2018-05-18 | 2019-03-12 | 厦门乾照光电股份有限公司 | Light emitting diode and its chip |
-
2018
- 2018-05-18 CN CN201810478979.1A patent/CN108682726B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108682726A (en) | 2018-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8378373B2 (en) | Light-emitting device | |
| US7285801B2 (en) | LED with series-connected monolithically integrated mesas | |
| US8217416B2 (en) | Light emitting device package and method for fabricating the same | |
| CN106486572B (en) | Light emitting diode chip | |
| CN107768495A (en) | Micro-led and its manufacture method | |
| TW201545377A (en) | Semiconductor light-emitting device and method of forming the same | |
| US9614126B2 (en) | Light emitting device | |
| US20120037946A1 (en) | Light emitting devices | |
| US11430934B2 (en) | Light-emitting diode device | |
| CN110212069B (en) | Light emitting diode chip and manufacturing method thereof | |
| KR100691497B1 (en) | Light-emitting device and Method of manufacturing the same | |
| CN108682726B (en) | Light emitting diode, chip thereof, manufacturing method thereof and light emitting method of chip | |
| US20220367563A1 (en) | Light-emitting device and manufacturing method thereof | |
| US11456399B2 (en) | Light emitting diode (LED) chip and manufacturing method and light emitting method thereof | |
| KR20060104162A (en) | Luminescence device and method of manufacturing the same | |
| JP5772213B2 (en) | Light emitting element | |
| CN105098010A (en) | Semiconductor light emitting element | |
| TW201413915A (en) | Light emitting diode array on wafer level and method of forming the same | |
| KR20090087374A (en) | Light emitting diode and package thereof | |
| KR20160143431A (en) | Light-emitting diode and method of fabricating the same | |
| KR101420790B1 (en) | Semiconductor light emitting device | |
| KR101171325B1 (en) | Light emitting device having a plurality of light emitting cells and method of fabricating the same | |
| KR20150038891A (en) | High efficiency light emitting diode | |
| KR20120121608A (en) | Vertical light emitting diode and method for manufacturing the same | |
| KR20120031047A (en) | Luminescence device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |