CN108646172B

CN108646172B - Chip testing device

Info

Publication number: CN108646172B
Application number: CN201810738353.XA
Authority: CN
Inventors: 邓文博
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2018-07-06
Filing date: 2018-07-06
Publication date: 2020-08-18
Anticipated expiration: 2038-07-06
Also published as: CN108646172A

Abstract

The invention discloses a chip testing device, comprising: a JTAG connection module having a JTAG test tool and a single JTAG connector, the JTAG test tool being mounted on the single JTAG connector; the switching module is used for switchably providing the output of the JTAG test tool to the input ends of the two tested chips and providing the output of the two tested chips to the input ends of the JTAG test tool; and the control module is connected to the switching module and controls a mode that the JTAG test tool tests the two tested chips by providing high/low level to the switching enabling end of the switching module. The invention can flexibly switch and test different chips or different types of chips, reduce the volume of JTAG link topology and facilitate operation.

Description

Chip testing device

Technical Field

The present invention relates to the field of integrated circuit testing, and more particularly, to a chip testing apparatus.

Background

JTAG (Joint Test Action Group) is an international standard Test protocol (compatible with IEEE 1149.1), and is mainly used for testing the inside of a chip. Most devices in the prior art (such as DSP, FPGA devices, etc.) support the JTAG protocol. The standard JTAG interface is a 5-wire interface with TMS, TCK, TRST, TDI and TDO, corresponding to mode select, clock, reset, data input and data output, respectively. 2 chips with the same type are used in one card design, the JTAG application of the chip is mainly two, and firstly, the eye pattern test is carried out on a high-speed interface of the chip; and secondly, performing online programming and firmware burning on the chip. When performing eye-testing on a chip high-speed interface, the JTAG test tool only supports the presence of a single chip within the link.

To implement the JTAG functionality of the chips described above, a prior art JTAG link topology is shown in FIG. 1, with each chip individually corresponding to a JTAG interface. The JTAG link can meet the eye pattern test function and the online programming and firmware burning function of a high-speed interface of a single chip, but two JTAG connectors are used. The JTAG connector has larger volume, occupies larger board card space, and leads the layout and wiring of the PCB of the board card to be tense; meanwhile, as the board card is installed in the host, the board card is complex to disassemble and assemble, after one chip is tested, the other chip is tested, only the board card structure can be disassembled, and the JTAG test tool is removed from the JTAG connector corresponding to the chip and then installed on the JTAG connector corresponding to the other chip, so that the complexity of chip test is greatly increased.

Aiming at the problems that the JTAG connector in the JTAG link topology used in the prior art is large in size and the test board card is difficult to disassemble and assemble, an effective solution is not provided at present.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a chip testing apparatus, which can perform flexible switching and testing for different chips or different types of chips, reduce the volume of the JTAG link topology, and facilitate operation.

In view of the above, an aspect of the embodiments of the present invention provides a chip testing apparatus, including:

a JTAG connection module having a JTAG test tool and a single JTAG connector, the JTAG test tool being mounted on the single JTAG connector;

the switching module is used for switchably providing the output of the JTAG test tool to the input ends of the two tested chips and providing the output of the two tested chips to the input ends of the JTAG test tool;

and the control module is connected to the switching module and controls a mode that the JTAG test tool tests the two tested chips by providing high/low level to the switching enabling end of the switching module.

In some embodiments, the two tested chips are provided with input terminals TCK, TMS, TRST, TDI and an output terminal TDO; the JTAG connecting module is correspondingly provided with output ends TCK, TMS, TRST, TDI and input end TDO.

In some embodiments, the switching module includes three four-channel switching chips and one single-channel switching chip, the three four-channel switching chips connect the enable terminals TCK, TMS, TRST of the two chips under test in parallel to the JTAG connection module, and connect the data terminal TDI of the JTAG connection module to the data terminals TDI of the two chips under test; and the single-channel switching chip connects the data ends TDO of the two tested chips to the data end TDO of the JTAG connection module.

In some embodiments, three four-channel switching chips and one single-channel switching chip are both QFN packages; the control module is a BMC chip.

In some embodiments, the two chips under test are a first chip under test and a second chip under test; the control module is provided with a first output end and a second output end, and the first output end and the second output end are connected to the switching enabling end of the switching module so as to control the mode of the chip testing device for testing the two chips to be tested.

In some embodiments, in the case where the first output terminal and the second output terminal both output a high level, the chip testing apparatus does not test the first chip under test nor the second chip under test, and the input terminal TDO of the JTAG connection block receives the same signal as the signal transmitted from the output terminal TDI thereof.

In some embodiments, in a case where the first output terminal outputs a low level and the second output terminal outputs a high level, the chip testing apparatus tests the first chip under test and bypasses the second chip under test, and the signal received at the input terminal TDO of the JTAG connection module is the signal transmitted at the output terminal TDO of the first chip under test.

In some embodiments, in a case where the first output terminal outputs a high level and the second output terminal outputs a low level, the chip testing apparatus tests the second chip under test and bypasses the first chip under test, and the signal received at the input terminal TDO of the JTAG connection module is the signal transmitted at the output terminal TDO of the second chip under test.

In some embodiments, in a case where both the first output terminal and the second output terminal output a low level, the chip testing apparatus tests the serial operation of the first chip under test and the second chip under test at the same time, and the signal received at the input terminal TDO of the JTAG connection module is the signal sent by the output terminal TDO of the first chip under test after the signal sent by the output terminal TDO of the first chip under test is processed by the second chip under test.

In some embodiments, the levels of the first output terminal and the second output terminal can be switched at any time to change the operation mode of the chip testing device in real time.

The invention has the following beneficial technical effects: according to the chip testing device provided by the embodiment of the invention, through the technical scheme that the single JTAG connector is simultaneously connected to the two tested chips through the switching module and the two tested chips are selectively tested according to the working mode under the control of the control module, flexible switching and testing can be carried out on different chips or different types of chips, the size of JTAG link topology is reduced, and the operation is convenient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a connection relationship of a chip testing apparatus in the prior art;

FIG. 2 is a block diagram of a chip testing apparatus according to the present invention;

FIG. 3 is a schematic circuit diagram of a chip testing apparatus according to the present invention;

FIG. 4 is a schematic circuit diagram of the chip testing apparatus provided by the present invention when neither of the two tested chips is tested;

FIG. 5 is a schematic circuit diagram of the chip testing apparatus according to the present invention when testing a first chip under test;

FIG. 6 is a schematic circuit diagram of the chip testing apparatus according to the present invention when testing a second chip under test;

FIG. 7 is a schematic circuit diagram of the chip testing apparatus according to the present invention when testing the first and second chips under test in series.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above, a first aspect of the embodiments of the present invention provides an embodiment of an apparatus capable of flexibly switching and testing different chips or different types of chips. Fig. 2 is a block diagram illustrating a chip testing apparatus according to an embodiment of the present invention.

The chip testing device includes:

a JTAG connection module 1 having a JTAG test tool and a single JTAG connector, the JTAG test tool being mounted on the single JTAG connector;

the switching module 2 is used for connecting the single JTAG connector to the two tested chips through the switching module 2, and the switching module 2 can switchably provide the output of the JTAG test tool to the input ends of the two tested chips and provide the output of the two tested chips to the input ends of the JTAG test tool;

and the control module 3 is connected to the switching module 2, and the control module 3 controls a mode that the JTAG test tool tests the two chips to be tested by providing a high/low level to a switching enabling end of the switching module 2.

In some embodiments, the two tested chips are provided with input terminals TCK, TMS, TRST, TDI and an output terminal TDO; the JTAG connecting module 1 is correspondingly provided with output terminals TCK, TMS, TRST, TDI and input terminal TDO. The JTAG connection module 1 is connected with a corresponding pin of the tested chip and tests the tested chip by sending signals to TDI and receiving feedback from TDO, such as eye pattern or programming burning.

The JTAG connection module 1 may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The functionality of JTAG connection module 1 may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

In some embodiments, the switching module 2 includes three four-channel switching chips and one single-channel switching chip, the three four-channel switching chips connect the enable terminals TCK, TMS, TRST of the two chips under test in parallel to the JTAG connection module 1, and connect the data terminal TDI of the JTAG connection module 1 to the data terminals TDI of the two chips under test; the single-channel switching chip connects the data terminals TDO of the two tested chips to the data terminal TDO of the JTAG connection module 1.

As shown in fig. 3, the embodiment of the present invention reduces the use of one JTAG connector based on the prior art, instead of using 3 pieces of 4-channel switch chips and 1 piece of single-channel switch chip as the switch module 2, and uses two GPIOs (i.e., output terminals) of the BMC chip (i.e., the control module 3) to implement the switching of the JTAG link topology. Fig. 2 shows a specific topology in which the Switch0, Switch1, Switch2 chips are 4-channel switching chips, when the SEL signal (i.e., the Switch enable) is high, a — B1; when the SEL signal is low, a equals B0. In addition, the Switch3 chip is a single-channel switching chip, similar to the 4-channel switching chip, and when the SEL signal is high, a — B1; when the SEL signal is low, a equals B0. All pins of CHIP0, CHIP1 CHIPs are directly connected to the B0 channel of the respective switching CHIP, i.e., the CHIP is on when the SEL signal is low.

It should be noted, however, that the embodiments of the present invention may also adopt a completely different switching and controlling manner from the above-mentioned schemes. For example, a person skilled in the art modifies the switching CHIP channels connected to the CHIP0 and CHIP1 into B1, and adaptively modifies the output level of GPIO (by adding an inverter or a BMC CHIP to directly output an inverted signal), so that the connection relationship between the switching module 2 and the CHIP0 and CHIP1 can be adjusted without changing 3 4-channel switching CHIPs and 1 single-channel switching CHIP, and the same effect as that of the embodiment of the present invention can be achieved; on the other hand, a person skilled in the art uses 1 chip and 8 channel switching chip to replace any 2 chips and 4 channel switching chips, or uses 1 chip and 8 channel switching chip to replace 1 chip and 4 channel switching chip and 1 single channel switching chip, and the number of chips used can be reduced on the premise of not changing the connection relationship, so as to achieve the same effect as the embodiment of the present invention. It is also within the ability and willingness of those skilled in the art to select an appropriate implementation depending on the particular application scenario. It should therefore be understood that the embodiment of the invention makes the described specific implementation of the switching module 2 only one of many available ways, and this specific implementation should not be taken as a limitation of the scope of protection.

In some embodiments, three four-channel switching chips and one single-channel switching chip are both QFN packages; the control module 3 is a BMC chip. The SEL signal of the switching chip is connected to the GPIO of the BMC chip, and the level of the GPIO controls the SEL signal to switch in real time. QFN packages may occupy less PCB layout space.

In some embodiments, the two chips under test are a first chip under test and a second chip under test; the control module 3 has a first output terminal and a second output terminal, and the first output terminal and the second output terminal are connected to the switching enable terminal of the switching module 2 to control the chip testing device to test the method of the two chips under test.

The first output end and the second output end respectively have two states (1 and 0), have four outputs of 00, 01, 10 and 11 in total, and respectively correspond to four working modes of not testing, testing the first chip to be tested, testing the second chip to be tested and simultaneously testing the first chip to be tested and the second chip to be tested. Specific modes of operation are described below:

under the condition that the first output end and the second output end both output high levels, the chip testing device does not test the first chip to be tested and the second chip to be tested, and the signal received by the input end TDO of the JTAG connection module 1 is the same as the signal sent by the output end TDI.

As shown in fig. 4, pins GPIO0 and GPIO1 of the BMC CHIP are both set to 1, so that SEL signals of the Switch CHIPs of Switch0, Switch1, Switch2 and Switch3 are all at a high level (i.e., a is B1), and at this time, signals sent by the JTAG test tool are switched to the B1 channel through the switched CHIP a channel, so that the signals are not input to JTAG interfaces of CHIPs CHIP0 and CHIP 1.

Under the condition that the first output end outputs low level and the second output end outputs high level, the chip testing device tests a first chip to be tested and bypasses a second chip to be tested, and a signal received by the input end TDO of the JTAG connection module 1 is a signal sent by the output end TDO of the first chip to be tested.

As shown in fig. 5, in this operation mode, since the GPIO0 of the BMC chip is set to 0 and the GPIO1 is set to 1, the SEL signal of the Switch0 or Switch1 switching chip is at low level (a ═ B0), and the SEL signal of the Switch2 or Switch3 switching chip is at high level (a ═ B1). The signals (TCK, TMS, TRST, and TDI) sent by the JTAG test tool at this time are switched to the B0 channel via the a channel of the Switch0 CHIP, and input to the JTAG interface of the CHIP0 CHIP. The JTAG signals (TCK _1, TMS _1, TRST _1, and TDI _1) output via the Switch1 CHIP are switched from the a channel to the B1 channel by the Switch2 CHIP and are bypassed, and thus are not input to the JTAG interface of the CHIP1 CHIP. The Switch3 CHIP switches the TDO signal sent by the CHIP0 CHIP from the B1 to the a channel, and finally feeds the TDO signal back to the JTAG test tool, so that the JTAG interface of the CHIP0 CHIP communicates with the JTAG test tool.

Under the condition that the first output end outputs high level and the second output end outputs low level, the chip testing device tests the second chip to be tested and bypasses the first chip to be tested, and the signal received by the input end TDO of the JTAG connection module 1 is the signal sent by the output end TDO of the second chip to be tested.

As shown in fig. 6, since the GPIO0 of the BMC chip is set to 1 and the GPIO1 is set to 0, the SEL signal of the Switch0 or Switch1 switching chip is at high level (a ═ B1), and the SEL signal of the Switch2 or Switch3 switching chip is at low level (a ═ B0). The signals (TCK, TMS, TRST, and TDI) issued by the JTAG test tool at this time are switched to the B1 channel via the a channel of the Switch0 CHIP and bypassed, and thus are not input to the JTAG interface of the CHIP0 CHIP. JTAG signals (TCK _1, TMS _1, TRST _1, and TDI _1) output via the Switch1 CHIP are switched from the A channel to the B0 channel by the Switch2 CHIP and input to the JTAG interface of the CHIP1 CHIP. The Switch3 CHIP switches the TDO signal sent by the CHIP1 CHIP from the B0 to the A channel, and finally feeds the TDO signal back to the JTAG test tool, so that the JTAG interface of the CHIP1 CHIP is communicated with the JTAG test tool.

Under the condition that the first output end and the second output end both output low levels, the chip testing device simultaneously tests the serial connection working condition of the first chip to be tested and the second chip to be tested, and the signal received by the input end TDO of the JTAG connecting module 1 is the signal sent by the output end TDO of the first chip to be tested after the signal sent by the output end TDO of the first chip to be tested is processed by the second chip to be tested.

As shown in fig. 7, the pins GPIO0 and GPIO1 of the BMC CHIP are all set to 0, so that the SEL signals of the Switch0, Switch1, Switch2, and Switch3 switching CHIPs are all at low level (i.e., a is B0), and at this time, the signals (TCK, TMS, TRST, and TDI) sent by the JTAG test tool are switched to the B0 channel via the a channel of the Switch0 CHIP and input to the JTAG interface of the CHIP0 CHIP. JTAG signals (TCK _1, TMS _1, TRST _1, and TDI _1) output via the Switch1 CHIP are switched from the A channel to the B0 channel by the Switch2 CHIP and input to the JTAG interface of the CHIP1 CHIP. The Switch3 CHIP switches the TDO signal sent by the CHIP1 CHIP from the B0 channel to the a channel, and finally feeds the TDO signal back to the JTAG test tool, thereby implementing the function of gating the CHIP0 and CHIP1 CHIPs JTAG interfaces simultaneously. Since the JTAG test tool only supports testing a single chip, this mode actually tests the first chip under test and the second chip under test in series as a unified chip, and both of them use the identical enable terminals in this state.

The four modes of operation described above, the various illustrative logical blocks, modules, circuits, and circuits described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

In some embodiments, the levels of the first output terminal and the second output terminal can be switched at any time to change the operation mode of the chip testing device in real time. The testing time can be greatly saved and the working efficiency can be improved without powering down or reassembling the chip.

It can be seen from the above embodiments that, in the chip testing apparatus provided in the embodiments of the present invention, by using a single JTAG connector to be simultaneously connected to two chips under test via the switching module and selectively testing the two chips under test according to the working mode under the control of the control module, flexible switching and testing can be performed for different chips or different types of chips, the volume of the JTAG link topology is reduced, and the operation is facilitated.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A chip testing apparatus, comprising:

a switching module through which the single JTAG connector is connected to two chips under test, the switching module switchably providing the outputs of the JTAG test tools to the inputs of the two chips under test and providing the outputs of the two chips under test to the inputs of the JTAG test tools;

the control module is connected to the switching module and controls a mode that the JTAG test tool tests the two chips to be tested by providing high/low level to a switching enabling end of the switching module;

the two tested chips are a first tested chip and a second tested chip; the control module is provided with a first output end and a second output end, and the first output end and the second output end are connected to the switching enabling end of the switching module to control the mode of the chip testing device for testing the two chips to be tested.

2. The apparatus of claim 1, wherein the two chips under test are provided with input terminals TCK, TMS, TRST, TDI and output terminal TDO; the JTAG connecting module is correspondingly provided with output ends TCK, TMS, TRST, TDI and input end TDO.

3. The apparatus of claim 1, wherein the switching module comprises three four-channel switching chips and one single-channel switching chip, the three four-channel switching chips connect the enable terminals TCK, TMS, TRST of the two chips under test in parallel to the JTAG connection module, and connect the data terminal TDI of the JTAG connection module to the data terminals TDI of the two chips under test; and the single-channel switching chip connects the data ends TDO of the two tested chips to the data end TDO of the JTAG connecting module.

4. The apparatus of claim 3, wherein the three four-channel switching chips and the one single-channel switching chip are each QFN packages; the control module is a BMC chip.

5. The apparatus of claim 1, wherein in a case where the first output terminal and the second output terminal both output a high level, the chip testing apparatus tests neither the first chip under test nor the second chip under test, and the input terminal TDO of the JTAG connection block receives the same signal as the signal sent from the output terminal TDI thereof.

6. The apparatus of claim 1, wherein in a case where the first output terminal outputs a low level and the second output terminal outputs a high level, the chip testing apparatus tests the first chip under test and bypasses the second chip under test, and the signal received at the input terminal TDO of the JTAG connection block is a signal transmitted at the output terminal TDO of the first chip under test.

7. The apparatus of claim 1, wherein the chip testing apparatus tests the second chip under test and bypasses the first chip under test in a case where the first output terminal outputs a high level and the second output terminal outputs a low level, and the signal received at the input terminal TDO of the JTAG connection block is a signal transmitted at the output terminal TDO of the second chip under test.

8. The apparatus of claim 1, wherein the chip testing apparatus simultaneously tests the serial operation of the first chip under test and the second chip under test when the first output terminal and the second output terminal both output low levels, and the signal received at the input terminal TDO of the JTAG connection module is the signal sent by the output terminal TDO of the first chip under test after the signal sent by the output terminal TDO of the first chip under test is processed by the second chip under test.

9. The apparatus of claim 1, wherein the levels of the first output terminal and the second output terminal can be switched at any time to change the operation mode of the chip testing apparatus in real time.