CN108616792B

CN108616792B - Integrated circuit imitating alarm sound and alarm device

Info

Publication number: CN108616792B
Application number: CN201810667581.2A
Authority: CN
Inventors: 张丹丹; 曹进伟; 陈孟邦; 蔡荣怀; 邹云根; 雷先再; 蔡文前
Original assignee: Zongren Technology Pingtan Co ltd
Current assignee: Zongren Technology Pingtan Co ltd
Priority date: 2018-06-26
Filing date: 2018-06-26
Publication date: 2024-05-24
Anticipated expiration: 2038-06-26
Also published as: CN108616792A

Abstract

The invention belongs to the technical field of electronics, and provides an integrated circuit imitating alarm sound and an alarm device; the integrated circuit includes: the device comprises a control module, an oscillator module, an audio module, an address module, a ROM module and an output module, wherein the control module is connected with a key signal and generates an enabling signal and a resetting signal according to the key signal, the oscillating signal and a circulating signal; the audio module adjusts the frequency of the oscillating signal according to the N paths of coding signals to obtain a note signal; the address module generates an N+2 path address signal according to the note signal and generates a circulating signal according to the N+2 path address signal; the ROM module codes and decodes the N paths of address signals to generate N paths of coded signals; when the enabling signal is in a first level state, the output module can output a sound driving signal; the invention can effectively solve the problems that the existing alarm device integrated circuit can not generate alarm sounds with different frequencies and has small application range.

Description

Integrated circuit imitating alarm sound and alarm device

Technical Field

The invention belongs to the technical field of electronics, and particularly relates to an integrated circuit imitating alarm sound and an alarm device.

Background

In the prior art, the alarm device is used as a separate and indispensable electronic device of the police car, an integrated circuit inside the alarm device is often extremely complex, and the alarm device needs to be arranged on the police car when in use. Therefore, in the alarm device of the existing police car, in order to realize the alarm function, an integrated circuit inside the alarm device is often extremely complex, so that the volume of the alarm device is large; and because police car is in the in-process of traveling, alarm device need carry out for a long time, send out same kind of alarm sound repeatedly, and the circuit structure of integrated circuit sets for in advance in the current alarm device to the alarm audio frequency that sends out through integrated circuit in the alarm device is single, can't be applied to the alarm device of different grade type police car with this integrated circuit, application scope is less.

Disclosure of Invention

The invention provides an integrated circuit imitating alarm sound and an alarm device, and aims to solve the problems that the integrated circuit in the existing alarm device is complex in structure, can not generate alarm sounds with different frequencies, and further is small in application range.

A first aspect of the invention provides an integrated circuit mimicking an alarm sound, comprising:

The control module is connected with the key signal and configured to generate an enabling signal and a resetting signal according to the key signal, the oscillating signal and the circulating signal;

an oscillator module connected to the control module and configured to generate the oscillation signal when the enable signal is in a first level state;

The audio module is connected with the oscillator module and is configured to adjust the frequency of the oscillating signal according to N paths of coding signals to obtain a note signal, wherein N is a positive integer greater than or equal to 7;

The address module is connected with the audio module and the control module and is configured to generate an N+2 path address signal according to the note signal and generate the circulating signal according to the N+2 path address signal;

the ROM module is connected with the address module and the audio module and is configured to encode and decode the N+2 paths of address signals to generate N paths of encoded signals; and

And the output module is connected with the address module and the control module and is configured to perform logic operation on the inverted signal of the address signal to generate a sound driving signal when the enabling signal is in a first level state.

A second aspect of the present invention provides an alarm device comprising an integrated circuit as described above, and:

and the audio equipment is connected with the integrated circuit and is configured to emit an alarm signal according to the sound driving signal generated by the integrated circuit.

Compared with the prior art, the invention has the following beneficial technical effects: in the integrated circuit imitating the alarm sound, the reset signal generated by the control module is used for resetting each signal in the integrated circuit, so that the function of circularly playing the alarm sound can be realized; the alarm device can send out alarm sounds with various frequencies by setting note codes in the N paths of coded signals, so that the circuit structure of the integrated circuit is simplified, and the applicability universality of the integrated circuit and a police car is improved; therefore, the problems that an integrated circuit inside the alarm device in the prior art is complex in structure, alarm sounds with different frequencies cannot be generated, and the application range is small are effectively solved.

Drawings

FIG. 1 is a block diagram of an integrated circuit that emulates an alarm sound provided by an embodiment of the present invention;

FIG. 2 is a block diagram of a control module according to an embodiment of the present invention;

FIG. 3 is a circuit configuration diagram of a power-on reset unit according to an embodiment of the present invention;

Fig. 4 is a circuit configuration diagram of a control signal generating unit according to an embodiment of the present invention;

fig. 5 is a circuit configuration diagram of an oscillator module according to an embodiment of the present invention;

Fig. 6 is a circuit configuration diagram of an audio module according to an embodiment of the present invention;

FIG. 7 is a block diagram of an address module according to an embodiment of the present invention;

fig. 8 is a circuit configuration diagram of an address signal generating unit according to an embodiment of the present invention;

fig. 9 is a circuit configuration diagram of a cyclic signal generating unit according to an embodiment of the present invention;

FIG. 10 is a block diagram of a ROM module according to an embodiment of the present invention;

fig. 11 is a circuit configuration diagram of a decoder unit according to an embodiment of the present invention;

fig. 12 is a circuit configuration diagram of an encoder unit provided in an embodiment of the present invention;

fig. 13 is a circuit configuration diagram of an output module according to an embodiment of the present invention;

FIG. 14 is a block diagram of an alarm device according to an embodiment of the present invention;

FIG. 15 is a block diagram of a police car according to an embodiment of the present invention;

Fig. 16 is a diagram of an internal circuit of a composite flip-flop according to an embodiment of the present invention.

Detailed Description

Fig. 1 shows a block structure of an integrated circuit 10 imitating alarm sounds provided in an embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown in detail as follows:

As shown in fig. 1, the integrated circuit 10 imitating alarm sounds includes a control module 101, an oscillator module 102, an audio module 103, an address module 104, a ROM module 105, and an output module 106; the control module 101 is connected to the key signal TG, and generates an enable signal EN and a RESET signal RESET according to the key signal TG, the oscillation signal OSC and the cyclic signal SET, wherein the RESET signal RESET is configured to SET the cyclic number of the alarm sound played by the integrated circuit 10, and when the alarm sound of the integrated circuit 10 is completely played, the RESET signal RESET plays a role in resetting; the oscillator module 102 is bi-directionally connected to the control module 101, the oscillator module 102 can output an oscillation signal OSC to the control module 101, and the control module 101 can also output an enable signal EN to the oscillator module 102, wherein when the enable signal EN output by the control module 101 is in a first level state, the oscillator module 102 generates the oscillation signal OSC; specifically, the on or off state of the oscillator module 102 can be controlled by the level state of the enable signal EN, and if the enable signal EN is in the first level state, the oscillator module 102 works normally and outputs the oscillation signal OSC; on the contrary, if the enable signal EN is in the second level state, the oscillator module 102 stops working, and the oscillator module 102 does not output the oscillation signal OSC; preferably, the first level state is a high level state, and the second level state is a low level state; optionally, the oscillation signal OSC is a square wave.

The audio module 103 is connected with the oscillator module 102, and the audio module 103 adjusts the frequency of the oscillation signal OSC according to N paths of encoded signals D and obtains a note signal TONE, wherein N is a positive integer greater than or equal to 7; in order to make the frequency of the alarm sound generated by the integrated circuit 10 adjustable, the frequency of the alarm sound finally generated by the integrated circuit 10 can be changed by adjusting the codes of each of the N paths of code signals D, namely, the integrated circuit 10 has the frequency division function; setting codes of each path of coded signals in the N paths of coded signals D, so that the N paths of coded signals D have various code combinations; each code combination in the N code signals D represents a corresponding frequency note; for example, the audio module 103 receives 6 encoded signals, wherein the code combination of the 6 encoded signals D0 to D6 is 0101010, and the audio module 103 can generate the note signal TONE with a specific frequency based on the 6 encoded signals D0 to D6; the integrated circuit 10 thus generates alarm sounds having a plurality of frequencies by changing the code combination of the N-way coded signal D.

The address module 104 is connected with the control module 101 and the audio module 103, wherein the audio module 103 transmits a note signal TONE to the address module 104, the note signal TONE has a function of realizing carry, and the integrated circuit 10 can play alarm sounds circularly and sequentially; the address module 104 generates an n+2-way address signal Q from the note signal TONE, and generates a cyclic signal SET from the n+2-way address signal Q, the cyclic signal SET being configured to enable cyclic transmission of signals in the integrated circuit 10; meanwhile, the address module 104 transmits the cyclic signal SET to the control module 101, and then bidirectional signal transmission and reception are performed between the control module 101 and the address module 104, so as to realize a complex signal processing function.

The ROM module 105 is connected with the address module 104 and the audio module 103, and the address module 104 generates N paths of coded signals D after coding and decoding the N+2 paths of address signals Q; because the n+2 path address signal Q generated by the address module 104 cannot be directly identified by the audio module 103, the n+2 path address signal Q is converted into an N path encoded signal D which can be directly compatible with the audio module 103 through encoding and decoding operations; further, when the ROM module 105 transmits the N-way coded signal D to the audio module 103, the audio module 103 adjusts the frequency of the oscillation signal OSC according to the specific code combination of the N-way coded signal D, so that the N-way coded signal D generated by the ROM module 105 controls the frequency at which the integrated circuit 10 outputs the alarm sound.

The output module 106 is connected to the address module 104 and the control module 101, the control module 101 transmits the enable signal EN to the output module 106, and if the enable signal EN is in the first level state, the output module 106 inverts the address signal QGenerating a sound driving signal OUT after logic operation; the output module 106 is further connected to the audio device 20, the output module 106 transmits a sound driving signal OUT to the audio device 20, and the audio device 20 sends OUT a cyclic alarm sound under the driving of the sound driving signal OUT; it should be noted that, since the address signal Q generated by the address module 104 includes n+2 paths, the output module 106 may select the inverse signal/>, of one path of the address signal QThe logic operation can also be carried out to select the inverse signal/>, of the multipath signals in the address signal QPerforming logic operation, wherein both selection modes can ensure that the output module 106 can output the sound driving signal OUT; wherein the control module 101 controls the on or off state of the output module 106 through the level state of the enable signal EN; that is, the output module 106 can generate the sound driving signal OUT only when the enable signal EN is in the first level state; on the contrary, if the enable signal EN is in the second level state, the output module 106 will not generate the sound driving signal, and the integrated circuit 10 is in the stop state, and the audio device 20 will not sound an alarm; preferably, the enabling signal EN is in a first level state and means that the enabling signal EN is in a high level state, and the enabling signal EN is in a second level state and means that the enabling signal EN is in a low level state.

Specifically, fig. 2 shows a block structure of the control module 101 provided by the embodiment of the present invention, as shown in fig. 2, the control module 101 includes a power-on reset unit 1011 and a control signal generating unit 1012, where the power-on reset unit 1011 accesses a dc power supply VDD and generates a power-on reset signal POR, and the power-on reset signal POR is configured to perform power-on reset protection on the control module 101 during a power-on start process, so as to ensure normal operation of the integrated circuit 10; the control signal generating unit 1012 is connected to the power-on RESET unit 1011, the power-on RESET unit 1011 transmits the power-on RESET signal POR to the control signal generating unit 1012, the control signal generating unit 1012 generates an enable signal EN and a RESET signal RESET according to the power-on RESET signal POR, the key signal TG, the oscillation signal OSC and the cyclic signal SET, wherein the enable signal EN is configured to control the operation and the stop state of the integrated circuit 10, and the RESET signal RESET is configured to control the time and the number of times the integrated circuit 10 cyclically plays the alarm sound.

Specifically, fig. 3 shows a circuit structure of a power-on reset unit 1011 according to an embodiment of the present invention, and as shown in fig. 3, the power-on reset unit 1011 includes: a second PMOS transistor PMOS2, a second capacitor C2, a twenty-sixth inverter INV26, a twenty-seventh inverter INV27, and a twenty-eighth inverter INV28; the source of the second PMOS transistor PMOS2 is connected to the dc power supply VDD, through which dc power can be output to the control module 101, the gate of the second PMOS transistor PMOS2 is grounded GND, the drain of the second PMOS transistor PMOS2 and the input end of the twenty-sixth inverter INV26 are commonly connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is grounded GND, the output end of the twenty-sixth inverter INV26 is connected to the input end of the twenty-seventh inverter INV27, the output end of the twenty-seventh inverter INV27 is connected to the input end of the twenty-eighth inverter INV28, the output end of the twenty-eighth inverter INV28 is connected to the control signal generating unit 1012, and the output end of the twenty-eighth inverter INV28 is the output end of the power-on reset unit 1011 configured to transmit the power-on reset signal POR to the control signal generating unit 1012.

Specifically, fig. 4 shows a circuit structure of the control signal generating unit 1012 provided in the embodiment of the present invention, and as shown in fig. 4, the control signal generating unit 1012 includes: the first PMOS transistor PMOS1, the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, the first NOR gate NOR1, the second NOR gate NOR1, the third NOR gate NOR3, the D flip-flop ZDR, the first T flip-flop ZTR1 and the second T flip-flop ZTR2.

The input end of the first inverter INV1 is configured to be connected with an oscillation signal OSC, the output end of the first inverter INV1 and the CKB input end of the first T flip-flop ZTR1 are connected with the input end of the second inverter INV2, the output end of the second inverter INV2 is connected with the CK input end of the first T flip-flop ZTR1, the source electrode of the first PMOS transistor PMOS1 is connected with a direct current power supply VDD, the gate electrode of the first PMOS transistor PMOS1 is grounded GND, the drain electrode of the first PMOS transistor PMOS1 and the input end of the third inverter INV3 are configured to be connected with a key signal TG, the input end of the fourth inverter INV4 is connected with the inverted signal TGB of the first T flip-flop ZTR1, the output end of the fourth inverter INV4 and the CK input end of the D flip-flop ZDR are connected with the input end of the sixth inverter INV6, the output end of the sixth inverter INV6 is connected with the CKB input end of the D flip-flop ZDR, the first input end of the first NOR gate 1 is connected with the first reset signal input end of the first NOR gate 1011; the output end of the fifth inverter INV5 is connected with the second input end of the first NOR gate NOR1, the output end of the first NOR gate NOR1 is connected with the input end of the seventh inverter INV7, the R input end of the D trigger ZDR, the R input end of the second T trigger ZTR2 and the first input end of the second NOR gate NOR2 are commonly connected with the output end of the seventh inverter INV7, and the second input end of the second NOR gate NOR2 is connected with the control module 101 and is configured to be connected with the circulating signal SET; the output end of the second NOR gate NOR2 is connected with the input end of the eighth inverter INV8, the output end of the eighth inverter INV8 is configured to output a RESET signal RESET, the R input end of the first T flip-flop ZTR1 is configured to input the RESET signal RESET, the Q output end of the D flip-flop ZDR is connected with the CK input end of the second T flip-flop ZTR2, the QB output end of the D flip-flop ZDR is connected with the CKB input end of the second T flip-flop ZTR2, the first input end of the third NOR gate NOR3 and the output end of the third inverter INV3 are connected with the D input end of the D flip-flop ZDR in common, the Q output end of the second T flip-flop ZTR2 is connected with the second input end of the third NOR gate NOR3, and the output end of the third NOR gate BOR3 is connected with the input end of the ninth inverter INV 9.

Specifically, in the circuit structure of the control signal generating unit 1012, the drain of the first PMOS transistor PMOS1 and the input end of the third inverter INV3 are connected to a pull-up resistor, wherein the key signal TG is generated by an external key, when the external key is pressed, the key signal TG is triggered to ground, at this time, the key signal TG becomes low level, the inverted signal TGB of the key signal TG becomes high level, the input end of the fifth inverter INV5 is connected to the high level signal, the control signal generating unit 1012 is in normal operation, and the control signal generating unit 1012 starts outputting the enable signal EN and the RESET signal RESET.

Specifically, fig. 5 shows a circuit structure of an oscillator module 102 provided in an embodiment of the present invention, and as shown in fig. 5, the oscillator module 102 includes: the first capacitor C1, the first resistor R1, the tenth inverter INV10, the eleventh inverter INV11, the twelfth inverter INV12, the thirteenth inverter INV13, the fourteenth inverter INV14, the fifteenth inverter INV15, the first NAND gate NAND1, the second NAND gate NAND2, and the third NAND gate NAND3.

The first end of the first resistor R1, the first end of the first capacitor C1 and the input end of the tenth inverter INV10 are commonly connected to the input end of the eleventh inverter INV11, the output end of the eleventh inverter INV11 is connected to the input end of the twelfth inverter INV12, the output end of the tenth inverter INV10 is connected to the first input end of the first NAND gate NAND1, the second input end of the first NAND gate NAND1 is connected to the output end of the second NAND gate NAND2, the first input end of the second NAND gate NAND2 and the output end of the first NAND gate NAND1 are commonly connected to the first input end of the third NAND gate NAND3, the output end of the twelfth inverter INV12 is connected to the second input end of the second NAND gate NAND2, the second input end of the third NAND gate NAND3 is configured to be connected to the enable signal EN, the output end of the thirteenth inverter INV13 is connected to the second input end of the control module 101, the output end of the thirteenth inverter INV13 and the second end of the second capacitor C1 are commonly connected to the first input end of the fourteenth inverter INV14, the output end of the fifteenth inverter INV is configured to the output end of the fifteenth inverter OSC 1; the enable signal EN generated by the control module 101 can control the operation or stop state of the oscillator module 102.

Specifically, fig. 6 shows a circuit structure of an audio module 103 provided in an embodiment of the present invention, and as shown in fig. 6, the audio module 103 includes: sixteenth inverter INV16, seventeenth inverter INV17, eighteenth inverter INV18, nineteenth inverter INV19, composite flip-flop array, third T flip-flop ZTR3, exclusive or gate XOR, and fourth NOR gate NOR4.

The composite trigger array is formed by cascading N composite triggers ZSR1, ZSR2 … ZSRN-1 and ZSRN, and the forward output end Q of the previous-stage composite trigger ZSRj-1 is connected with the trigger signal input end D of the next-stage composite trigger ZSRj, wherein j is any positive integer between 2 and N; an input end of the sixteenth inverter INV16 is connected to the oscillation signal OSC, and an input end of the sixteenth inverter INV16 is connected to the oscillator module 102; the input end CKB of the reverse clock signal of each stage of compound trigger in the compound trigger array is commonly connected with the output end of a sixteenth inverter INV16, the input end of a seventeenth inverter INV17 is connected with the output end of the sixteenth inverter INV16, the input end CK of the forward clock signal of each stage of compound trigger in the compound trigger array is commonly connected with the output end of the seventeenth inverter INV17, the reset signal input end J of each stage of compound trigger in the compound trigger array is connected with one path of coding signal, the trigger signal input end D of the first stage of compound trigger is connected with the output end of an exclusive-OR gate XOR, the first input end of the exclusive-OR gate XOR is connected with the forward output end Q of the N stage of compound trigger, and the second input end of the exclusive-OR gate XOR is connected with the forward output end Q of the N-1 stage of compound trigger.

The fourth NOR gate NOR4 has N-1 input ends, the forward output end Q of the ith stage of composite flip-flop ZSRi is connected to the i-1 input end of the fourth NOR gate NOR4, i is any positive integer between 2 and N, the output end of the fourth NOR gate NOR4 is connected to the input end of the eighteenth inverter INV18, the reverse control end PSB of each stage of composite flip-flop in the composite flip-flop array, the output end of the eighteenth inverter INV18 and the input end of the nineteenth inverter INV19 are commonly connected to the CKB input end of the third T flip-flop ZTR3, the forward control end PS of each stage of composite flip-flop in the composite flip-flop array and the output end of the nineteenth inverter INV19 are commonly connected to the CK input end of the third T flip-flop ZTR3, and the QB output end of the third T flip-flop ZTR3 is configured to output the note signal TONE.

It should be noted that, the composite flip-flop in the composite flip-flop array includes N composite flip-flops, where the composite flip-flop has similar signal processing functions as the T flip-flop and the D flip-flop in the technical field, but the composite flip-flop in the embodiment of the present invention is different from the T flip-flop and the D flip-flop in the technical field in that the composite flip-flop further has a forward control terminal PS and a reverse control terminal PSB, and the signals accessed by the forward control terminal PS and the reverse control terminal PSB can control the signal states output by the forward output terminal Q and the reverse output terminal QB of the composite flip-flop, i.e. the composite flip-flop in the embodiment of the present invention has more signal control terminals, so that in order to more clearly illustrate the functional principle of the composite flip-flop in the embodiment of the present invention, fig. 16 shows the internal circuit structure of the composite flip-flop provided in the embodiment of the present invention, and the composite flip-flop is formed by cascading a reverser, a CMOS tube and an adder as shown in fig. 16.

Specifically, the R input end of the third T flip-flop ZTR3 is connected to the control module 101 and configured to be connected to a RESET signal RESET, and perform a RESET operation on the audio module 103 through the RESET signal RESET.

Further, according to the circuit structure of the audio module 103 shown in fig. 6, the oscillating signal OSC is connected to the input end of the sixteenth inverter INV16, the composite trigger array adjusts the frequency of the oscillating signal OSC according to the code combination of the input N-way code signals to obtain the note signal TONE with a specific frequency, and the integrated circuit 10 can output alarm sounds with various frequencies.

Specifically, fig. 7 shows a block structure of an address module 104 provided in an embodiment of the present invention, and as shown in fig. 7, the address module 104 includes an address signal generating unit 1041 and a cyclic signal generating unit 1042; the address signal generating unit 1041 is connected with the audio module 103 and the control module 101, the audio module 103 transmits the note signal TONE to the address module 104, the control module 101 transmits the RESET signal RESET to the address module 104, and the address signal generating unit 1041 generates an n+2 address signal Q according to the note signal TONE and the RESET signal RESET; the cyclic signal generating unit 1042 is connected to the address signal generating unit 1041 and the control module 101, the address signal generating unit 1041 transmits the n+2 address signal Q to the cyclic signal generating unit 1042, and the control module 101 transmits the power-on reset signal POR and the clock signal S1 to the cyclic signal generating unit 1042; it should be noted that, the clock signal S1 is generated by the control module 101, and specifically referring to fig. 4, the clock signal S1 is output by the QB output terminal of the first T flip-flop ZTR 1; wherein the note signal TONE is configured to implement a carry function in the address module 104, so as to ensure that the integrated circuit 10 can switch and play the alarm sound in sequence; the RESET signal RESET is configured to RESET the address module 104 to ensure that the integrated circuit 10 can cycle through the alarm sounds.

Specifically, fig. 8 shows a circuit structure of an address signal generating unit 1041 provided in an embodiment of the present invention, and as shown in fig. 8, the address signal generating unit 1041 includes: the twentieth inverter INV20, the twenty-first inverter INV21, the twenty-second inverter INV22, and the T flip-flop array.

The T flip-flop array is formed by cascading n+2T flip-flops ZTR4, ZTR5 … ZTRN +4, ZTRN +5, the Q output end of the Q flip-flop of the previous stage T flip-flop ZTRk is connected to the CKB input end of the next stage T flip-flop ZTRk +1, where k is any positive integer of 4,5 … n+3, n+4, the QB output end of the previous stage T flip-flop ZTRk is connected to the CK input end of the next stage T flip-flop ZTRk +1, the Q output end of each stage T flip-flop in the T flip-flop array outputs one path of address signals Q1, Q2 … qn+1, qn+2, and the R input end of each stage T flip-flop in the T flip-flop array is connected to the control module 101 and configured to access a RESET signal RESET, through which the address signal generating unit 1041 can perform a RESET operation.

Wherein the input end of the twentieth inverter INV20 is connected with the audio module 103 and is configured to be connected with the note signal TONE; the output end of the twenty-first inverter INV20 and the CKB input end of the first stage T flip-flop ZTR4 in the T flip-flop array are commonly connected to the input end of the twenty-first inverter INV21, the output end of the twenty-first inverter INV21 is connected to the CK input end of the first stage T flip-flop ZTR4 in the T flip-flop array, the input end of the twenty-second inverter INV22 is connected to the Q output end of the first stage T flip-flop ZTR4 in the T flip-flop array, and specifically, the first path address signal Q1 output by the Q output end of the first stage T flip-flop ZTR4 outputs the inverted signal Q1B of the first path address signal Q1 through the twenty-second inverter INV 22.

Specifically, fig. 9 shows a circuit structure of a cyclic signal generating unit 1042 provided in an embodiment of the present invention, and as shown in fig. 9, the cyclic signal generating unit 1042 includes: the twenty-third inverter INV23, the twenty-fourth inverter INV24, the twenty-fifth inverter INV25, the fourth NAND gate NAND4, the fifth NAND gate NAND5, the fifth NOR gate NOR5, the sixth NOR gate NOR6, and the seventh NOR gate NOR7.

The fourth NAND gate NAND4 has four input terminals, the fifth NAND gate NAND5 has five input terminals, the seventh NOR gate NOR7 has three input terminals, and the input terminal of the thirteenth inverter INV23 is connected to the address signal generating unit 1041 and configured to access the first path address signal Q1; the output end of the twenty-third inverter INV23 is connected with the first input end of the fourth NAND gate NAND4, and the second input end of the fourth NAND gate NAND4 is connected with the address signal generating unit 1041 and is configured to be connected with the second path address signal Q2; a third input end of the fourth NAND gate NAND4 is connected with the address signal generating unit 1041 and is configured to be connected with a third address signal Q3; an input end of the twenty-fourth inverter INV24 is connected with the address signal generating unit 1041 and is configured to be connected with the fourth path address signal Q4; the output end of the twenty-fourth inverter INV24 is connected to the fourth input end of the fourth NAND gate NAND4, and the first input end of the fifth NAND gate NAND5 is connected to the address signal generating unit 1041 and is configured to be connected to the fifth address signal Q5; a second input end of the fifth NAND gate NAND5 is connected with the address signal generating unit 1041 and is configured to be connected with a sixth path address signal Q6; an input end of the twenty-fifth inverter INV25 is connected with the address signal generating unit 1041 and is configured to be connected with the seventh address signal Q7; the output end of the twenty-fifth inverter INV25 is connected to the third input end of the fifth NAND gate NAND5, the fourth input end of the fifth NAND gate NAND5 is connected to the address signal generating unit 1041 and is configured to be connected to the eighth path address signal Q8, and the fifth input end of the fifth NAND gate NAND5 is connected to the address signal generating unit 1041 and is configured to be connected to the ninth path address signal Q9.

The output end of the fourth NAND gate NAND4 is connected to the first input end of the fifth NOR gate NOR5, the output end of the fifth NAND gate NAND5 is connected to the second input end of the fifth NOR gate NOR5, the output end of the fifth NOR gate NOR5 is connected to the first input end of the sixth NOR gate NOR6, the output end of the sixth NOR gate NOR6 is connected to the first input end of the seventh NOR gate NOR7, the second input end of the sixth NOR gate NOR6 is connected to the output end of the seventh NOR gate NOR7, the second input end of the seventh NOR gate NOR7 is configured to be connected to the clock signal S1, the third input end of the seventh NOR gate NOR7 is connected to the power-on reset unit 1011, and is configured to be connected to the power-on reset signal POR, and the output end of the seventh NOR gate NOR7 is configured to output the cycle signal SET.

Specifically, fig. 10 shows a block structure of a ROM module 105 according to an embodiment of the present invention, as shown in fig. 10, the ROM module includes a decoder unit rowdec_p and an encoder unit rom_512, where the decoder unit rowdec_p is connected to an address module 104, and the decoder unit rowdec_p generates a decoding signal according to an address signal Q; optionally, the address module 104 may transmit a part of the n+2 address signals Q to the decoder unit ROWDEC_P; the decoder unit ROWDEC_P transmits a decoded signal to the encoder unit ROM_512, wherein the decoded signal includes 32 segments of signals.

The encoder unit ROM_512 is connected with the decoder unit ROWDEC_P and the address module 104, the decoder unit ROWDEC_P transmits decoding signals to the encoder unit ROM_512, the address module 104 transmits partial address signals in the N+2 paths of address signals Q to the encoder unit ROM_512, and the encoder unit ROM_512 generates N paths of encoding signals D1, D2 … DN-1 and DN according to the decoding signals and the address signals.

As an alternative implementation manner, fig. 11 shows a circuit structure of a decoder unit rowdec_p provided by an embodiment of the present invention, fig. 12 shows a circuit structure of an encoder unit rom_512 provided by an embodiment of the present invention, and as can be seen from fig. 11 and 12, the decoder unit rowdec_p is formed by interconnecting a plurality of CMOS pipes and a plurality of inverters, and similarly, the encoder unit rom_512 is formed by interconnecting a plurality of CMOS pipes and a plurality of inverters; the input multi-channel address signal Q controls the on or off of the CMOS tube, so that the ROM module 105 outputs N channels of coded signals with different code combinations.

It should be noted that, in the above-mentioned module structure of the ROM module 105, the anti-leakage signal input terminal of the decoder unit rowdec_p and the anti-leakage signal input terminal of the encoder unit rom_512 are commonly connected to the control module 101, and are configured to be connected to the enable signal EN to prevent the ROM module 105 from leaking during the period of stopping operation.

As an alternative implementation manner, fig. 13 shows a circuit structure of an output module 106 provided by an embodiment of the present invention, and as shown in fig. 13, the output module 106 includes: twenty-ninth inverter INV29, thirty-fifth inverter INV30, thirty-first inverter INV31, thirty-second inverter INV32, thirty-third inverter INV33, thirty-fourth inverter INV34, thirty-fifth inverter INV35, sixth NAND gate NAND6, and seventh NAND gate NAND7.

Specifically, the first input terminal of the sixth NAND gate NAN6 and the second input terminal of the seventh NAND gate NAND7 are commonly connected to the control module 101 and configured to access the enable signal EN; the second input end of the sixth nand gate NAN6 and the input end of the twenty-ninth inverter INV29 are commonly connected to the address module 104 and configured to be connected to the inverted signal Q of the address signal Q; the output end of the twenty-ninth inverter INV29 is connected with the first input end of the seventh NAND gate NAND7, the output end of the sixth NAND gate NAND6 is connected with the input end of the thirty-first inverter INV30, the output end of the thirty-first inverter INV30 is connected with the input end of the thirty-second inverter INV32, the output end of the seventh NAND gate NAND7 is connected with the input end of the thirty-third inverter INV33, the output end of the thirty-fourth inverter INV33 is connected with the input end of the thirty-fifth inverter INV34, the output end of the thirty-second inverter INV32 and the output end of the thirty-fifth inverter INV35 are configured to output sound driving signals BD and BDB; the above-mentioned sound drive signal OUT includes sound drive signals BD and BDB here. The circuit connection structure of the output module 106 shown in fig. 13 is combined, wherein the phase of the sound driving signal BD output by the output end of the thirty-second inverter INV32 is opposite to the phase of the sound driving signal BDB output by the output end of the thirty-fifth inverter INV 35.

Further, in the circuit structure of the output module 106 shown in fig. 13, the output module 106 is connected to the inverted signal of the address signal Q generated by the address module 104In combination with the above, since the address module 104 generates the n+2-way address signal Q according to the note signal TONE, i.e., the inverse signal/>, of the address signal QAlso having n+2 ways, as a preferred embodiment, the address module 104 may invert the n+2 way signal/>The output module 106 outputs one of the inverted signals (e.g., the first inverted signal Q1B) to the output module 106, and the output module 106 performs logic operation on one of the inverted signals in the address signal Q to generate the sound driving signal OUT, so as to drive the integrated circuit 10 to generate alarm sounds with various frequencies.

As a preferred embodiment, the N is 7.

In the integrated circuit 10 simulating the alarm sound, the control module 101 generates the enable signal EN and the RESET signal RESET, so that the operation and the stop state of the integrated circuit 10 can be controlled by adjusting the level state of the enable signal EN, and the circulation signal SET can realize the function of circulating the alarm sound in the integrated circuit 10, thereby greatly simplifying the structure of the circuit; because the N-way code signal D has a plurality of code combination forms, the note signals TONE with different frequencies can be obtained by changing the code combination of the N-way code signal D, and the integrated circuit 10 can circularly play the alarm sounds with different frequencies; the problem that an integrated circuit in the existing alarm device cannot generate alarm sounds with different frequencies and the circuit structure is complex is effectively solved.

Fig. 14 shows a block structure of an alarm device 140 according to an embodiment of the present invention, the alarm device 140 including an integrated circuit 10 and an audio apparatus 1401 as described above; wherein the integrated circuit 10 is connected to an audio device 1401, the audio device 1401 emits an alarm signal in response to a sound drive signal OUT generated by the integrated circuit 10; since the integrated circuit 10 can generate the note signals TONE with different frequencies by adjusting the code combination form of the internal multi-channel code signal D, the parameters of the sound driving signal OUT generated by the integrated circuit 10 will also be changed accordingly, such as the frequency, signal amplitude, etc. of the sound driving signal OUT; accordingly, the audio device 1401 can cyclically play alert signals having different frequencies under the drive of the sound drive signal OUT.

Preferably, in the alarm device 140, the audio device 1401 is a buzzer or a loudspeaker or the like.

Fig. 15 shows a module structure of a police car 150 according to an embodiment of the present invention, where the police car 150 includes an audio device 1401 as described above, and when the audio device 1401 is applied to the police car 150, the police car 150 can cyclically play alarm sounds with different frequencies according to different uses of the police car 150, thereby enhancing the practical performance of the police car 150 and having a good application prospect.

Claims

1. An integrated circuit that mimics an alarm sound, comprising:

The output module is connected with the address module and the control module and is configured to perform logic operation on the inverted signal of the address signal to generate a sound driving signal when the enabling signal is in a first level state;

and if the enabling signal is in the second level state, the oscillator module stops working, and the oscillator module does not output an oscillating signal.

2. The integrated circuit of claim 1, wherein the control module comprises:

a power-on reset unit configured to access a direct current power supply and generate a power-on reset signal; and

And the control signal generating unit is connected with the power-on reset unit and is configured to generate the enabling signal and the reset signal according to the power-on reset signal, the key signal, the oscillation signal and the circulating signal.

3. The integrated circuit of claim 2, wherein the control signal generation unit comprises: the first PMOS tube, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the ninth inverter, the first NOR gate, the second NOR gate, the third NOR gate, the D trigger, the first T trigger and the second T trigger;

The input end of the first inverter is configured to be connected to the oscillation signal, the output end of the first inverter and the CKB input end of the first T flip-flop are commonly connected to the input end of the second inverter, the output end of the second inverter is connected to the CK input end of the sixth inverter, the source electrode of the first PMOS tube is connected to a dc power supply, the gate electrode of the first PMOS tube is grounded, the drain electrode of the first PMOS tube and the input end of the third inverter are configured to be connected to the key signal, the input end of the fourth inverter is connected to the inverted signal of the first T flip-flop, the output end of the fifth inverter and the CK input end of the D flip-flop are commonly connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the CKB input end of the D flip-flop, the first input end of the first nor gate is connected to the gate, the drain electrode of the first inverter and the input end of the third PMOS tube is configured to be connected to the key signal, the input end of the second inverter is configured to the seventh inverter, the input end of the second inverter is connected to the second inverter, the output end of the second inverter is connected to the output end of the seventh inverter, the output end of the second inverter is connected to the second inverter, the output end of the second inverter is connected to the output end of the third inverter, the output end of the second inverter is connected to the output end of the third inverter, and the output end of the third inverter is connected to the third input end of the third inverter, and the output end of the second inverter is connected to the second inverter, the QB output end of the D trigger is connected with the CKB input end of the second T trigger, the first input end of the third NOR gate and the output end of the third inverter are connected with the D input end of the D trigger, the Q output end of the second T trigger is connected with the second input end of the third NOR gate, the output end of the third NOR gate is connected with the input end of the ninth inverter, and the output end of the ninth inverter is configured to output the enabling signal.

4. The integrated circuit of claim 1, wherein the oscillator module comprises: a first capacitor, a first resistor, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a fifteenth inverter, a first NAND gate, a second NAND gate, and a third NAND gate;

The first end of the first resistor, the first end of the first capacitor and the input end of the tenth inverter are commonly connected to the input end of the eleventh inverter, the output end of the eleventh inverter is connected to the input end of the twelfth inverter, the output end of the tenth inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the second NAND gate, the first input end of the second NAND gate and the output end of the first NAND gate are commonly connected to the first input end of the third NAND gate, the output end of the twelfth inverter is connected to the second input end of the second NAND gate, the second input end of the third NAND gate is configured to be connected to the enable signal, the output end of the third NAND gate is connected to the input end of the thirteenth inverter, the output end of the thirteenth inverter and the second end of the first capacitor are commonly connected to the output end of the fourteenth inverter, and the output end of the fourteenth inverter is configured to be connected to the output end of the fifteenth oscillator.

5. The integrated circuit of claim 1, wherein the audio module comprises: sixteenth, seventeenth, eighteenth, nineteenth, composite flip-flop arrays, third T flip-flops, exclusive-or gates, and fourth nor gates;

The positive output end of each stage of compound trigger in the compound trigger array is connected with one path of coding signal, the trigger signal input end of each stage of compound trigger in the compound trigger array is connected with the output end of the exclusive-OR gate, the first input end of the exclusive-OR gate is connected with the positive output end of the N stage of compound trigger, and the second input end of the exclusive-OR gate is connected with the positive output end of the N-1 stage of compound trigger;

The positive output end of the i-th stage of the composite trigger is connected with the i-1-th input end of the fourth nor gate, i is any positive integer between 2 and N, the output end of the fourth nor gate is connected with the input end of the eighteenth inverter, the reverse control end of each stage of the composite trigger in the composite trigger array, the output end of the eighteenth inverter and the input end of the nineteenth inverter are commonly connected with the CKB input end of the third T trigger, the positive control end of each stage of the composite trigger in the composite trigger array and the output end of the nineteenth inverter are commonly connected with the CK input end of the third T trigger, and the QB output end of the third T trigger is configured to output the note signal.

6. The integrated circuit of claim 2, wherein the address module comprises:

An address signal generating unit connected to the audio module and the control module and configured to generate the n+2 address signals according to the note signal and the reset signal; and

And the circulating signal generating unit is connected with the control module and the address signal generating unit and is configured to generate the circulating signal according to the N+2-path address signal, the power-on reset signal and the clock signal.

7. The integrated circuit of claim 6, wherein the address signal generation unit comprises: a twenty-first inverter, a twenty-second inverter, and a T flip-flop array;

The T trigger array is formed by cascading N+2T triggers, the Q output end of the Q trigger of the previous stage T trigger is connected with the CKB input end of the next stage T trigger, the QB output end of the previous stage T trigger is connected with the CK input end of the next stage T trigger, the Q output end of each stage T trigger in the T trigger array outputs one path of address signal, and the R input end of each stage T trigger in the T trigger array is configured to be connected with the reset signal;

The input end of the twentieth inverter is configured to be connected with the note signal, the output end of the twentieth inverter and the CKB input end of the first-stage T flip-flop in the T flip-flop array are commonly connected with the input end of the twenty-first inverter, the output end of the twenty-first inverter is connected with the CK input end of the first-stage T flip-flop in the T flip-flop array, and the input end of the twenty-second inverter is connected with the Q output end of the first-stage T flip-flop in the T flip-flop array.

8. The integrated circuit according to claim 6 or 7, wherein the cyclic signal generating unit includes: a twenty-third inverter, a twenty-fourth inverter, a twenty-fifth inverter, a fourth nand gate, a fifth nor gate, a sixth nor gate, and a seventh nor gate;

The fourth nand gate has four input ends, the fifth nand gate has five input ends, the seventh nor gate has three input ends, the input end of the twenty-third inverter is configured to be connected to a first path of address signal, the output end of the twenty-fifth inverter is connected to a first input end of the fourth nand gate, the second input end of the fourth nand gate is configured to be connected to a second path of address signal, the third input end of the fourth nand gate is configured to be connected to a third path of address signal, the input end of the twenty-fourth inverter is configured to be connected to a fourth path of address signal, the output end of the twenty-fourth inverter is connected to the fourth input end of the fourth nand gate, the first input end of the fifth nand gate is configured to be connected to a fifth path of address signal, the second input end of the fifth nand gate is configured to be connected to a sixth path of address signal, the input end of the twenty-fifth inverter is configured to be connected to a seventh path of address signal, the output end of the twenty-fifth inverter is configured to be connected to a fifth path of address signal, and the fifth input end of the fifth nand gate is configured to be connected to a ninth path of address signal;

The output end of the fourth NAND gate is connected with the first input end of the fifth NOR gate, the output end of the fifth NAND gate is connected with the second input end of the fifth NOR gate, the output end of the fifth NOR gate is connected with the first input end of the sixth NOR gate, the output end of the sixth NOR gate is connected with the first input end of the seventh NOR gate, the second input end of the sixth NOR gate is connected with the output end of the seventh NOR gate, the second input end of the seventh NOR gate is configured to be connected with the clock signal, the third input end of the seventh NOR gate is configured to be connected with the power-on reset signal, and the output end of the seventh NOR gate is configured to output the circulating signal.

9. The integrated circuit of claim 1, wherein the ROM module comprises:

A decoder unit connected to the address module and configured to generate a decoding signal according to the address signal;

and the encoder unit is connected with the decoder unit and the address module and is configured to generate the N paths of encoded signals according to the decoding signals and the address signals.

10. An alarm device comprising an integrated circuit as claimed in any one of claims 1 to 9, and: