CN108615498B - Gate drive circuit, display panel and display device - Google Patents
Gate drive circuit, display panel and display device Download PDFInfo
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- CN108615498B CN108615498B CN201810458282.8A CN201810458282A CN108615498B CN 108615498 B CN108615498 B CN 108615498B CN 201810458282 A CN201810458282 A CN 201810458282A CN 108615498 B CN108615498 B CN 108615498B
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- 239000010409 thin film Substances 0.000 claims description 6
- 230000006641 stabilisation Effects 0.000 claims description 4
- 238000011105 stabilization Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 16
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 12
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 12
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 9
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 9
- 238000004088 simulation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 4
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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- 230000004048 modification Effects 0.000 description 2
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- 101000854879 Homo sapiens V-type proton ATPase 116 kDa subunit a 2 Proteins 0.000 description 1
- 101000854873 Homo sapiens V-type proton ATPase 116 kDa subunit a 4 Proteins 0.000 description 1
- 102100020737 V-type proton ATPase 116 kDa subunit a 4 Human genes 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention discloses a grid driving circuit, a display panel and a display device, wherein each grid driving unit of the grid driving circuit comprises: a first transistor, a control terminal of which receives the fourth clock signal, a first path terminal of which receives a previous stage gate driving signal, and a second path terminal of which is connected to the first node to precharge a voltage of the first node to a high level voltage or pull down the voltage of the first node to a low level signal; the control end of the second transistor is connected with the first node, the first path end receives a second clock signal, and the second path end is connected with the output end to provide a current-stage grid driving signal; and the stabilizing module is connected with the first node and stabilizes the current-level gate driving signal to a low-level signal according to the first node voltage and the second clock signal.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving circuit, a display panel and a display device.
Background
With the development of display devices, the application of integrated Gate Driver In Array (GIA) technology is becoming more and more extensive, and this technology not only can reduce thousands of wires, make the display device more symmetrical and compact, but also can reduce cost and improve the resolution and the degree of bending of the display panel.
Fig. 1 shows a schematic structure of a gate driving unit of a gate driving circuit in the related art. As shown in FIG. 1, the gate driving unit is composed of seven transistors T1-T7 and two capacitors C1And C2The gate driving signal Vo of the current stage is generated according to the front stage gate driving signal GN-4, the rear stage gate driving signal GN +4, the first clock signal CLK1 to the fourth clock signal CLK 4. After the gate driving unit completes the effective output of the present-stage gate driving signal Vo (the present-stage gate driving signal Vo is at a high level), the present-stage gate driving signal Vo needs to be maintained at a low level. When the clock signal CLK2 is at a high level and Vo is at a low level, the capacitor C2The voltage at the node D is coupled to the high level, the transistor T5 and the transistor T7 are turned on, and the low level signal V is asserted at this timeLThe voltage of the node Q and the current-stage gate driving signal Vo are maintained at low levels by the transistor T5 and the transistor T7, respectively, so as to achieve the purpose of noise reduction.
However, in the prior art, the noise reduction process only occurs during the period when CLK2 is at high level, and therefore, the circuit has the problems of poor stability, large noise, small noise margin, and the like. In addition, the number of components of the circuit is large, so that the narrow frame of the panel is not facilitated.
Disclosure of Invention
In view of the above, the present invention provides a gate driving circuit, a display panel and a display device, which solve the above problems in the prior art, in which the first transistor pulls down the first node voltage to a low level signal, so as to prolong the noise reduction time and improve the problems of poor circuit stability, large noise, small noise margin and the like in the prior art.
According to a first aspect of the present invention, there is provided a gate driving circuit comprising a plurality of stages of gate driving units, each stage of the gate driving units comprising: a first transistor, a control terminal of which receives a fourth clock signal, a first path terminal of which receives a previous stage gate driving signal, and a second path terminal of which is connected to the first node to precharge a voltage of the first node to a high level voltage or pull down the voltage of the first node to a low level signal; a control end of the second transistor is connected with the first node, a first path end receives a second clock signal, and a second path end is connected with an output end to provide a current-stage grid driving signal; and the stabilizing module is connected with the first node, and stabilizes the current-stage gate driving signal to the low-level signal according to the first node voltage and the second clock signal when the first transistor and the second transistor are both turned off.
Preferably, the fourth clock signal and the second clock signal do not overlap each other.
Preferably, the period and duty ratio of the fourth clock signal and the second clock signal are the same, and the phase difference is half a period.
Preferably, the gate driving circuit further includes a first capacitor, and two ends of the first capacitor are respectively connected to the control end of the second transistor and the second pass end to implement bootstrapping according to the second clock signal.
Preferably, the stabilizing module comprises: a pull-down control unit providing a second node voltage to a second node according to the first node voltage and the second clock signal; and the pull-down unit is connected with the pull-down control unit and the second node, and maintains the first node voltage and the current-stage gate driving voltage at the low-level signal under the control of the second node voltage.
Preferably, the pull-down control unit includes a second capacitor and a third transistor, a control end of the third transistor is connected to the first node, a first pass end of the third transistor receives a low-level signal, a first end of the second capacitor receives the second clock signal, and a second end of the second capacitor and a second pass end of the third transistor are connected to the second node.
Preferably, the pull-down unit includes a fourth transistor and a fifth transistor, control ends of the fourth transistor and the fifth transistor are connected to the second node, first path ends of the fourth transistor and the fifth transistor receive a low-level signal, a second path end of the fourth transistor is connected to a second path end of the second transistor, and a second path end of the fifth transistor is connected to the first node.
Preferably, the transistors in the gate driving circuit are implemented by N-channel thin film transistors or P-channel thin film transistors.
According to a second aspect of the present invention, a display panel is provided, which includes the gate driving circuit described above.
According to a third aspect of the present invention, there is provided a display device comprising the display panel described above.
In the gate driving circuit of the embodiment of the invention, the first transistor pre-charges the first node voltage or pulls down the first node voltage to a low level signal by using the fourth clock signal and the preceding stage gate driving signal, thereby realizing multiplexing of the first transistor; the stabilizing module keeps the current-stage grid driving signal at a low-level signal in a stabilizing stage through the first node voltage and the second clock signal, so that the aim of keeping the current-stage grid driving signal at a low level after the grid driving unit finishes effective output of the current-stage grid driving signal is fulfilled. Compared with the prior art, in the gate driving circuit of the embodiment of the invention, due to multiplexing of the first transistor, the first transistor charges the first node in the pre-charging stage, and discharges the first node in the pull-down stage, and in the stabilizing stage, the first transistor can stably maintain the voltage of the first node at a low level for noise reduction, namely, the noise of the voltage of the first node at the low level is reduced, so that the noise tolerance of the gate driving circuit is increased, and the stability of the gate driving circuit is improved. The display panel of the present invention has the same effects as the display device.
In addition, each stage of gate driving unit of the gate driving circuit in the embodiment of the invention is composed of five transistors and two capacitors, and each stage of gate driving unit only needs two clock signals.
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The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic structure diagram of a gate driving unit in the prior art.
Fig. 2 shows a schematic structural diagram of a display device in an embodiment of the present invention.
Fig. 3 shows a schematic structural diagram of a gate driving circuit in an embodiment of the invention.
Fig. 4 shows a schematic structural diagram of an ith-stage gate driving unit in an embodiment of the present invention.
Fig. 5 is a timing diagram of the ith gate driving unit according to an embodiment of the present invention.
Fig. 6A to 6E are circuit operation simulation diagrams showing the ith-stage gate driving unit in the embodiment of the present invention.
Detailed Description
In order to make the objects and aspects of the present invention clearer and more convenient to implement, the present invention will be described in further detail with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Fig. 2 shows a schematic structural diagram of a display device in an embodiment of the present invention. As shown in fig. 2, the display device in the embodiment of the present invention includes a display panel. The display panel includes: the timing control circuit 1100, the source driving circuit 1200, the gate driving circuit 1300, and the pixel array 1400 arranged in the display region, wherein the gate driving circuit 1300 may be integrated at both sides of the pixel array 1400. The pixel array 1400 includes a plurality of pixel units 1410, the gate driving circuit 1300 is connected to the corresponding pixel unit through n gate lines G1 to Gn, the source driving circuit 1200 is connected to the corresponding pixel unit through m data lines S1 to Sm, and the timing control circuit 1100 is connected to the source driving circuit 1200 and the gate driving circuit 1300, respectively, where n and m are non-zero natural numbers.
A plurality of pixel units 1410 are arranged in an array, and each pixel unit 1410 includes a transistor 1411 and a pixel capacitance 1412 (formed by a pixel electrode and a common electrode). The transistor 1411 in each pixel cell 1410 has a gate connected to a corresponding gate line, a source connected to a corresponding data line, and a drain connected to a pixel electrode in the corresponding pixel cell 1410.
The timing control circuit 1100 is used for providing timing signals to the source driving circuit 1200 and the gate driving circuit 1300, and the timing signals include a plurality of clock signals and a plurality of Start Vertical (STV) signals. The source driving circuit 1200 is configured to apply a gray scale voltage corresponding to display data to the corresponding pixel electrode 1412 when the transistor 1411 in the pixel unit 1410 is turned on. The gate driving circuit 1300 is used for providing a gate driving signal to the gate line 1430 according to a timing signal.
In the following description of the embodiments of the present invention, if not otherwise specified, i is a natural number of 1 or more and n or less.
Fig. 3 shows a schematic structural diagram of a gate driving circuit in an embodiment of the invention. It should be noted that the structure of the gate driving circuit in the embodiment of the present invention is not limited thereto, and those skilled in the art may substitute other embodiments. As shown in fig. 3, a gate driving circuit 1300 according to an embodiment of the present invention includes a plurality of stages of gate driving units GIA [1] to GIA [ n ]. The gate driving units of each stage respectively have a preceding driving end for receiving a preceding stage gate driving signal G [ i-4] or a start signal, a clock signal CLKA and CLKB corresponding to each stage of gate driving unit, a low level receiving end for receiving a low level signal VGL, and an output end for outputting the present stage gate driving signal G [ i ], wherein the reference signal VGL is a low level signal, and signals received by the preceding driving ends of the first stage gate driving unit GIA [1], the second stage gate driving unit GIA [2], the third stage gate driving unit GIA [3], and the fourth stage gate driving unit GIA [4] are respectively a first start signal STV1, a second start signal STV2, a third start signal STV3, and a fourth start signal STV4 provided by the timing control circuit directly or through the source driving circuit.
Fig. 4 shows a schematic structural diagram of an ith-stage gate driving unit in an embodiment of the present invention. It should be noted that the transistors mentioned in this embodiment are all N-type thin film transistors, and the first via terminal and the second via terminal of each transistor may be interchanged (i.e., the drain and the source may be interchanged). Implementations of the invention are not so limited and in some other embodiments the transistors may also include P-type thin film transistors.
As shown in fig. 4, the gate driving unit includes: a first transistor T1, a second transistor T2, and a stabilization module 1310.
The gate (control terminal) of the first transistor T1 receives the fourth clock signal CLK4, the source (first path terminal) of the first transistor T1 receives the previous stage gate driving signal G [ i-4], and the drain (second path terminal) of the first transistor T1 is connected to the first node Q1 to precharge the voltage of the first node Q1 to a high level voltage or pull down the voltage of the first node Q1 to a low level signal. The gate of the second transistor T2 is connected to the first node Q1, the source of the second transistor T2 receives the second clock signal CLK2, and the drain of the second transistor T2 is connected to the output terminal to supply the present stage gate driving signal G [ i ]. The stabilizing module 1310 is connected to the first node Q1, and stabilizes the gate driving signal G [ i ] of the current stage to a low level signal according to the voltage of the first node Q1 and the second clock signal CLK 2.
In some preferred embodiments, the gate driving unit further includes a first capacitor C1. Both ends of the first capacitor C1 are connected to the gate and the drain of the second transistor T2, respectively, to achieve bootstrap according to the second clock signal CLK 2.
In an embodiment of the present invention, the stabilization module 1310 includes: a pull-down control unit 1311 and a pull-down unit 1312.
The pull-down control unit 1311 supplies the second node voltage to the second node Q2 according to the first node Q1 voltage and the second clock signal CLK 2. The pull-down unit 1312 and the pull-down control unit 1311 are connected to the second node Q2, and the pull-down unit 1312 maintains the voltage of the first node Q1 and the current-stage gate driving signal G [ i ] at low level under the control of the voltage of the second node Q2. The pull-down control unit 1311 includes a second capacitor C2 and a third transistor T3, a gate of the third transistor T3 is connected to the first node Q1, a source of the third transistor T3 receives a low level signal VGL, a first end of the second capacitor C2 receives a second clock signal CLK2, a second end of the second capacitor C2 and a drain of the third transistor T3 are connected to the second node Q2. The pull-down unit 1312 includes a fourth transistor T4 and a fifth transistor T5, gates of the fourth transistor T4 and the fifth transistor T5 are connected to the second node Q2, sources of the fourth transistor T4 and the fifth transistor T5 receive a low level signal VGL, a drain of the fourth transistor T4 is connected to a drain of the second transistor T2, and a drain of the fifth transistor T5 is connected to the first node Q1.
Fig. 5 is a timing diagram illustrating an ith gate driving unit in the display device according to the embodiment of the invention. As shown in fig. 5, each duty cycle of the ith stage gate driving unit includes a precharge phase L1, a bootstrap charge phase L2, a pull-down phase L3, and a stabilization phase L4. The phases of two adjacent clock signals are different by 1/4 periods T, the duty ratio of each clock signal is the same, the periods T are the same, and the fourth clock signal CLK4 and the second clock signal CLK2 do not overlap each other. The following description will sequentially describe the four phases with reference to fig. 4 and 5, taking as an example that the period T and the duty ratio of the fourth clock signal CLK4 and the second clock signal CLK2 are the same and the phase difference is a half period T.
In the precharge stage L1, the fourth clock signal CLK4 is at a high level, the transistor T1 is turned on, the previous stage gate driving signal G [ i-4] is at a high level, so that the voltage of the first node Q1 is at a first high level, the transistor T2 is turned on, the second clock signal CLK2 is at a low level, the transistor T3 is turned on, the reference signal VGL is at a low level, the voltage of the second node Q2 is at a low level, the transistor T4 and the transistor T5 are turned off, and at this time, the present stage gate driving signal G [ i ] is at a low level.
In the bootstrap charging phase L2, the fourth clock signal CLK4 is at a low level, the transistor T1 is turned off, the voltage of the first node Q1 is maintained at a first high level, the transistor T2 is turned on, the second clock signal CLK2 is at a high level, the present stage gate driving signal G [ i ] rises to a high level, the voltage of the first node Q1 is set to a high level by the bootstrap effect of the first capacitor C1, the second clock signal CLK2 changes from the high level to the low level, and the present stage gate driving signal G [ i ] is pulled down.
In the pull-down stage L3, the fourth clock signal CLK4 is high, the transistor T1 is turned on, the previous gate driving signal G [ i-4] is low, the voltage at the first node Q1 is low, the transistor T2 is turned off, and the present gate driving signal G [ i ] is low.
In the stable period L4, the second clock signal CLK2 is at a high level, the voltage of the second node Q2 is set at a high level by the coupling action of the second capacitor C2, the transistor T4 and the transistor T5 are turned on, the reference signal VGL is a low level signal, the voltage of the first node Q1 and the present-stage gate drive signal G [ i ] are stably maintained at a low-level potential, the fourth clock signal CLK4 is at a high level, the transistor T1 is turned on, the previous-stage gate drive signal G [ i-4] is at a low level, the voltage of the first node Q1 is stably maintained at a low-level potential, and the first node voltage Q1 and the present-stage gate drive signal G [ i ] are continuously and stably maintained at a low level by alternately setting the second clock signal CLK2 and the fourth clock signal CLK4 at a high level.
Fig. 6A to 6E are circuit operation simulation diagrams illustrating an ith-stage gate driving unit in the display device according to the embodiment of the present invention. Fig. 6A is a simulation diagram of the second clock signal CLK2, fig. 6B is a simulation diagram of the fourth clock signal CLK4, fig. 6C is a simulation diagram of the voltage of the first node Q1, fig. 6D is a simulation diagram of the voltage of the second node Q2, and fig. 6E is a simulation diagram of the present-stage gate driving signal G [ i ]. Wherein the abscissa is time in seconds and the ordinate is voltage in volts.
In the gate driving circuit of the embodiment of the invention, the first transistor pre-charges the first node voltage or pulls down the first node voltage to a low level signal by using the fourth clock signal and the preceding stage gate driving signal, thereby realizing multiplexing of the first transistor; the stabilizing module keeps the current-stage grid driving signal at a low-level signal in a stabilizing stage through the first node voltage and the second clock signal, so that the aim of keeping the current-stage grid driving signal at a low level after the grid driving unit finishes effective output of the current-stage grid driving signal is fulfilled. Compared with the prior art, in the gate driving circuit of the embodiment of the invention, due to multiplexing of the first transistor, the first transistor charges the first node in the pre-charging stage, and discharges the first node in the pull-down stage, and in the stabilizing stage, the first transistor can stably maintain the voltage of the first node at a low level for noise reduction, namely, the noise of the voltage of the first node at the low level is reduced, so that the noise tolerance of the gate driving circuit is increased, and the stability of the gate driving circuit is improved. The display panel of the present invention has the same effects as the display device.
In addition, each stage of gate driving unit of the gate driving circuit in the embodiment of the invention is composed of five transistors and two capacitors, and each stage of gate driving unit only needs two clock signals.
In the foregoing, numerous specific details of the invention are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (5)
1. A gate driving circuit comprising a plurality of stages of gate driving units, wherein each stage of the gate driving units comprises:
a first transistor, a control terminal of which receives a fourth clock signal, a first path terminal of which receives a previous stage gate driving signal, and a second path terminal of which is connected to the first node to precharge a voltage of the first node to a high level voltage or pull down the voltage of the first node to a low level signal;
a control end of the second transistor is connected with the first node, a first path end receives a second clock signal, and a second path end is connected with an output end to provide a current-stage grid driving signal;
a stabilizing module connected to the first node, the stabilizing module stabilizing the current-stage gate driving signal to the low-level signal according to the first node voltage and the second clock signal,
the stabilization module includes:
a pull-down control unit providing a second node voltage to a second node according to the first node voltage and the second clock signal;
a pull-down unit connected to the pull-down control unit and the second node, the pull-down unit maintaining the first node voltage and the current gate driving voltage at the low level signal under the control of the second node voltage,
the pull-down control unit comprises a second capacitor and a third transistor, a control end of the third transistor is connected with the first node, a first pass end of the third transistor receives a low level signal, a first end of the second capacitor receives the second clock signal, a second end of the second capacitor and a second pass end of the third transistor are connected with the second node,
the pull-down unit comprises a fourth transistor and a fifth transistor, the control ends of the fourth transistor and the fifth transistor are connected with the second node, the first path ends of the fourth transistor and the fifth transistor receive low-level signals, the second path end of the fourth transistor is connected with the second path end of the second transistor, the second path end of the fifth transistor is connected with the first node,
the fourth clock signal and the second clock signal are not overlapped with each other, the period and the duty ratio of the fourth clock signal and the second clock signal are the same, the phase difference is half period,
the number of clock signals received by each stage of the gate driving unit is 2, and a fourth clock signal in the gate driving unit of the present stage serves as a second clock signal in the gate driving unit of the previous stage to generate the gate driving signal of the previous stage.
2. The gate driving circuit according to claim 1, further comprising a first capacitor, wherein two ends of the first capacitor are respectively connected to the control terminal of the second transistor and the second pass terminal to realize bootstrap according to the second clock signal,
and each stage of the grid driving unit is a circuit structure formed by five transistors and two capacitors.
3. A gate driver circuit according to claim 1 or 2, wherein the transistors in the gate driver circuit are implemented by N-channel thin film transistors or P-channel thin film transistors.
4. A display panel comprising the gate driver circuit according to any one of claims 1 to 3.
5. A display device characterized by comprising the display panel according to claim 4.
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| CN114120884A (en) * | 2020-09-01 | 2022-03-01 | 深圳市柔宇科技股份有限公司 | Display panel light-emitting drive circuit and display panel |
| CN113140176B (en) * | 2021-04-12 | 2022-04-08 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
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| CN103839510A (en) * | 2014-03-26 | 2014-06-04 | 华映视讯（吴江）有限公司 | Gate driving circuit |
| CN106531048A (en) * | 2016-11-29 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit, display panel and driving method |
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| JP2007242129A (en) * | 2006-03-08 | 2007-09-20 | Mitsubishi Electric Corp | Shift register circuit and image display device having the circuit |
| CN102842278B (en) * | 2012-08-06 | 2015-09-02 | 北京大学深圳研究生院 | Gate drive circuit unit, gate driver circuit and display |
| CN103500561B (en) * | 2013-10-12 | 2015-06-17 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN106910450B (en) * | 2017-04-10 | 2021-01-29 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
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| CN103839510A (en) * | 2014-03-26 | 2014-06-04 | 华映视讯（吴江）有限公司 | Gate driving circuit |
| CN106531048A (en) * | 2016-11-29 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit, display panel and driving method |
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