CN106910450B - Gate drive circuit and display device - Google Patents
Gate drive circuit and display device Download PDFInfo
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- CN106910450B CN106910450B CN201710229075.0A CN201710229075A CN106910450B CN 106910450 B CN106910450 B CN 106910450B CN 201710229075 A CN201710229075 A CN 201710229075A CN 106910450 B CN106910450 B CN 106910450B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention discloses a gate driving circuit and a display device, wherein each stage of gate driving unit in the gate driving circuit comprises: the main circuit is used for generating a first grid driving signal according to a first input signal, a second input signal, a first clock signal, a second clock signal and a third clock signal; and the pull-down circuit is used for generating a first pull-down signal and a second pull-down signal according to the second clock signal and the fourth clock signal, and an output end of the main circuit, which is used for providing the first grid signal, is connected with an output end of the pull-down circuit, which is respectively used for providing the first pull-down signal and the second pull-down signal, so that the first grid driving signal is pulled down by the first pull-down signal and the second pull-down signal to form a grid driving signal of the grid driving unit at the current stage. The display device provided by the invention has stable output, can be suitable for the design of a narrow frame, and has wider application range.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit and a display device.
Background
A display device generally includes a display panel, a gate driving circuit, and a source driving circuit. The display panel includes a pixel array formed of a plurality of pixel units, each of which includes a thin film transistor. In the pixel array, the grid electrodes of the thin film transistors in the pixel units in the same row are connected with a grid electrode driving circuit through the same scanning line, and the grid electrode driving circuit gates the pixel units in each row in the pixel array row by row through a plurality of scanning lines; the source electrodes or the drain electrodes of the thin film transistors in the pixel units in the same row are connected with a source electrode driving circuit through the same data line, and the source electrode driving circuit applies gray scale voltage to the pixel units in each row through a plurality of data lines, so that the display panel presents images.
In order to ensure the stability of the output gate driving signal, the conventional gate driving circuit generally adopts a noise reduction circuit including a Thin Film Transistor (TFT) to reduce noise, but this also increases power consumption, which is not favorable for the design of a narrow frame of the circuit.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
The invention aims to provide a gate driving circuit and a display device which are suitable for the design of a narrow frame, have a better noise reduction effect and output a driving signal more stably.
According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of stages of gate driving units for driving one corresponding gate line on a display panel, respectively, each of the stages of gate driving units including: the main circuit is used for generating a first grid driving signal according to a first input signal, a second input signal, a first clock signal, a second clock signal and a third clock signal; and the pull-down circuit is used for generating a first pull-down signal and a second pull-down signal according to the second clock signal and the fourth clock signal, and an output end of the main circuit, which is used for providing the first grid signal, is connected with an output end of the pull-down circuit, which is respectively used for providing the first pull-down signal and the second pull-down signal, so that the first grid driving signal is pulled down by the first pull-down signal and the second pull-down signal to form a grid driving signal of the grid driving unit at the current stage.
Preferably, the pull-down circuit includes a first pull-down module and a second pull-down module, the first pull-down module and the second pull-down module receive a low supply voltage, the first pull-down module is connected to the main circuit at a first node, the first pull-down module generates the first pull-down signal according to the second clock signal and a voltage of the first node, and the second pull-down module generates the second pull-down signal according to the fourth clock signal and the low supply voltage.
Preferably, the first pull-down module includes a first capacitor and first to fifth transistors, one end of the first capacitor and a first path end of the third transistor receive the second clock signal, the other end of the first capacitor and the control terminal of the third transistor are connected with the first pass end of the first transistor, a second pass terminal of the third transistor, a control terminal of the fourth transistor, and a control terminal of the fifth transistor are connected to a first pass terminal of the second transistor, a control terminal of the first transistor and a first path terminal of the fourth transistor are connected to the first node, a first path end of the fifth transistor is configured to output a first pull-down signal, and a second path end of the first transistor, a second path end of the second transistor, a second path end of the fourth transistor, and a second path end of the fifth transistor receive the low supply voltage.
Preferably, the second pull-down module includes a sixth transistor, a control terminal of the sixth transistor receives the fourth clock signal, a first path terminal of the fourth transistor outputs a second pull-down signal, and a second path terminal of the fourth transistor receives the low supply voltage.
Preferably, the main circuit includes an input module and an output module, the input module and the output module are connected at a first node, the input module is configured to provide a voltage of the first node according to the first input signal, the second input signal, the first clock signal and the third clock signal, and the output module is configured to generate a first gate driving signal according to the second clock signal and the voltage of the first node.
Preferably, the input module includes a seventh transistor and an eighth transistor, a first path end of the seventh transistor receives the first clock signal, a second path end of the seventh transistor and a first path end of the eighth transistor are connected to the first node, a second path end of the eighth transistor receives the third clock signal, a control end of the seventh transistor receives the first input signal, and a control end of the eighth transistor receives the second input signal.
Preferably, the output module includes a second capacitor and a ninth transistor, a control terminal of the ninth transistor and one end of the second capacitor are connected to the first node, a first path terminal of the ninth transistor receives the second clock signal, and a second path terminal of the ninth transistor is connected to the other end of the second capacitor and outputs the first gate driving signal.
Preferably, the periods of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are all equal, and the duty ratios of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are all 50%.
Preferably, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal sequentially change from a low level to a high level, and an interval time at which the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal change from the low level to the high level is a quarter cycle.
According to another aspect of the present invention, there is also provided a display device including any one of the gate driver circuits described above.
Compared with the prior art, the gate drive circuit of the display device has a better noise reduction effect on the basis of being suitable for the design of a narrow frame, and the output drive signal is more stable.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Fig. 2 shows a schematic block diagram of an ith-stage gate driving unit in the display device according to the embodiment of the present invention.
Fig. 3 is a schematic structural diagram of an ith-stage gate driving unit in the display device according to the embodiment of the invention.
Fig. 4 is a timing diagram illustrating the operation of the ith gate driving unit in the display device according to the embodiment of the invention.
Fig. 5a to 5d respectively show the first node, the second node, the third node and the T-V curve of the gate driving signal of the current stage in the ith gate driving unit in the display device according to the embodiment of the invention.
Fig. 6 illustrates T-V curves of a third node in an ith-stage gate driving unit in the display device according to the embodiment of the present invention and the related art.
Fig. 7a shows the T-V curves of the present stage gate driving signal in the ith stage gate driving unit in the display device of the embodiment of the present invention and the related art at 27 ℃.
Fig. 7b shows the T-V curves of the present stage gate driving signal in the ith stage gate driving unit in the display device of the embodiment of the present invention and the related art at 70 c.
Fig. 8a shows a T-V curve of the first node in the ith stage gate driving unit in the display device of the embodiment of the present invention at 90 deg.c.
Fig. 8b shows a T-V curve of the present stage gate driving signal in the ith stage gate driving unit in the display device of the embodiment of the present invention at 90 ℃.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
Numerous specific details of the invention are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention.
As shown in fig. 1, the display device 1000 according to the embodiment of the invention includes a display panel 1100, a gate driving circuit 1200, a source driving circuit 1300 and a timing control circuit 1400, wherein the gate driving circuit 1200 and the display panel 1100 can be integrated on the same substrate to form an integrated gate driving structure, thereby realizing a narrow frame of the display device 1000.
The display panel 1100 includes m × n pixel units 1110 arranged in an m × n array, n scan lines transmitting gate driving signals G [1] to G [ n ], respectively, and m data lines transmitting data signals D [1] to D [ m ], respectively, m and n being non-zero natural numbers. Each pixel unit 1110 includes a pixel electrode and a transistor, such as a thin film transistor, for turning on or off the pixel electrode. In the display panel 1100, the gates of the transistors in the pixel units located in the same row (the "row" corresponds to, for example, the lateral direction shown in the figure) are connected and one scanning line is led out to the edge area of the display panel, and the pixel units in n rows output gate driving signals G [1] to G [ n ] through the corresponding scanning lines, respectively; the sources of the transistors in the pixel units in the same column (the "column" corresponds to the longitudinal direction shown in the figure, for example) are connected and lead out a data line, and the m columns of pixel units output data signals D [1] to D [ m ] through the corresponding data lines respectively; in each pixel unit, the drain of the transistor is connected to the pixel electrode.
The gate driving circuit 1200 integrated with the display panel and on the same substrate includes a plurality of gate driving units GIA [1] to GIA [ n ], the gate driving units GIA [1] to GIA [ n ] respectively apply gate driving signals G [1] to G [ n ] to each row of pixel units in the display panel 1100 through n scan lines, thereby triggering each row of pixel units in the display panel 1100 line by line, so that transistors in all pixel units in the triggered pixel unit line are simultaneously turned on to receive data signals D [1] to D [ m ] provided by the source driving circuit 1300 through data lines.
The timing control circuit 1400 is configured to provide a plurality of clock signals and control signals (Start Vertical, STV) such as a Start signal (e.g., a front Start signal and a rear Start signal) to the source driver circuit 1300 and the gate driver circuit 1200, where the Start signal is, for example, a Start signal for one frame.
Fig. 1 shows only a part of the connection relationship between or within each circuit in the display device. In the following description of the embodiments of the present invention, i is a natural number of 1 or more and n or less unless otherwise specified.
Fig. 2 shows a schematic block diagram of an ith-stage gate driving unit in the display device according to the embodiment of the present invention.
As shown in fig. 2, each stage of the gate driving unit GIA [ i ] has, for example, a front stage input terminal, a rear stage input terminal, a first clock terminal, a second clock terminal, a third clock terminal, a fourth clock terminal, a power supply terminal, and a driving terminal.
The front stage input end of each stage of gate driving unit GIA [ i ] receives a first input signal in1, the rear stage input end receives a second input signal in2, the first clock end, the second clock end, the third clock end and the fourth clock end respectively receive a first clock signal clk1, a second clock signal clk2, a third clock signal clk3 and a fourth clock signal clk4, the power supply end receives a low power supply voltage VGL, and the driving end outputs a driving signal Gn [ i ] of the gate driving unit.
When the natural number i is equal to or greater than 3 and equal to or less than n, the preceding-stage input terminal of the ith-stage gate driving unit GIA [ i ] receives the first input signal in1, and the first input signal in1 may be the gate driving signal G [ i-2] output by the i-2 th-stage gate driving unit GIA [ i-2], so as to precharge the ith-stage gate driving unit GIA [ i ]. For example, the previous stage input terminal of the 3 rd stage gate driving unit GIA [3] receives the gate driving signal G [1] outputted from the 1 st stage gate driving unit GIA [1], the previous stage input terminal of the 4 th stage gate driving unit GIA [4] receives the gate driving signal G [2] outputted from the 2 nd stage gate driving unit GIA [2], and so on. The first input signal in1 received at the previous input terminal of the 1 st stage gate driving unit GIA [1] is the previous stage start signal STV1 provided directly from the timing control circuit 140 or provided through the source driving circuit 130, and the first input signal in1 received at the previous input terminal of the 2 nd stage gate driving unit GIA [2] is the previous stage start signal STV2 provided directly from the timing control circuit 1400 or provided through the source driving circuit 1300.
When the natural number i is equal to or greater than 1 and equal to or less than n-2, the subsequent input terminal of the ith gate driving unit GIA [ i ] receives the second input signal in2, and the second input signal in2 may be the gate driving signal G [ i +2] output by the (i + 2) th gate driving unit GIA [ i +2 ]. For example, a rear stage input terminal of the 1 st stage gate driving unit GIA [1] receives the gate driving signal G [3] provided from the 3 rd stage gate driving unit GIA [3], and a rear stage input terminal of the 2 nd stage gate driving unit GIA [2] receives the gate driving signal G [4] provided from the 4 th stage gate driving unit GIA [4 ]. The second input signal in2 received at the rear stage input terminal of the nth stage gate driving unit GIA [ n ] is the rear stage start signal STV3 provided directly from the timing control circuit 1400 or through the source driving circuit 1300, and the second input signal in2 received at the rear stage input terminal of the (n-1) th stage gate driving unit GIA [ n-1] (not shown) is the rear stage start signal STV4 provided directly from the timing control circuit 1400 or through the source driving circuit 1300.
The ith gate driving unit GIA [ i ] includes a main circuit 1210 and a pull-down circuit 1220, wherein the main circuit 1210 includes an input module 1211 and an output module 1212, and the pull-down circuit 1220 includes a first pull-down module 1221 and a second pull-down module 1222.
The connection relationship and signal relationship of each block in the ith-stage gate driving unit GIA [ i ] will be described in detail below.
The output terminal of the input module 1211 is connected to the first node Q1, and the input module 1211 is configured to provide a voltage of the first node Q1 according to a first output signal in1 received by a front-stage input terminal of the stage gate driving unit, a second input signal in2 received by a rear-stage input terminal, a first clock signal clk1 received by the first clock terminal, and a third clock signal clk3 received by the third clock terminal.
The first pull-down module 1221 is connected to the first node Q1, and generates a first pull-down signal ctl1 according to the second clock signal clk2 received at the second clock terminal of the stage gate driving unit and the voltage of the first node Q1. The low level supply voltage of the first pull-down module 1221 is equal to the low supply voltage VGL.
The second pull-down module 1222 generates a second pull-down signal ctl2 according to a fourth clock signal clk4 received by a fourth clock terminal of the stage gate driving unit. The low supply voltage of the second pull-down module 1222 is equal to the low supply voltage VGL.
The output module 1212 is connected to the first node Q1, and generates the first gate driving signal gout1 according to the second clock signal clk2 received at the second clock terminal of the stage of gate driving units and the voltage of the first node Q1.
The output terminal of the output module 1212 for providing the first gate driving signal gout1 is connected to the output terminal of the first pull-down module 1221 for providing the first pull-down signal ctl1 and the output terminal of the second pull-down module 1222 for providing the second pull-down signal ctl2, so that the first pull-down signal ctl1 and the second pull-down signal ctl2 pull-down the first gate driving signal gout1 to form the gate driving signal G [ i ] of the current stage, thereby achieving noise reduction and stabilization of the gate driving signal G [ i ] of the current stage.
Fig. 3 is a schematic structural diagram of an ith-stage gate driving unit in the display device according to the embodiment of the invention. It should be noted that the transistors mentioned in this embodiment are all N-type thin film transistors, and the first via terminal and the second via terminal of each transistor may be interchanged (i.e., the drain and the source may be interchanged). But implementations of the invention are not limited thereto.
As shown in fig. 4 and 3, the input module 1211 includes a seventh transistor T7 and an eighth transistor T8, a control terminal of the seventh transistor T7 receives the first input signal in1, a control terminal of the eighth transistor T8 receives the second input signal in2, a drain of the seventh transistor T7 receives the first clock signal clk1, a source of the seventh transistor T7 is connected to a drain of the eighth transistor T8 for providing the voltage of the first node Q1, and a source of the eighth transistor T8 receives the third clock signal clk 3.
The first pull-down module 1221 includes a first capacitor C1 and first to fourth transistors T4, a first end of the first capacitor C1 and a drain of the third transistor T3 receive the second clock signal clk2, the other end of the first capacitor C1, a control end of the third transistor T3, and a drain of the first transistor TI are connected to a second node Q2, a drain of the fourth transistor T4 is connected to the first node Q1, a drain of the second transistor T2, a source of the third transistor T3, a control end of the fourth transistor T4, and a control end of the fifth transistor T5 are connected to a third node Q3, a source of the first transistor TI, a source of the second transistor T2, and a source of the fifth transistor T5 receive the low supply voltage VGL, and a drain of the fifth transistor T5 outputs the first pull-down signal ctl 1.
The second pull-down module 1222 includes a sixth transistor T6, a control terminal of the sixth transistor T6 receives the fourth clock signal clk4, a source of the sixth transistor T6 receives the low supply voltage VGL, and a drain of the sixth transistor T6 is configured to output the second pull-down signal ctl 2.
The output module 1212 includes a second capacitor C2 and a ninth transistor T9, one end of the second capacitor C2 and a control end of the ninth transistor T9 are connected to the first node Q1, a drain of the ninth transistor T9 receives the second clock signal clk2, and a source of the ninth transistor T9 and the other end of the second capacitor C2 are connected to output a first gate driving signal gout 1.
The source of the ninth transistor T9, the drain of the fifth transistor T5 and the drain of the sixth transistor T6 are connected such that the first pull-down signal ctl1 and the second pull-down signal ctl2 pull down the first gate driving signal gout1 to form the present stage of gate driving signal G [ i ].
In the gate driving circuit 1200, the operation process of each stage of the gate driving unit GIA [ i ] is divided into a pre-charge stage, a pull-up stage, a pull-down stage and a stabilization stage, and the operation stages of each gate driving unit are described below with reference to the drawings.
Fig. 5 is a timing diagram illustrating the operation of the ith gate driving unit in the display device according to the embodiment of the invention.
As shown in fig. 5 and 4, the periods of the first clock signal clk1, the second clock signal clk2, the third clock signal clk3, and the fourth clock signal clk4 are all equal, and the duty ratios of the first clock signal clk1, the second clock signal clk2, the third clock signal clk3, and the fourth clock signal clk4 are all 50%. In an operation of the i-th stage gate driving unit GIA [ i ], the first clock signal clk1, the second clock signal clk2, the third clock signal clk3, and the fourth clock signal clk4 sequentially change from a low level to a high level, and an interval time at which the first clock signal clk1, the second clock signal clk2, the third clock signal clk3, and the fourth clock signal clk4 change from a low level to a high level is one quarter cycle.
During the precharge phase P1: the first input signal in1 is at a high level, the second input signal in2 is at a low level, the seventh transistor T7 is turned on but the eighth transistor T8 is turned off, the first clock signal clk1 changes from a low level to a high level, and at this time, the first node Q1 is charged to the first voltage through the seventh transistor T7, so that the ninth transistor T9 is turned on, and since the second clock signal clk2 is at a low level, the ninth transistor T9 outputs the first gate driving signal gout1 at a low level. Since the first node Q1 is charged to the first voltage, the first transistor TI and the second transistor T2 are turned on, the second node Q2 and the third node Q3 are both low, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off. The fourth clock signal clk4 is at a high level, the sixth transistor T6 is turned on, and the second pull-down signal ctl2 pulls down the first gate driving signal gout1 to form the low-level gate driving signal G [ i ].
Pull-up phase P2: the first input signal in1 and the second input signal in2 are both low, the seventh transistor T7 and the eighth transistor T8 are both off, since the first node Q1 has been charged to the first voltage in the pre-charge phase, the ninth transistor T9 is turned on, the second clock signal clk2 changes from low to high, and due to the bootstrap action of the second capacitor C2, the voltage of the first node Q1 is further pulled up to the second voltage, the first transistor TI and the second transistor T2 are turned on, the second node Q2 and the third node Q3 continue to maintain the low level, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned off, the fourth clock signal clk4 is at the low level, the sixth transistor T6 is turned off, since the voltage of the first node Q1 is further pulled up to the second voltage to make the ninth transistor T9 more fully conductive, the ninth transistor T9 outputs the first gate driving signal gout1 (equal to the present stage gate driving signal gi) of high level.
In pull-down phase P3: the first input signal in1 is at a low level, the second input signal in2 is at a high level, the seventh transistor T7 is turned off and the eighth transistor T8 is turned on, the first clock signal clk1 is at a low level, the third clock signal clk3 is at a high level, the eighth transistor T8 pulls down the voltage of the first node Q1 to the first level, the first transistor TI and the second transistor T2 are turned on, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned off, the ninth transistor T9 is turned on, because the second clock signal T2 is at a low level, the ninth transistor T9 outputs a first gate driving signal at a low level, the fourth clock signal 4 is at a high level, the sixth transistor T6 is turned on, and the second pull-down signal ctl2 pulls down the first gate driving signal gout1 to form a local gate driving signal G [ i ] at a low level.
In the stabilization phase P4: the first input signal in1 is at a low level, the second input signal in2 is at a high level, the seventh transistor T7 is turned off and the eighth transistor T8 is turned on, the third clock signal clk3 is at a low level, the eighth transistor T8 further pulls down the voltage of the first node Q1 to a low level, the first transistor TI, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are all turned off, the fourth clock signal clk4 is at a high level, the sixth transistor T6 is turned on, and the second pull-down signal ctl2 pulls down the first gate driving signal gout1 to form the low-level gate driving signal G [ i ].
Therefore, in the subsequent time (i.e., after the stable period), the current stage gate driving signal G [ i ] output by the current stage gate driving unit needs to be maintained at the low level, so as to obtain the ideal waveform. However, since the second clock signal clk2 is a clock signal, which will generate pulses continuously in the following time (i.e. after the stable period), it will affect the current-stage gate driving signal G [ i ] output by the current-stage gate driving unit, and in order to reduce these effects as much as possible, the embodiment of the present invention improves by using the first capacitor C1 and the first to fifth transistors.
Specifically, in the subsequent time, the voltage of the first node Q1 is at a low level, the first transistor TI, the second transistor T2, and the ninth transistor T9 are all turned off, when the second clock signal clk2 changes from a low level to a high level, the second clock signal clk2 pulls up the voltage of the second node Q2 to a high level through the second capacitor C2, so that the third transistor T3 is turned on, the voltage of the third node Q3 is pulled up to a high level through the third transistor T3, so that the fourth transistor T4 and the fifth transistor T5 are both turned on, and the first pull-down signal ctl1 pulls down the first gate driving signal gout1 to form the local gate driving signal G [ i ] at a low level.
Fig. 5a to 5d respectively show the first node, the second node, the third node and the T-V curve of the gate driving signal of the current stage in the ith gate driving unit in the display device according to the embodiment of the invention. As shown in fig. 5a to 5d, it can be visually observed that the process of the voltage variation of the first node, the second node, the third node and the gate driving signal of the current stage in the ith gate driving unit in the display device according to the embodiment of the present invention with time is consistent with the foregoing description of the voltage variation of each of the four operation stages (i.e., the pre-charge stage, the pull-up stage, the pull-down stage and the stabilization stage) of the ith gate driving unit in the display device according to the embodiment of the present invention, and the description is not repeated herein.
Fig. 6 illustrates T-V curves of a third node in an ith-stage gate driving unit in the display device according to the embodiment of the present invention and the related art. As shown in fig. 6, at the same time, the voltage of the third node in the ith gate driving unit in the display device according to the embodiment of the present invention is significantly higher than the voltage of the third node in the ith gate driving unit in the display device according to the related art.
Fig. 7a shows the T-V curves of the present stage gate driving signal in the ith stage gate driving unit in the display device of the embodiment of the present invention and the related art at 27 ℃. As shown in fig. 7a, under the condition of 27 ℃ and 0bias, the noise of the gate driving signal of the current stage in the i-th stage gate driving unit in the display device according to the embodiment of the present invention is significantly reduced compared to the noise of the gate driving signal of the current stage in the i-th stage gate driving unit in the display device of the prior art.
Fig. 7b shows the T-V curves of the present stage gate driving signal in the ith stage gate driving unit in the display device of the embodiment of the present invention and the related art at 70 c. As shown in fig. 7b, under the conditions of 70 ℃, -3bias, the noise of the gate driving signal of the current stage in the i-th stage gate driving unit in the display device according to the embodiment of the present invention is significantly reduced compared to the noise of the gate driving signal of the current stage in the i-th stage gate driving unit in the display device according to the prior art.
Fig. 8a shows a T-V curve of a first node in an i-th stage gate driving unit in the display device of the embodiment of the present invention at 90 c, and fig. 8b shows a T-V curve of a present stage gate driving signal in the i-th stage gate driving unit in the display device of the embodiment of the present invention at 90 c. Under the conditions of 90 ℃, -3bias, because the temperature condition is extreme, the present stage gate driving signal in the i-th stage gate driving unit in the display device of the prior art cannot be stably output, whereas in the display device of the embodiment of the present invention, as shown in fig. 8a and 8b, the first node in the i-th stage gate driving unit and the present stage gate driving signal both have stable outputs, and the noise level in the present stage gate driving signal is lower than 2V, which meets the basic specification.
Compared with the prior art, the invention is suitable for the design of a narrow frame, further reduces the noise in the gate driving signal output by each stage of gate driving unit, makes the driving signal more stable, improves the reliability of display and enlarges the application range of the display device.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (8)
1. A gate driving circuit comprising a plurality of stages of gate driving units for driving a corresponding gate line on a display panel, respectively, each of the plurality of stages of gate driving units comprising:
the main circuit is used for generating a first gate driving signal according to a first input signal, a second input signal, a first clock signal, a second clock signal and a third clock signal, a control end of the main circuit receives the first input signal and the second input signal as control signals, and an output end of the main circuit provides the first gate driving signal; and
the pull-down circuit comprises a first pull-down module and a second pull-down module which are respectively used for generating a first pull-down signal and a second pull-down signal, the output end of the first pull-down module and the output end of the second pull-down module are respectively connected with the output end of the main circuit, so that the first gate driving signal is pulled down by the first pull-down signal and the second pull-down signal to form a gate driving signal of the gate driving unit at the current stage,
the first pull-down module includes a first capacitor and first to fifth transistors, one end of the first capacitor and a first via terminal of the third transistor receive the second clock signal, the other end of the first capacitor and a control terminal of the third transistor are connected to the first via terminal of the first transistor, a second via terminal of the third transistor, a control terminal of the fourth transistor and a control terminal of the fifth transistor are connected to the first via terminal of the second transistor, the control terminal of the first transistor, the control terminal of the second transistor and the first via terminal of the fourth transistor are connected to the first node of the main circuit, the first via terminal of the fifth transistor is configured to output the first pull-down signal, and the second via terminal of the first transistor and the second via terminal of the second transistor are connected to the first node of the main circuit, The second path terminal of the fourth transistor and the second path terminal of the fifth transistor receive a low supply voltage,
the second pull-down module comprises a sixth transistor, a control terminal of the sixth transistor receives a fourth clock signal, a first path terminal of the sixth transistor outputs the second pull-down signal, a second path terminal of the sixth transistor receives the low supply voltage,
the interval time between the first clock signal, the second clock signal, the third clock signal and the fourth clock signal changing from low level to high level is one quarter of a cycle.
2. The gate driving circuit of claim 1, wherein the first pull-down module generates the first pull-down signal according to the second clock signal and a voltage of the first node, and the second pull-down module generates the second pull-down signal according to the fourth clock signal and the low supply voltage.
3. A gate drive circuit as claimed in claim 1, wherein the main circuit comprises an input block and an output block, the input block and the output block being connected at a first node,
the input module is used for providing the voltage of the first node according to the first input signal, the second input signal, the first clock signal and the third clock signal,
the output module is used for generating a first gate driving signal according to the second clock signal and the voltage of the first node.
4. A gate driving circuit as claimed in claim 3, wherein the input module comprises a seventh transistor and an eighth transistor, a first path terminal of the seventh transistor receives the first clock signal, a second path terminal of the seventh transistor and a first path terminal of the eighth transistor are connected to the first node, a second path terminal of the eighth transistor receives the third clock signal, a control terminal of the seventh transistor receives the first input signal, and a control terminal of the eighth transistor receives the second input signal.
5. A gate driving circuit according to claim 3, wherein the output module comprises a second capacitor and a ninth transistor, a control terminal of the ninth transistor and one terminal of the second capacitor are connected to the first node, a first path terminal of the ninth transistor receives the second clock signal, and a second path terminal of the ninth transistor is connected to the other terminal of the second capacitor and outputs the first gate driving signal.
6. The gate driving circuit of claim 1, wherein the periods of the first, second, third and fourth clock signals are all equal, and the duty cycles of the first, second, third and fourth clock signals are all 50%.
7. The gate driving circuit according to claim 6, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal sequentially change from a low level to a high level.
8. A display device comprising the gate driver circuit according to any one of claims 1 to 7.
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| CN201710229075.0A CN106910450B (en) | 2017-04-10 | 2017-04-10 | Gate drive circuit and display device |
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| CN107689219A (en) * | 2017-09-12 | 2018-02-13 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| KR102612946B1 (en) | 2017-09-26 | 2023-12-11 | 엘지디스플레이 주식회사 | Gate driver and display panel having the same |
| CN108109593B (en) * | 2017-12-01 | 2020-11-03 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
| CN108062935A (en) * | 2017-12-08 | 2018-05-22 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and display device |
| CN108615498B (en) * | 2018-05-14 | 2021-11-02 | 昆山龙腾光电股份有限公司 | Gate drive circuit, display panel and display device |
| CN109686291A (en) * | 2019-01-22 | 2019-04-26 | 福建华佳彩有限公司 | A kind of the GIP driving circuit and Notch display screen of Notch display screen |
| CN110969977A (en) * | 2019-12-02 | 2020-04-07 | 深圳市华星光电半导体显示技术有限公司 | Grid driving circuit, control method thereof and display device |
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