CN108573883A - System and method for being bonded to semiconductor element - Google Patents
System and method for being bonded to semiconductor element Download PDFInfo
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- CN108573883A CN108573883A CN201810210143.3A CN201810210143A CN108573883A CN 108573883 A CN108573883 A CN 108573883A CN 201810210143 A CN201810210143 A CN 201810210143A CN 108573883 A CN108573883 A CN 108573883A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 312
- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000010276 construction Methods 0.000 claims description 57
- 239000010949 copper Substances 0.000 claims description 44
- 229910052802 copper Inorganic materials 0.000 claims description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 34
- 238000005516 engineering process Methods 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 description 67
- 229910052782 aluminium Inorganic materials 0.000 description 63
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 60
- 239000004411 aluminium Substances 0.000 description 44
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Wire Bonding (AREA)
Abstract
A method of ultrasonic bond is carried out to semiconductor element, is included the following steps：(a) surface of multiple first conductive structures of the first semiconductor element is aligned with the respective surfaces of multiple second conductive structures of the second semiconductor element；(b) positioning bonding part is ultrasonically formed between several first conductive structures several second conductive structures corresponding in second conductive structure in first conductive structure；And (c) between first conductive structure and second conductive structure form complete bonding part.
Description
Cross reference to related applications
The application is that the part of submitted on May 5th, 2016 15/147, No. 015 application continues application, this 15/147,
No. 015 application is the divisional application for 14/822, No. 164 applications submitted for 10th in August in 2015, this 14/822, No. 164 applications
It is the continuity application of submitted on October 3rd, 2014 14/505, No. 609 applications (now for United States Patent (USP) 9,136,240), it should
14/505, No. 609 application requires the equity for the provisional application 61/888,203 submitted for 8th in August in 2013, in these applications
Each of content be incorporated herein by reference.
Technical field
The present invention relates to the formation of semiconductor packages, more particularly, to by semiconductor device bonded improvement system together
System and method.
Background technology
Traditional semiconductor packages generally includes die attached technique and lead key closing process.It is advanced in this industry
Semiconductor packaging (for example, flip-chip bonding, thermocompression bonding etc.) is just obtaining more concerns.For example, in thermocompression bonding
In, multiple interconnections are formed using heat and pressure between semiconductor element.
Although the application of Advanced Packaging increasingly increases, there are many limitations in these techniques, these limitations
Including such as related limitation with the relative infancy of some Advanced Packagings (relative infancy).Therefore, it is desirable to carry
For for by semiconductor device bonded improvement system and method together.
Invention content
Exemplary embodiment according to the present invention provides a kind of method carrying out ultrasonic bond to semiconductor element.Institute
The method of stating includes the following steps：(a) by the surface of multiple first conductive structures of the first semiconductor element and the second semiconductor element
The respective surfaces of multiple second conductive structures of part are aligned；(b) several first conductive knots in first conductive structure
Positioning bonding part is ultrasonically formed between structure several second conductive structures corresponding with second conductive structure；And
(c) complete bonding part is formed between first conductive structure and second conductive structure.
Another exemplary embodiment according to the present invention, provides a kind of bonding system.The bonding system includes using
In the support construction for supporting the first semiconductor element, first semiconductor element includes multiple first conductive structures.The key
Collaboration system further include bonding tool, the bonding tool be used for carry include multiple second conductive structures the second semiconductor element
Part, and for applying ultrasonic energy to second semiconductor element, with several in the multiple second conductive structure
Positioning key is formed between a second conductive structure several first conductive structures corresponding with the multiple first conductive structure
Conjunction portion.
Description of the drawings
From the following detailed description when read with the accompanying drawing figures, the present invention will be best understood.It is emphasized that according to logical
Normal practice, what the various features of attached drawing were not drawn to scale.On the contrary, for the sake of clarity, the size of various features is appointed
Meaning expands or reduces.Attached drawing includes following picture：
Figure 1A to Fig. 1 C is the block diagram of the part of ultrasonic bonding machine, they show that property is real according to an example of the present invention
Apply example by the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 2A is the block diagram of the part of ultrasonic bonding machine, and it illustrates another exemplary embodiments according to the present invention
By the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 2 B are the enlarged drawings of the part Fig. 2A " Fig. 2 B "；
Fig. 2 C are views of Fig. 2 B after ultrasonic bond；
Fig. 3 is the block diagram of the part of ultrasonic bonding machine, and it illustrates another exemplary embodiments according to the present invention
By the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 4 A are the block diagrams of the part of ultrasonic bonding machine, and it illustrates another exemplary embodiments according to the present invention
By the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 4 B are the enlarged drawings of the part Fig. 4 A " Fig. 4 B "；
Fig. 4 C are views of Fig. 4 B after ultrasonic bond；
Fig. 5 A are the block diagrams of the part of ultrasonic bonding machine, and it illustrates another exemplary embodiments according to the present invention
By the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 5 B are the enlarged drawings of the part Fig. 5 A " Fig. 5 B "；
Fig. 5 C are views of Fig. 5 B after ultrasonic bond；
Fig. 6 A are the block diagrams of the part of ultrasonic bonding machine, and it illustrates another exemplary embodiments according to the present invention
By the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 6 B are the enlarged drawings of the part Fig. 6 A " Fig. 6 B "；
Fig. 6 C are the views after a part of Fig. 6 A contacts between conductive structure；
Fig. 7 is the side that ultrasonic bond is carried out to semiconductor element for showing property embodiment according to an example of the present invention
The flow chart of method；
Fig. 8 A to Fig. 8 E are the block diagrams of the part of ultrasonic bonding machine, they show that property is real according to an example of the present invention
Apply example by the device bonded structure and method to lower semiconductor element of upper semiconductor；
Fig. 9 is the side that ultrasonic bond is carried out to semiconductor element for showing property embodiment according to an example of the present invention
The flow chart of method；
Figure 10 A to Figure 10 E are the block diagrams of the part of ultrasonic bonding machine, they show another example according to the present invention
Property embodiment by device bonded another structure and method to lower semiconductor element of upper semiconductor；
Figure 11 be show another exemplary embodiment according to the present invention to semiconductor element carry out ultrasonic bond
Another method flow chart；
Figure 12 A to Figure 12 D are the block diagrams of the part of ultrasonic bonding machine, they show another example according to the present invention
Property embodiment by device bonded another structure and method to lower semiconductor element of upper semiconductor；
Figure 13 be show another exemplary embodiment according to the present invention to semiconductor element carry out ultrasonic bond
Another method flow chart；
Figure 14 A to Figure 14 D are the block diagrams of the part of ultrasonic bonding machine, they show another example according to the present invention
Property embodiment by device bonded another structure and method to lower semiconductor element of upper semiconductor；And
Figure 15 be show another exemplary embodiment according to the present invention to semiconductor element carry out ultrasonic bond
Another method flow chart.
Specific implementation mode
As it is used herein, term " semiconductor element " means to include (or be configured to include) in subsequent step
Any structure of semiconductor chip or bare die.Illustrative semiconductor element includes exposed semiconductor bare chip, is located at substrate (example
Such as, lead frame, PCB, carrier etc.) on semiconductor bare chip, encapsulation semiconductor devices, flip-chip semiconductor device, insertion
Bare die in substrate, the stacking etc. being made of semiconductor bare chip.In addition, semiconductor element may include be configured to be bonded or
The element that person is included in other ways in semiconductor packages is (for example, be bonded to the spacer in stacked die configuration, lining
Bottom etc.).
Certain exemplary embodiments according to the present invention are provided for assembling such as stacked package (that is, PoP) structure
Semiconductor devices innovative technology (and structure).For example, multiple semiconductor elements (can be encapsulation) can be in stacking configuration
Arrangement.Each element in these elements preferably include by ultrasonic bond together aluminium (aluminium alloy or part be aluminium
(partially aluminum)) conductive structure.This technology have the advantages that it is certain, including for example：With other interconnection technique (examples
Such as, the PoP technologies based on solder) it compares, density reduces；With other interconnection techniques on the contrary, flowing back without using solder bump；And
It makes it possible to carry out room temperature ultrasonic bond by using aluminium-aluminium interconnection in certain applications.
Figure 1A shows the part of ultrasonic bonding machine 100, which includes bonding tool 124 and support
Structure 150.Arrive as will be understood by those skilled, thermocompression bonding machine (such as machine 100 or it is described herein it is any its
The embodiment of its machine) it may include for simplicity and many elements not shown in figures.Illustratively element includes
Such as：Input element is used to provide and wait for and other semiconductor device bonded input workpiece；Output element is used to receive
Include the processed workpiece of other semiconductor elements at this time；Conveyer system for travelling workpiece；For being imaged to workpiece
With the imaging system of alignment；Carry the bondhead assembly of bonding tool；Kinematic system for moving bondhead assembly；Including with
In the computer system of the software of operation machine；And other elements.
Referring again to Figure 1A, upper semiconductor element 108 is by the holding part 110 of bonding tool 124 (for example, by true
Sky, the vacuum ports such as limited by the holding surface by holding part 110) it keeps.Upper semiconductor element 108 includes
Top conductive structure 112a and 112b on its lower surface.Lower semiconductor element 160 includes being bonded to substrate 104
The semiconductor bare chip 102 of (or being supported in other ways by substrate 104).Conductive structure 106a and 106b are arranged on for lower part
On the upper surface of lower semiconductor bare die 102.Substrate 104 is again by support construction 150 (for example, the heat block of machine 100, machine
100 anvil block or any other desired support construction) support.In the configuration shown in Figure 1A (being ready for being bonded), on
Each of portion conductive structure 112a and 112b are substantially aligned with opposite respective lower conductive structure 106a and 106b.Pass through key
The movement of conjunction tool 124 makes semiconductor element 108 move down (as shown in the arrow 126 in Figure 1A).After this movement, scheme
1B shows corresponding conductive structure 106a contacts between 112a and 106b and 112b.Using ultrasonic transducer (be not shown,
But it is represented as " USG ", i.e. ultrasonic generator in the accompanying drawings) ultrasonic energy 114 is applied to by top by bonding tool 124
Semiconductor element 108 and top conductive structure 112a and 112b.For example, the ultrasonic transducer of carrying bonding tool 124 may be used again
To be carried by the bondhead assembly of machine 100.
During ultrasonic bond, lower part conductive structure 106a and 106b can be by being supplied to lower part half by support construction 150
The support of conductor element 160 is (for example, the support surface of support construction 150 may include one or more vacuum ports, to be bonded
Substrate 104 is fastened to support construction 150 by period) keep opposing stationary.Ultrasonic energy 114 (with optional bonding force and/or
Heat is together) conductive structure local deformation can be made.For example, in fig. 1 c, conductive structure 106a and 106b and 112a and
112b is shown as partly deforming.In fig. 1 c, ultrasonic bond portion is formed between the conductive structure of corresponding pairs.Example
Such as, ultrasonic bond portion 128a is formed between conductive structure 112a'/106a' of deformation, and ultrasonic bond portion 128b quilts
It is formed between conductive structure 112b'/106b' of deformation.Conductive structure 106a and 106b and 112a and 112b can be by aluminium
Or aluminium alloy formed or can include at their bonding surface aluminium, etc..
The conducting element 106a and 112a and 106b of corresponding pairs and 112b can be at room temperature (during bonding technologies
Without adding heat) it is bonded together.It is alternatively possible to apply additional heat, such as：(1) during bonding technology, lead to
Cross bonding tool 124 and apply additional heat to upper semiconductor element 108, thus heat upper conductive element 112a and
112b；And/or (2) give lower semiconductor element during bonding technology by support construction 150 (for example, heat block 150)
160 apply additional heat, thus heat lower part conductive structure 106a and 106b.This optional heating is (for example, pass through key
Conjunction tool and/or support construction etc.) it is suitable for any embodiment of the present invention illustrated and described herein.
Semiconductor element 160 shown in Figure 1A to Fig. 1 C and 108 can be configured for being bonded together multiple partly lead
Any one of volume elements part.In an especially specific example, (it is also suitable for other realities illustrated and described herein
Apply example) in, semiconductor element 160 is processor (for example, at the mobile phone of also referred to as APU (application processor unit)
Manage device), and semiconductor element 108 is configured for being bonded to the memory device of processor as shown in Figure 1A to Fig. 1 C.
Conductive structure shown in Figure 1A to Fig. 1 C (that is, 112a, 112b, 106a, 106b) is shown as universal architecture.These
Structure can take a number of different forms, such as conductive column, column-shaped projection (for example, being formed using column-shaped projection machine), plating
Conductive structure, sputtering conductive structure, lead portion, bonding welding pad, contact pad and other forms.It is provided herein it is various its
Its attached drawing shows the specific example of these structures.Some embodiments according to the present invention, conductive structure is at the position will
The contact area (that is, bonding surface) for being bonded to other conductive structures includes aluminium.In these embodiments, conductive structure can be with
It is formed by aluminum or aluminum alloy (for example, aluminium is melt into alloy, aluminium and silicon with copper and copper is melt into alloy etc.).In other examples, conductive
Structure may include base conductor material (for example, copper) in addition to aluminum and the aluminium (or aluminium alloy) positioned at contact area.At this
In application, if conductive structure is referred to as " aluminium ", it will be appreciated that, which can be aluminium, can be aluminium alloy, or can be with
Include aluminium (or aluminium alloy) in the contact area of this conductive structure.
Fig. 2A shows the part of ultrasonic bonding machine 200, which includes bonding tool 224 and support
Structure 250.Upper semiconductor element 208 is kept by the holding part 210 (for example, passing through vacuum) of bonding tool 224, and
Including top the conductive structure 222a and 222b (that is, conductive aluminum pad 222a and 222b) being arranged at its lower surface.Lower part half
Conductor element 260 includes the semiconductor bare chip 202 for being bonded to substrate 204 (or being supported in other ways by substrate 204).Under
Conductive structure 206a and 206b are arranged on the upper surface of lower semiconductor bare die 202 in portion.Substrate 204 is again by support construction
250 supports.In the configuration shown in Fig. 2A, under each of top conductive structure 222a and 222b are substantially corresponding to opposite
Portion conductive structure 206a and 206b alignment (and be configured to ultrasonic bond to opposite respective lower conductive structure 206a and
206b).Lower part conductive structure 206a includes copper (Cu) column 230 on the upper surface being arranged on lower semiconductor bare die 202
And the top aluminium contact structures 216 on the upper surface of Cu columns 230.Top aluminium contact structures 216 can be for example plated
Or it is splashed on the upper surface of lower part copper post 230.Fig. 2 B are the enlarged drawing of the part Fig. 2A " B ", and show lower part conduction
Structure 206a's is in the top contacted with upper conductive element 222a.
Ultrasonic energy is applied to by upper semiconductor element by bonding tool 224 using ultrasonic transducer (not shown)
208.As shown in Figure 2 C, ultrasonic energy can make conductive structure local deformation.That is, ultrasonic bond portion 228 is formed on deformation
Between top conductive structure 222a' and the contact structures 216' of deformation (as shown in Figure 2 C).
It arrives as will be understood by those skilled, Cu columns 230 (including the aluminium contact structures/part for being electroplated or sputtering
216) be only the conductive structure for including aluminium an example.Fig. 2A also shows another illustrative conductive structure 206b.Under
Portion conductive structure 206b be a part of aluminum steel (can be bonded using lead key closing process), aluminium column etc. constructed of aluminium (or
Aluminium alloy structure).
Fig. 3 shows the part of ultrasonic bonding machine 300, which includes bonding tool 324 and support
Structure 350.Upper semiconductor element 308 is kept by the holding part 310 (for example, passing through vacuum) of bonding tool 324, and
Including top conductive structure 322a and 322b (that is, conductive aluminum pad 322a and 322b).Fig. 3 shows encapsulation semiconductor devices
360 (that is, lower semiconductor elements 360) arrive the bonding of upper semiconductor element 308.Lower semiconductor element 360 includes bonding
To the semiconductor bare chip 302 of substrate 304 (or being supported in other ways by substrate 304).Lower part conductive structure 306a and 306b
It is arranged on the upper surface of substrate 304.Substrate 304 is supported by support construction 350 again.Feed-through collar 320a and 320b are bonded
(although not shown in FIG. 3, bare die 302 can be bonded to flip-chip between semiconductor bare chip 302 and substrate 304
Substrate 304, this is different from or with feed-through collar interconnection to its supplement).In bare die 302 and feed-through collar 320a and 320b
Upper application coating/encapsulation 334 (for example, epoxy molding material).As shown, the top of lower part conductive structure 306a and 306b
Part is exposed to 334 top of coating/encapsulation, to allow to be electrically connected to upper semiconductor element 308.
In configuration shown in Fig. 3, each of top conductive structure 322a and 322b substantially with opposite respective lower
Conductive structure 306a and 306b alignment (and be configured to ultrasonic bond to opposite respective lower conductive structure 306a and
306b).As shown in figure 3, each of lower part conductive structure 306a and 306b include the phase on the upper surface of substrate 304
Answer Cu column 330a and 330b and respective upper aluminium contact structures 316a on the upper surface of Cu columns 330a and 330b and
316b.Aluminium contact structures 316a and 316b can be plated or are splashed in the respective upper surfaces of Cu columns 330a and 330b on top.
As shown, so that semiconductor element 308 is moved down by the movement (as shown by the arrow in Figure 3) of bonding tool 324,
So that Fig. 3 shows conductive structure 306a contacts between 322a and 306b and 322b.Use ultrasonic transducer (example
Such as, pass through bonding tool 324) ultrasonic energy is applied to upper semiconductor member (together with optional heat and/or bonding force)
Part 308, to form ultrasonic bond between aluminium conductive structure 322a and 322b and corresponding aluminium contact structures 316a and 316b
Portion.
Fig. 4 A show the part of ultrasonic bonding machine 400, which includes bonding tool 424 and support
Structure 450.Upper semiconductor element 408 is kept by the holding part 410 (for example, passing through vacuum) of bonding tool 424, and
Including top conductive structure 412a and 412b (that is, such as sputtered aluminum protrusion, aluminium column-shaped projection) on its lower surface.
Lower semiconductor element 460 includes being bonded to support construction 404 (for example, FR4 support constructions) (or in other ways by propping up
Support structure 404 support) semiconductor bare chip 402.Lower part conductive structure 406a and 406b are (that is, such as sputtered aluminum protrusion, aluminium cylindricality
Protrusion etc.) it is arranged on the upper surface of lower semiconductor bare die 402.Substrate 404 is supported by support construction 450 again.In Fig. 4 A
Shown in configuration, each of top conductive structure 412a and 412b substantially with opposite respective lower conductive structure 406a
And 406b alignments (and being configured to ultrasonic bond to opposite respective lower conductive structure 406a and 406b).Fig. 4 B are shown
The details of structure 412a and 406a (before ultrasonic bond).Referring again to Fig. 4 A, pass through the movement of bonding tool 424
(as shown in the arrow in Fig. 4 A) makes semiconductor element 408 move down so that contact be illustrated in conductive structure 406a with
Between 412a and 406b and 412b.Using ultrasonic transducer (for example, passing through bonding tool 424) by ultrasonic energy 414 (with
Optional heat and/or bonding force are together) be applied to upper semiconductor element 408, with the top aluminium conductive structure of deformation with
Ultrasonic bond portion 428a and 428b are formed between the respective lower aluminium contact structures of deformation (see, e.g. quilt as shown in Figure 4 C
The completion ultrasonic bond portion 428a' being formed between the structure 412a' of deformation and the structure 406a' of deformation).
Fig. 5 A show the part of ultrasonic bonding machine 500, which includes bonding tool 524 and support
Structure 550.Upper semiconductor element 508 is kept by the holding part 510 (for example, passing through vacuum) of bonding tool 524, and
Including top conductive structure 522a and 522b (that is, conductive aluminum pad 522a and 522b).Lower semiconductor element 560 includes by key
It is bonded to the semiconductor bare chip 502 of substrate 504 (for example, FR4 support constructions) (or being supported in other ways by substrate 504).Under
Portion conductive structure 506a and 506b (that is, such as sputtered aluminum protrusion, aluminium column-shaped projection) are arranged on lower semiconductor bare die 502
Upper surface on.Substrate 504 is supported by support construction 550 again.In the configuration shown in Fig. 5 A, top conductive structure 522a and
Each of 522b, which is substantially aligned with opposite respective lower conductive structure 506a and 506b, (and is configured to ultrasonic bond extremely
Opposite respective lower conductive structure 506a and 506b).Fig. 5 B show structure 522a's and 506a (before ultrasonic bond)
Details.As shown, made (as shown in the arrow in Fig. 5 A) by the movement of bonding tool 524 semiconductor element 508 to
Lower movement so that Fig. 5 A show the contact between conductive structure 506a and 522a.Using ultrasonic transducer (for example, passing through
Bonding tool 524) ultrasonic energy is applied to upper semiconductor element 508 (together with optional heat and/or bonding force), with
Ultrasonic bond portion 528a and 528b are formed between the top aluminium conductive structure of deformation and the respective lower aluminium contact structures of deformation
(see, e.g. the completion ultrasound between the structure 522a' for being formed on deformation and the structure 506a' of deformation as shown in Figure 5 C
Bonding part 528a').
Fig. 6 A show the part of ultrasonic bonding machine 600, which includes bonding tool 624 and support
Structure 650.In figure 6, introduction according to the present invention, multiple semiconductor elements are bonded together in stacking configuration.Specifically
For, semiconductor element 660a includes being bonded to partly leading for substrate 604a (or being supported in other ways by substrate 604a)
Body bare die 602a, wherein conductive structure 606a and 606b (that is, such as sputtered aluminum protrusion, aluminium column-shaped projection) are arranged on and partly lead
On the upper surface of body bare die 602a.Semiconductor element 660a is supported by support construction 650.
Another semiconductor element 660b (including be bonded to substrate 604b or supported in other ways by substrate 604b
Corresponding semiconductor bare die 602b, and include be located at substrate 604b on conductive structure 612a and 612b) in advance by key
It is bonded to semiconductor element 660a.Specifically, bonding tool 624 is in advance by element 660b bondings (for example, ultrasonic bond) to member
Part 660a so that ultrasonic bond portion is formed between the aluminium conductive structure 612a and 606a and 612b and 606b of corresponding pairs
628a and 628b.Element 660b further includes conductive structure 606a' and 606b', they are in steps described below by key
It is bonded to the conductive structure of element 660c.Fig. 6 B show the ultrasonic bond portion of conductive structure 612a and 606a including deformation
The detailed view of 628a.
Similarly, another semiconductor element 660c (including is bonded to substrate 604c or in other ways by substrate
The corresponding semiconductor bare die 602c of 604c supports, and include the conductive structure 612a' and 612b' being located on substrate 604c)
Through being bonded to semiconductor element 660b in advance.Specifically, bonding tool 624 is in advance by element 660c bondings (for example, ultrasound
Bonding) to element 660b so that the shape between the aluminium conductive structure 612a' and 606a' and 612b' and 606b' of corresponding pairs
At ultrasonic bond portion 628a' and 628b'.Element 660c further includes conductive structure 606a " and 606b ", they are retouched below
The conductive structure of element 660d is bonded in the step of stating.
As shown in Figure 6A, upper semiconductor element 660d by the holding part 610 of bonding tool 624 (for example, by true
It is empty) it keeps, and include the semiconductor bare chip for being bonded to substrate 604d (or being supported in other ways by substrate 604d)
602d.Conductive structure 612a " and 612b " (that is, such as sputtered aluminum protrusion, aluminium column-shaped projection) are arranged under substrate 604d
On surface.Conductive structure 612a " and 612b " conductive structure 606a " and 606b " substantially corresponding with opposite are aligned (and by structure
Cause ultrasonic bond to opposite corresponding conductive structure 606a " and 606b ").By the movement of bonding tool 624 (in such as Fig. 6 A
Arrow shown in) so that semiconductor element 660d is moved down.After this is moved downward, in the conductive structure of corresponding pairs
It is in contact between 612a " and 606a " and 612b " and 606b " (see, e.g. between the structure 612a " and 606a " of Fig. 6 C
The detailed view of contact before being deformed by ultrasonic bond).It will by bonding tool 624 using ultrasonic transducer (not shown)
Ultrasonic energy is applied to upper semiconductor element 604d, in the conductive structure 612a " and 606a " and 612b " of corresponding pairs
With formation ultrasonic bond portion between 606b ".
Although having been illustrated with specific Exemplary upper aluminium conductive structure and lower part aluminium conductive structure, this field skill
Art personnel will be appreciated that, allow have variously-shaped and design top aluminium conductive structure and lower part aluminium to lead in the teachings of the present invention
Electric structure.
Fig. 7 is the stream for showing the method by bonding semiconductor together of property embodiment according to an example of the present invention
Cheng Tu.It arrives as understood by those skilled in the art, it is convenient to omit be included in certain steps of flow chart；It can increase
Additional step；And the sequence of step can change relative to shown sequence.In step 700, the first semiconductor element
(e.g., including the semiconductor bare chip being located on substrate) it is supported in the support construction of bonder.First semiconductor element (example
Such as, the upper surface of semiconductor structure) include multiple first conductive structures for being made of at least partly aluminium (see, e.g. Figure 1A
In element 160 structure 106a and 106b；The structure 206a and 206b of element 260 in Fig. 2A；Element 360 in Fig. 3
Structure 306a and 306b；The structure 406a and 406b of element 460 in Fig. 4 A；The structure 506a of element 560 in Fig. 5 A and
506b；And the structure 606a " and 606b " of the element 660c in Fig. 6 A).In a step 702, the second semiconductor element is by being bonded
The holding part of the bonding tool of machine keep (see, e.g. in respective drawings element 108,208,308,408,508 and
660d).Second semiconductor element includes multiple second conductive structures for being made of at least partly aluminium (for example, positioned at the second half
On the lower surface of conductor element).In step 704, the first conductive structure and the second conductive structure by aligned with each other (referring to example
Such as Figure 1A and Fig. 6 A), then them is made to be in contact with each other.In optional step 706, with the bonding force of predefined size by multiple quilts
The first conductive structure and the second conductive structure of alignment force together.The bonding force of predefined size can be single bonding force value,
Or the bonding force curve (profile) that actual bond power changes wherein during being bonding operation.In optional step
In 708, by applying heat to multiple the first conductive structures and/or the second conductive structure being aligned.It is, for example, possible to use support
The support construction of first semiconductor element is by applying heat to the first conductive structure.Similarly, it can use and keep the second half
The bonding tool of conductor element is by applying heat to the second conductive structure.In step 720, multiple first conductive structures and
Two conductive structures by ultrasonic bond together, to form ultrasonic bond portion between them.
It arrives as will be understood by those skilled, since aluminum material is bonded to aluminum material by the present invention, this can be easy
Ground is completed using ultrasonic energy and/or bonding force, and is not usually required to heat, therefore when desired environment temperature/lower temperature
Bonding operation when, the present invention it is particularly useful.
The present invention has shown and described by the two pairs of conductive structures of ultrasonic bond together although having related generally to,
The present invention is certainly not limited to this.In fact, can be had according to the semiconductor packages (for example, Advanced Packaging) that the present invention assembles
Any number of conductive structure, and can have and conduction is tied by hundreds of (or even thousands of) of ultrasonic bond together
Structure.In addition, conductive structure need not be at para-linkage.For example, a structure can be bonded to two or more opposite knots
Structure.Therefore, any number of conductive structure from a semiconductor element can be by ultrasonic bond to another semiconductor
Any number of conductive structure.
Although the present invention mainly describe (and showing) ultrasonic energy by bonding tool (for example, bonding tool with it is super
Sonic transducer engagement position) application, but the invention is not restricted to this.More precisely, any desired knot can be passed through
Structure transmits ultrasonic energy, such as support construction.
It arrives as will be understood by those skilled, according to concrete application, the details of ultrasonic bond can be widely varied.Although
In this way, some unrestricted exemplary details will now be described.For example, can be in conjunction with conductive structure (for example, rod structure etc.)
It designs to be designed to the frequency of ultrasonic transducer so that energy converter resonant frequency is substantially humorous with given semiconductor element
Vibration frequency is consistent, and in this case, conductive structure can dynamically work as cantilever beam.It is illustrative at another
In alternative solution, energy converter can be run relative to semiconductor element at non-resonant condition in a manner of simple " driven " type.
It is applied to showing for the energy of ultrasonic transducer (for example, being applied to piezo-electric crystal/ceramics in transducer driver)
Example property range can be in the ranges such as 0.1kHz to 160kHz, 10kHz to 120kHz, 20kHz to 60kHz.During bonding,
Single frequency can be applied, can either apply multiple frequencies (for example, in order, simultaneously or sequentially and simultaneously).It is right
The scouring (scrub) (that is, being applied to the vibrational energy of the semiconductor element kept by bonding tool) of semiconductor element can be with
It is applied on any direction in multiple desired orientations, and can be by keeping the bonding tool of semiconductor element (such as this
Shown in text), the support construction by supporting semiconductor element and other configurations apply.With specific reference to this paper institutes
The embodiment (wherein ultrasonic energy is by keeping the bonding tool of semiconductor element to apply) shown, scouring can be roughly parallel to
Either be approximately perpendicular on the direction of the longitudinal axis of bonding tool (or in other directions) apply.
The vibrational energy applied by ultrasonic transducer for example can apply (example with the peak-to-peak amplitude range of 0.1um to 10um
Such as, the alternating control of feedback control or including but not limited to slope current, ramp voltage to constant voltage, constant current is utilized
Scheme processed or the proportional feedback control inputted based on one or more).
As described herein, bonding force can also be applied during at least part in ultrasonic bond period.Bonding force
Exemplary range be 0.1kg to 100kg.Bonding force can be used as steady state value to apply, or can be during being bonded the period
The bonding force curve of change.In controlled bonding force embodiment, based on one or more input (for example, ultrasonic amplitude, when
Between, speed, deformation, temperature etc.), the feedback control of para-linkage power can be constant, slope or proportional.
It as described herein, can be before being bonded the period and/or during being bonded the period to one in semiconductor element
It is a or multiple heated.The exemplary temperature range of semiconductor element is between 20 DEG C to 250 DEG C.Heat is (for example, pass through key
One or all in conjunction tool and support construction or the application of other elements) steady state value can be used as to apply, or can be
The temperature curve changed during being bonded the period, and can be controlled using feedback control.
Ultrasonic bond portion is formed between the aluminium conductive structure on corresponding semiconductor element although having related generally to
The present invention has shown and described, but the present invention is certainly not limited to this.That is, the teachings of the present invention can be adapted for difference
Ultrasonic bond portion is formed between the conductive structure of ingredient.The exemplary lists of material for connected conductive structure include：
Aluminium is with copper (that is, in the aluminium conductive structure on a semiconductor element and the copper conduction knot on another semiconductor element
Ultrasonic bond portion is formed between structure)；Lead-free solder (for example, being mainly made of tin) and copper；Lead-free solder and aluminium；Copper and copper；Aluminium
With silver；Copper and silver；Aluminium and gold；Jin Yujin；And copper with gold.Of course, it is possible to imagine the other of conductive structure ingredient (for example, indium)
Combination.
As provided above, although having been combined the aluminum material in the various conductive structures for being included in semiconductor element
The aspect of the present invention is described, but the invention is not restricted to this.That is, the conductive structure on semiconductor element may include each
The different material (or being formed by a variety of different materials) of kind.For example, positioned at upper semiconductor element (for example, using bonding work
Tool carrying and bonding element) on conductive structure and/or positioned at lower semiconductor element (for example, upper conductive element is by key
The element being bonded to) on conductive structure can be formed by copper (or including copper).
According to some aspects invention, ultrasonic scouring/energy can in conjunction with multi-step bonding technology use.For example, ultrasonic
Scouring/energy may be used as the beginning (initiator) of flip-chip and/or thermocompression bonding technique.It is, for example, possible to use super
Sound is cleaned to remove and formed the relevant oxide of initial bonding part, is thus that final Joining Technology (connects work for example, spreading
Skill) it prepares.This multi-step bonding technology can have many different configurations.For example, using ultrasonic scouring/energy, key
Conjunction tool can be led in the first conductive structure on the first semiconductor element with second on the second semiconductor element
Initial bonding part (for example, " positioning (tack) " bonding part) is formed between electric structure.Can use same bonding tool (for example,
Pass through and apply heat and/or power) bonding part is completed, wherein Fig. 8 A to Fig. 8 D show an example of this technique.Another
In one example, it can be completed later using different process (for example, on same bonder, first-class in different bonders)
Bonding.Using this follow-up (difference) technique, multiple element can be completed at the same time by " group (gang) " type bonding technology
Bonding part, the wherein addition of Fig. 8 E together illustrate an example of this technique with Fig. 8 A to Fig. 8 C.
Therefore, some embodiments according to the present invention, then by semiconductor element (for example, semiconductor bare chip) upside-down mounting core
Piece and/or thermocompression bonding to another semiconductor element (for example, to substrate, to another bare die, to wafer etc.) before, utilize
Ultrasound is cleaned starts stable and firm welding (as needed, together with power).Ultrasonic motion erasing waits for the oxygen in connection surface
Compound.Ultrasound is cleaned and/or power is intended to interconnection (that is, the conductive structure of the first semiconductor element and the second semiconductor element
Conductive structure) be positioned together, this contributes to the oxidation for preventing the bonding surface of conductive structure.Conductive structure to be connected
Example includes：Sn and Cu, Cu and Al, Al and Al and Cu and Cu.Of course, it is possible to imagine other combinations of conductive structure material.
After positioning, semiconductor element (for example, bare die) can individually or be in a cluster bonded.
Fig. 8 A to Fig. 8 E (with together with the flow chart of Fig. 9), Figure 10 A to Figure 10 E (together with the flow chart of Figure 11), Figure 12 A
It is shown (together with the flow chart of Figure 15) to Figure 12 D (with together with the flow chart of Figure 13) and Figure 14 A to 14D and utilizes example
The multi-step bonding technology of property forms the system and method for interconnection between semiconductor element.Fig. 9, Figure 11, Figure 13 and figure
15 be the flow chart by semiconductor device bonded method together for showing exemplary embodiment according to the present invention.Such as this
Field technology personnel are understood, it is convenient to omit the certain steps being included in flow chart；Certain extra steps can be increased
Suddenly；And the sequence of step can change relative to shown sequence.
With specific reference to Fig. 8 A, upper semiconductor element 808 is by the holding part 810 of bonding tool 824 (for example, by true
Sky, the vacuum ports such as limited by the holding surface by holding part 810) it keeps.Upper semiconductor element 808 includes
Top conductive structure 812a and 812b on its lower surface is (for example, the copper conductive structure of such as copper post or other conductions
Structure).Lower semiconductor element 860 includes being bonded to partly leading for substrate 804 (or being supported in other ways by substrate 804)
Body bare die 802.For example, substrate 804 can be RF magnetron sputtering, semiconductor crystal wafer, temporary support structure (for example, silicon, metal or glass
Glass wafer or panel) and other substrates.In another example, no matter how attached drawing shows individual substrate 804, semiconductor
Bare die 802 still can be a part for semiconductor crystal wafer.Lower part conductive structure 806a and 806b are (for example, the copper of such as copper post is led
Electric structure or other conductive structures) it is arranged on the upper surface of lower semiconductor bare die 802.Substrate 804 is tied by support again
Structure 850 (for example, the anvil block of the heat block of machine 800, machine 800 or any other desired support construction) supports.Optionally,
Semiconductor bare chip 802 still can be a part for the wafer all or in part directly supported by support construction 850, without any
Additional substrate between two parties (intervening substrate) 804.In configuration (being ready for being bonded) as shown in Figure 8 A,
Each of top conductive structure 812a and 812b are substantially aligned with opposite respective lower conductive structure 806a and 806b.Pass through
The movement of bonding tool 824 makes semiconductor element 808 move down (as shown in the arrow 826 in Fig. 8 A).The movement it
Afterwards, Fig. 8 B show corresponding conductive structure 806a contacts between 812a and 806b and 812b.(not using ultrasonic transducer
Show, but be represented as " USG ", i.e. ultrasonic generator in the accompanying drawings) ultrasonic energy 814 is applied to by bonding tool 824
Upper semiconductor element 808 and top conductive structure 812a and 812b.For example, the ultrasonic transducer of carrying bonding tool 824
It can be carried again by the bondhead assembly of reverse chip key binder 800.During ultrasonic bond, lower part conductive structure 806a and
806b can be by being supplied to the support of lower semiconductor element 860 (for example, the support table of support construction 850 by support construction 850
Face may include one or more vacuum ports, substrate 804 is fastened to support construction 850 during bonding) keep opposite
It is static.Ultrasonic energy 814 can make conductive structure local deformation (together with optional bonding force and/or heat).For example, scheming
In 8C, conductive structure 806a and 806b and 812a and 812b are shown as deformation (or deforming at least partly).In Fig. 8 C
In, initial (positioning) ultrasonic bond portion is formed between the conductive structure of corresponding pairs.For example, as shown in Figure 8 C, initial (example
Such as, positioning) ultrasonic bond portion 828a is formed between conductive structure 812a'/806a' of deformation, and it is initial (for example, fixed
Position) ultrasonic bond portion 828b is formed between conductive structure 812b'/806b' of deformation.
In certain embodiments of the present invention, multi-step bonding technology can be completed as in fig. 8d.That is, in Fig. 8 C
Initial (positioning) bonding part has been formed, and can have been used from bonding tool 824 or different bonding tools in Fig. 8 D
The heat of 824a (for example, on identical or different machine) and/or power form final bonding part.
In other embodiments of the invention, different bonding tools can be used (for example, in identical or different machine
On) come (for example, being bonded multiple semiconductor elements simultaneously) forms final bonding part based on group or " group " as illustrated in fig. 8e.
In such an embodiment, after Fig. 8 C, the conductive structure of semiconductor element 808 and 860, which is " positioned ", to be bonded together.With
Afterwards, in Fig. 8 E, one group of upper semiconductor element 808 is bonded (for example, utilizing heat and/or power) to corresponding one group by " group "
Lower semiconductor element 860.In example as illustrated in fig. 8e, group's bonding tool 875 is provided, it can be in the machine of Fig. 8 A
The tool 875 is used on device 800 or different flip-chip and/or hot press.If on uniform machinery, support construction
850 (such as Fig. 8 A) can be used for supporting multiple lower semiconductor elements 860 during " group " bonding technology.If in different machines
On device, support construction 879 can be used for supporting multiple lower semiconductor elements 860 during " group " bonding technology." group " is bonded
Tool 875 (including holding part 877) completes the conductive structures of multiple upper semiconductor elements 808 to corresponding lower semiconductor
The bonding of the conductive structure (wherein, as described in above in conjunction with Fig. 8 A, each element 860 includes bare die 802) of element 860.At this
During final bonding technology, heat and/or power can be by bonding tool 875, by support construction 850/879 or pass through key
Conjunction tool 875 and support construction 850/879 provide.
With specific reference to Fig. 9, in step 900, the first semiconductor element (e.g., including the semiconductor being located on substrate is naked
Piece, element 860 shown in such as Fig. 8 A) it is supported in the support construction of bonder.First semiconductor element is (for example, partly lead
The upper surface of body structure) include multiple first conductive structures.In step 902, the second semiconductor element is (see, e.g. Fig. 8 A
In element 808) by bonder bonding tool holding part keep.Second semiconductor element includes the multiple second conductive knots
Structure (for example, on lower surface of the second semiconductor element).In step 904, the first conductive structure and the second conductive structure
By (see, e.g. Fig. 8 A) aligned with each other, and them is then made to be in contact with each other (see, e.g. Fig. 8 B).In step 906, surpass
Acoustic energy is applied to the second semiconductor element (such as in the fig. 8b, by the bonding tool of the second semiconductor element of carrying),
So that the conductive structure of the second semiconductor element is by " initial " bonding (for example, positioning bonding) as shown in Figure 8 C to the first half
The conductive structure of conductor element (referring to positioning bonding part 828a and 828b).
Step 908A, step 908B and step 908C is substantially considered as can be substituted for each other herein.In step 908A, make
Same bonding tool used in step 906 completes first (by bonding semiconductor element one at a time) one by one
Flip-chip (for example, hot pressing) bonding technology of conductive structure to the second conductive structure.For example, the example with reference to shown in figure 8D,
Bonding tool 824 can be used to apply heat and/or pressure, include further deforming to form complete bonding part 828a'(
Conductive structure 806a " and 812a ") and 828b'(include the conductive structure 806b " and 812b " further deformed).
As the alternative solution of step 908A, in step 908B, using with the bonding tool used in step 906 not
With tool (for example, different bonding tools on different bonding tools, different machines on uniform machinery) come one by one (by every
Next ground bonding semiconductor element) complete flip-chip (for example, hot pressing) key of the first conductive structure to the second conductive structure
Close technique.For example, referring again to example shown in Fig. 8 D (wherein, element 860 is supported by support construction 850a), bonding can be used
Tool 824a (including holding part 810a) applies heat and/or pressure, to form complete bonding part 828a'(includes into one
Walk deformation conductive structure 806a " and 812a ") and 828b'(include the conductive structure 806b " and 812b " further deformed).
As the alternative solution of step 908A, step 908B, in step 908C, using with used in step 906
The different tool of bonding tool (for example, different bonding tools on different bonding tools, different machines on uniform machinery) comes
The upside-down mounting of the first conductive structure to the second conductive structure is completed (by being bonded multiple semiconductor elements simultaneously) based on group
Chip (for example, hot pressing) bonding technology.For example, the example with reference to shown in figure 8E at this time, bonding tool 875 can be used (including to protect
Part 877 is held, multiple semiconductor elements 808 are bonded to corresponding semiconductor element 860) (wherein, if in same bonder
On 800, element 860 can be supported by support construction 850；Or if on different bonders, element 860 can be supported
In support construction 879) apply heat and/or pressure, with formed include the conductive structure that further deforms to 806a'a with
The complete bonding part of 812a'a and 806b'b and 812b'b.
Therefore, it by the option (and being shown in Fig. 8 A to Fig. 8 E) described in Fig. 9, describes for positioning and welding
(weld) various types of system and methods of (or positioning and group) bonding.Certainly, formed initial (positioning) bonding part and with
The further modification for forming complete (final) bonding part afterwards is deemed within the scope of the present invention.In conjunction with Fig. 8 A to Fig. 8 E and Fig. 9
Certain modifications of the system and technique (and the other systems and technique being located within the scope of the present invention) that show and describe are related to
The non-conducting material between the semiconductor element being bonded together is arranged on (for example, paste, epoxy resin, acrylate, silicon
Ketone, bismaleimide, polyimides, polyester etc. or non-conductive film) use.This non-conducting material can contain all
Such as silica or the inorganic filler material of the powder of aluminium oxide.Figure 10 A to Figure 10 E (and flow chart in Figure 11), Figure 12 A
This germline is shown to Figure 12 D (and flow chart in Figure 13) and Figure 14 A to Figure 14 D (and flow chart in Figure 15)
The example of system and technique.
With specific reference to Figure 10 A, upper semiconductor element 1008 is by the holding part 1010 of bonding tool 1024 (for example, logical
Cross vacuum, the vacuum ports such as limited by the holding surface by holding part 1010) it keeps.Upper semiconductor element 1008
Including top conductive structure 1012a and 1012b on its lower surface (for example, the copper conductive structure of such as copper post or its
Its conductive structure).Lower semiconductor element 1060 includes being bonded to substrate 1004 (or in other ways by substrate 1004
Support) semiconductor bare chip 1002.For example, substrate 1004 can be RF magnetron sputtering, semiconductor crystal wafer, temporary support structure (for example,
Silicon, metal or glass wafer or panel) and other substrates.In another example, no matter how attached drawing shows individually to serve as a contrast
Bottom 1004, semiconductor bare chip 1002 still can be a parts for semiconductor crystal wafer.Lower part conductive structure 1006a and 1006b (example
Such as, the copper conductive structure or other conductive structures of such as copper post) it is arranged on the upper surface of lower semiconductor bare die 1002.
Substrate 1004 is again by support construction 1050 (for example, the anvil block of the heat block of machine 1000, machine 1000 or any other desired
Support construction) support.Optionally, semiconductor bare chip 1002 can be directly supported all or in part by support construction 1050
A part for wafer, without any additional substrate 1004 between two parties.In configuration (being ready for being bonded) as shown in Figure 10 A
In, each of top conductive structure 1012a and 1012b substantially with opposite respective lower conductive structure 1006a and 1006b
Alignment.Semiconductor element 1008 is set to move down (as shown in the arrow 1026 in Figure 10 A) by the movement of bonding tool 1024.
After this movement, Figure 10 B show corresponding conductive structure 1006a contacts between 1012a and 1006b and 1012b.
It will by bonding tool 1024 using ultrasonic transducer (be not shown, but be represented as " USG ", i.e. ultrasonic generator in the accompanying drawings)
Ultrasonic energy 1014 is applied to upper semiconductor element 1008 and top conductive structure 1012a and 1012b.For example, carrying key
The ultrasonic transducer of conjunction tool 1024 can be carried again by the bondhead assembly of reverse chip key binder 1000.In the ultrasonic bond phase
Between, lower part conductive structure 1006a and 1006b can be by being supplied to the support of lower semiconductor element 1060 by support construction 1050
(for example, the support surface of support construction 1050 may include one or more vacuum ports, with during bonding by substrate 1004
It is fastened to support construction 1050) keep opposing stationary.Ultrasonic energy 1014 can (together with optional bonding force and/or heat)
So that conductive structure local deformation.For example, in fig 1 oc, conductive structure 1006a' and 1006b' and 1012a' and 1012b'
It is shown as deformation (or deforming at least partly) (compared with Figure 10 A to Figure 10 B).In fig 1 oc, initial (positioning) is super
Sound bonding part 1028a and 1028b are formed between the conductive structure of corresponding pairs.For example, as illustrated in figure 10 c, initial (example
Such as, positioning) ultrasonic bond portion 1028a is formed between conductive structure 1012a'/1006a' of deformation, and initial (for example,
Positioning) ultrasonic bond portion 1028b is formed between conductive structure 1012b'/1006b' of deformation.
After forming initial (positioning) ultrasonic bond portion as illustrated in figure 10 c, as shown in Figure 10 D, non-conducting material 1040
(for example, non-conductive paste, epoxy material, acrylate, silicone, bismaleimide, polyimides, polyester etc., wherein this
Non-conducting material may include the inorganic particulate etc. of silica or aluminium oxide particles) it is applied in semiconductor element 1008
Between semiconductor element 1002.Depending on selected materials and other details of application scenario, material 1040 can be by appointing
What desired mode (for example, as fluid distribution, capillary underfill technology being used to distribute etc.) applies.In Figure 10 E,
(for example, utilizing heat, pressure etc.) completes the bonding of the first conductive structure to the second conductive structure, to form complete bonding
Portion 1028a'(includes the conductive structure 1006a " and 1012a " further deformed) and 1028b'(include the conduction further deformed
Structure 1006b " and 1012b ").In Figure 10 E, the non-conducting material being applied in figure 10d has been cured, to form solidification
Non-conducting material 1040'.
With specific reference to Figure 11, in step 1100, the first semiconductor element (e.g., including the semiconductor being located on substrate
Bare die, element 1060 shown in such as Figure 10 A) it is supported in the support construction of bonder.First semiconductor element (for example,
The upper surface of semiconductor structure) include multiple first conductive structures.In step 1102, the second semiconductor element (see, e.g.
Element 1008 in Figure 10 A) it is kept by the holding part of the bonding tool of bonder.Second semiconductor element includes multiple
Two conductive structures (for example, on lower surface of the second semiconductor element).In step 1104, the first conductive structure and second
Conductive structure then makes them be in contact with each other (see, e.g. Figure 10 B) by (see, e.g. Figure 10 A) aligned with each other.In step
In rapid 1106, ultrasonic energy is applied to the second semiconductor element (such as in fig. 1 ob, by carrying the second semiconductor element
Bonding tool) so that the conductive structure of the second semiconductor element by as illustrated in figure 10 c it is " initial " bonding (for example, positioning key
Close) to the first semiconductor element conductive structure (referring to positioning bonding part 1028a and 1028b).In step 1108, non-to lead
Electric material is applied in the first semiconductor element and the second semiconductor element (see, e.g. the material 1040 applied in figure 10d)
Between part.In step 1110, (for example, by applying heat and/or power) completes the first conductive structure and the second conductive structure
Flip-chip and/or thermocompression bonding, and, in step 1112, non-conducting material has been cured (referring to Figure 10 E).Such as
It will be understood by the skilled person that, if it is desired, step 1110 and step 1112 can be executed at the same time.
With specific reference to Figure 12 A, upper semiconductor element 1208 is by the holding part 1210 of bonding tool 1224 (for example, logical
Cross vacuum, the vacuum ports such as limited by the holding surface by holding part 1210) it keeps.Upper semiconductor element 1208
Including top conductive structure 1212a and 1212b on its lower surface (for example, the copper conductive structure of such as copper post or its
Its conductive structure).Lower semiconductor element 1260 includes being bonded to substrate 1204 (or in other ways by substrate 1204
Support) semiconductor bare chip 1202.For example, substrate 1204 can be RF magnetron sputtering, semiconductor crystal wafer, temporary support structure (for example,
Silicon, metal or glass wafer or panel) and other substrates.In another example, no matter how attached drawing shows individually to serve as a contrast
Bottom 1204, semiconductor bare chip 1202 still can be a parts for semiconductor crystal wafer.Lower part conductive structure 1206a and 1206b (example
Such as, the copper conductive structure or other conductive structures of such as copper post) it is arranged on the upper surface of lower semiconductor bare die 1202.
Substrate 1204 is again by support construction 1250 (for example, the anvil block of the heat block of machine 1200, machine 1200 or any other desired
Support construction) support.Optionally, semiconductor bare chip 1202 can be directly supported all or in part by support construction 1250
A part for wafer, without any additional substrate 1204 between two parties.In configuration (being ready for being bonded) as illustrated in fig. 12
In, each of top conductive structure 1212a and 1212b substantially with opposite respective lower conductive structure 1206a and 1206b
Alignment.As illustrated in fig. 12, non-conducting material 1240 be applied in (for example, non-conductive paste, epoxy material, acrylate, silicone,
Bismaleimide, polyimides, polyester etc., wherein this non-conducting material may include such as silica or oxidation aluminum shot
The inorganic particulate etc. of son) (in this illustration, material 1240 is practical between semiconductor element 1208 and semiconductor element 1202
On be applied on semiconductor bare chip 1202).Depending on selected materials and other details of application scenario, material 1240 can
To be applied by (for example, as fluid distribution, capillary underfill technology being used to distribute etc.) in a manner of any desired.
As illustrated in fig. 12, semiconductor is made (as shown in the arrow 1226 in Figure 12 A) by the movement of bonding tool 1224
Element 1208 moves down.This movement is so that non-conducting material 1240 is distributed in semiconductor element 1208 and semiconductor element
Between 1260, including surrounds 1206a and 1212a and 1206b and 1212b and be distributed.After this movement, Figure 12 B show phase
Answer conductive structure 1206a contacts between 1212a and 1206b and 1212b.Using ultrasonic transducer (be not shown, but
" USG ", i.e. ultrasonic generator are represented as in attached drawing) it ultrasonic energy 1214 is applied to by top by bonding tool 1224 partly leads
Volume elements part 1208 and top conductive structure 1212a and 1212b.For example, the ultrasonic transducer of carrying bonding tool 1224 may be used again
To be carried by the bondhead assembly of reverse chip key binder 1200.During ultrasonic bond, lower part conductive structure 1206a and
1206b can be by being supplied to by support construction 1250 support of lower semiconductor element 1260 (for example, support construction 1250
Support surface may include one or more vacuum ports, substrate 1204 is fastened to support construction 1250 during bonding) come
Keep opposing stationary.Ultrasonic energy 1214 can make conductive structure local deformation (together with optional bonding force and/or heat).
For example, in fig. 12 c, conductive structure 1206a' and 1206b' and 1212a' and 1212b' are shown as deformation (or at least
Partly deform) (compared with Figure 12 A to Figure 12 B).In fig. 12 c, initial (positioning) ultrasonic bond portion 1228a and 1228b
It is formed between the conductive structure of corresponding pairs.For example, as indicated in fig. 12 c, initial (for example, positioning) ultrasonic bond portion
1228a is formed between conductive structure 1212a'/1206a' of deformation, and initial (for example, positioning) ultrasonic bond portion
1228b is formed between conductive structure 1212b'/1206b' of deformation.
After forming initial (positioning) ultrasonic bond portion as indicated in fig. 12 c, in fig. 12d, (for example, utilizing heat
Amount, pressure etc.) complete the first conductive structure to the second conductive structure bonding, with formed complete bonding part 1228a'(include into
One step deformation conductive structure 1206a " and 1212a ") and 1228b'(include the conductive structure 1206b " further deformed and
1212b”).In fig. 12d, the non-conducting material being applied in fig. 12 has been cured, to form cured non-conducting material
1240'。
With specific reference to Figure 13, in step 1300, the first semiconductor element (e.g., including the semiconductor being located on substrate
Bare die, element 1360 shown in such as Figure 12 A) it is supported in the support construction of bonder.First semiconductor element (for example,
The upper surface of semiconductor structure) include multiple first conductive structures.In step 1302, the second semiconductor element (see, e.g.
Element 1308 in Figure 12 A) it is kept by the holding part of the bonding tool of bonder.Second semiconductor element includes multiple
Two conductive structures (for example, on lower surface of the second semiconductor element).In step 1304, non-conducting material is (referring to example
Such as the material 1240 applied in fig. 12) it is applied between the first semiconductor element and the second semiconductor element.In step
In 1306, the first conductive structure and the second conductive structure then make them each other by (see, e.g. Figure 12 A) aligned with each other
It contacts (see, e.g. Figure 12 B).In step 1308, ultrasonic energy is applied to the second semiconductor element (such as in Figure 12 B
In, by the bonding tool for carrying the second semiconductor element) so that the conductive structure of the second semiconductor element is by such as Figure 12 C institutes
Show " initial " bonding (for example, positioning bonding) to the first semiconductor element conductive structure (referring to positioning bonding part 1228a and
1228b).In step 1310, (for example, by applying heat and/or power) completes the first conductive structure and the second conductive structure
Flip-chip and/or thermocompression bonding, and, in step 1312, non-conducting material has been cured (referring to Figure 12 D).Such as
It will be understood by the skilled person that, if it is desired, step 1310 and step 1312 can be executed at the same time.
With specific reference to Figure 14 A, upper semiconductor element 1408 is by the holding part 1410 of bonding tool 1424 (for example, logical
Cross vacuum, the vacuum ports such as limited by the holding surface by holding part 1410) it keeps.Upper semiconductor element 1408
Including top conductive structure 1412a and 1412b on its lower surface (for example, the copper conductive structure of such as copper post or its
Its conductive structure).Lower semiconductor element 1460 includes being bonded to substrate 1404 (or in other ways by substrate 1404
Support) semiconductor bare chip 1402.For example, substrate 1404 can be RF magnetron sputtering, semiconductor crystal wafer, temporary support structure (for example,
Silicon, metal or glass wafer or panel) and other substrates.In another example, no matter how attached drawing shows individually to serve as a contrast
Bottom 1404, semiconductor bare chip 1402 still can be a parts for semiconductor crystal wafer.Lower part conductive structure 1406a and 1406b (example
Such as, the copper conductive structure or other conductive structures of such as copper post) it is arranged on the upper surface of lower semiconductor bare die 1402.
Substrate 1404 is again by support construction 1450 (for example, the anvil block of the heat block of machine 1400, machine 1400 or any other desired
Support construction) support.Optionally, semiconductor bare chip 1402 can be directly supported all or in part by support construction 1450
A part for wafer, without any additional substrate 1404 between two parties.In configuration (being ready for being bonded) as shown in Figure 14 A
In, each of top conductive structure 1412a and 1412b substantially with opposite respective lower conductive structure 1406a and 1406b
Alignment.As shown in Figure 14 A, non-conductive film 1440 (for example, as applications such as solid-state non-conductive films) is applied in semiconductor element
Between 1408 and semiconductor element 1402 (in this illustration, film 1440 is actually applied on semiconductor bare chip 1402).
As shown in Figure 14 A, semiconductor is made (as shown in the arrow 1426 in Figure 14 A) by the movement of bonding tool 1424
Element 1408 moves down.This movement is so that non-conductive film 1440 is distributed in semiconductor element 1408 and semiconductor element 1460
Between, including surround 1406a and 1412a and 1406b and 1412b and be distributed.After this movement, Figure 14 B show and accordingly lead
Electric structure 1406a contacts between 1412a and 1406b and 1412b.It (is not shown, but in attached drawing using ultrasonic transducer
In be represented as " USG ", i.e. ultrasonic generator) by bonding tool 1424 by ultrasonic energy 1414 be applied to upper semiconductor member
Part 1408 and top conductive structure 1412a and 1412b.For example, the ultrasonic transducer of carrying bonding tool 1424 again can be by
The bondhead assembly of reverse chip key binder 1400 carries.During ultrasonic bond, lower part conductive structure 1406a and 1406b can
By being supplied to the support of lower semiconductor element 1460 (for example, the support surface of support construction 1450 by support construction 1450
May include one or more vacuum ports, substrate 1404 is fastened to support construction 1450 during bonding) keep opposite
It is static.Ultrasonic energy 1414 can make conductive structure local deformation (together with optional bonding force and/or heat).For example,
In Figure 14 C, conductive structure 1406a' and 1406b' and 1412a' and 1412b' are shown as deformation (or at least partly
Deformation) (compared with Figure 14 A to Figure 14 B).In Figure 14 C, initial (positioning) ultrasonic bond portion 1428a and 1428b are formed
Between the conductive structure of corresponding pairs.For example, as shown in Figure 14 C, initial (for example, positioning) ultrasonic bond portion 1428a is by shape
At between conductive structure 1412a'/1406a' of deformation, and initial (for example, positioning) ultrasonic bond portion 1428b is formed
Between conductive structure 1412b'/1406b' of deformation.
After forming initial (positioning) ultrasonic bond portion as shown in Figure 14 C, in Figure 14 D, (for example, utilizing heat
Amount, pressure etc.) complete the first conductive structure to the second conductive structure bonding, with formed complete bonding part 1428a'(include into
One step deformation conductive structure 1406a " and 1412a ") and 1428b'(include the conductive structure 1406b " further deformed and
1412b”).In Figure 14 D, the non-conducting material being applied in Figure 14 A has been cured, to form cured non-conducting material
1440'。
With specific reference in Figure 15, in step 1500, the first semiconductor element (e.g., including partly leading on substrate
Body bare die, element 1460 such as shown in figure 14 A) it is supported in the support construction of bonder.First semiconductor element (example
Such as, the upper surface of semiconductor structure) include multiple first conductive structures.In step 1502, the second semiconductor element (referring to,
Such as the element 1408 in Figure 14 A) kept by the holding part of the bonding tool of bonder.Second semiconductor element includes multiple
Second conductive structure (for example, on lower surface of the second semiconductor element).In step 1504, non-conductive film is (referring to example
The film 1440 such as applied in Figure 14 A) it is applied between the first semiconductor element and the second semiconductor element.In step 1506
In, the first conductive structure and the second conductive structure then make them be in contact with each other by (see, e.g. Figure 14 A) aligned with each other
(see, e.g. Figure 14 B).In step 1508, (such as in fig. 14b, ultrasonic energy is applied to the second semiconductor element
By the bonding tool for carrying the second semiconductor element) so that the conductive structure of the second semiconductor element is by as shown in Figure 14 C
" initial " bonding (for example, positioning bonding) to the first semiconductor element conductive structure (referring to, position bonding part 1428a and
1428b).In step 1510, (for example, by applying heat and/or power) completes the first conductive structure and the second conductive structure
Flip-chip and/or thermocompression bonding, and in step 1512, non-conductive film has been cured (referring to Figure 14 D).Such as this
Field technology personnel will be appreciated that, if it is desired, can execute step 1510 and step 1512 at the same time.
Each of Figure 10 A to Figure 10 E, Figure 12 A to Figure 12 D and Figure 14 A to Figure 14 D are shown as utilizing original key
Conjunction tool completes initial (positioning) ultrasonic bond and subsequent complete bonding steps.It should be understood, however, that these embodiments
Each of (and Figure 11, Figure 13 and respective flow chart shown in figure 15) can complete final key using different tools
Close, wherein different tools can be located on same bonder or different bonders, and different tools can one by one or
The ground bonding semiconductor element (for example, as illustrated in fig. 8e) in groups.In Fig. 8 A to Fig. 8 E, Fig. 9, Figure 10 A to Figure 10 E, Figure 11, figure
Each of 12A to Figure 12 D, Figure 13, Figure 14 A to Figure 14 D, embodiment shown in Figure 15 are especially suitable for positioning and group's work
Skill (tack and gang processes), wherein element are used as individual component localization by ultrasonic to be bonded (for example, with reference to figure first
8C, Figure 10 C, Figure 12 C, Figure 14 C), and then heat is utilized (using group's bonding tool, tool 875 shown in such as Fig. 8 E)
And/or pressure carries out group's bonding, so that conductive structure is further deformed into final complete bond styles.This positioning and group's work
Skill is perfectly suitable for chip to wafer (" C2W ") occasion, that is, ultrasonic bond tool is used alone by each semiconductor bare chip
(chip) localization by ultrasonic is bonded to wafer, then using group's bonding tool (for example, utilizing heat and/or pressure) to one group of key
The bare die of conjunction carries out group's bonding.
Multi-step bonding utilizes (i) initial ultrasound to position bonding technology, wherein partly being led to each using ultrasonic bond tool
Volume elements part (for example, bare die) carries out positioning bonding；Followed by (ii) group's bonding technology, plurality of semiconductor element passes through most
Whole bonding technology (being used together bonding tool with heat and/or pressure)；This multi-step bonding is particularly suited for upper copper
Conductive structure (being located on upper semiconductor element) is bonded to lower copper conductive structure (being located on lower semiconductor element).It is formed
The technique of final bonding part tends to be related to the growth particle (grow to across top conductive structure and the interface of lower part conductive structure
Gains it) is heat-treated.This technique tends to be related to for quite a long time.In order to provide efficient process yields (for example, UPH
Or hourly output), group's bonding is especially suitable.Therefore, relatively quick " positioning " ultrasonic bond technique can with per next half
Complete to conductor element, and relatively time-consuming " group " bonding technology (being related to heat and/or pressure) can with and meanwhile bonding it is more
The mode of a semiconductor element is completed.
Although the present invention has shown and described herein with reference to specific embodiment, the present invention is not intended to be limited to shown thin
Section.More precisely, can in the boundary and range of the equivalent of claim and without departing from the present invention
Details is carry out various modifications.
Claims (30)
1. a kind of method carrying out ultrasonic bond to semiconductor element, the described method comprises the following steps：
(a) conductive by multiple the second of the surface of multiple first conductive structures of the first semiconductor element and the second semiconductor element
The respective surfaces of structure are aligned；
(b) several first conductive structures in first conductive structure are corresponding several with second conductive structure
Positioning bonding part is ultrasonically formed between a second conductive structure；And
(c) complete bonding part is formed between first conductive structure and second conductive structure.
2. according to the method described in claim 1, it is characterized in that, first semiconductor element is semiconductor bare chip.
3. according to the method described in claim 1, it is characterized in that, first semiconductor element and second semiconductor element
Each of part is corresponding semiconductor bare chip.
4. according to the method described in claim 1, it is characterized in that, first semiconductor element includes semiconductor bare chip.
5. according to the method described in claim 1, it is characterized in that, first semiconductor element and second semiconductor element
Each of part includes corresponding semiconductor bare chip.
6. according to the method described in claim 1, it is characterized in that, further comprising the steps of：Make first semiconductor element
It is moved towards second semiconductor element so that the lower surface of first conductive structure and corresponding described second conductive knot
The upper surface of structure contacts.
7. according to the method described in claim 1, it is characterized in that, further comprising the steps of：At least the one of the step (b)
During portion, apply pressure between first semiconductor element and second semiconductor element.
8. according to the method described in claim 1, it is characterized in that, further comprising the steps of：During the step (b), make
Several first conductive structures deformation in first conductive structure.
9. according to the method described in claim 1, it is characterized in that, the step (b) carries out at ambient temperature.
10. according to the method described in claim 1, it is characterized in that, further comprising the steps of：The step (b) at least
At least one of first semiconductor element and second conducting element are heated during a part.
11. according to the method described in claim 1, it is characterized in that, further comprising the steps of：The step (b) at least
During a part, first semiconductor element is added using the bonding tool of first semiconductor element is kept
Heat.
12. according to the method described in claim 1, it is characterized in that, further comprising the steps of：The step (b) at least
During a part, support the support construction of second semiconductor element come to described second using during the step (b)
Semiconductor element is heated.
13. according to the method described in claim 1, it is characterized in that, the multiple first conductive structure and the multiple second
At least one of conductive structure conductive structure is formed by copper.
14. according to the method described in claim 1, it is characterized in that, the multiple first conductive structure and the multiple second
Conductive structure is copper conductive structure.
15. according to the method described in claim 1, it is characterized in that, the step (b) include use in step (b) phase
Between keep the bonding tool of first semiconductor element by several first conductive structures in first conductive structure
Several corresponding second conductive structures in ultrasonic bond to second conductive structure.
16. according to the method for claim 15, which is characterized in that during the step (b), the bonding tool with it is super
Sonic transducer is engaged to provide ultrasonic energy.
17. according to the method for claim 15, which is characterized in that the bonding tool utilizes during the step (b)
Vacuum keeps first semiconductor element.
18. according to the method described in claim 1, it is characterized in that, the step (b) is configured to including use by described
The bonding tools of 2 first semiconductor elements ultrasonically forms positioning bonding part.
19. according to the method for claim 18, which is characterized in that the step (c) includes using the bonding tool pair
Second semiconductor element is heated, to form the complete bonding part.
20. according to the method described in claim 1, it is characterized in that, the step (c) includes to first semiconductor element
It is heated at least one of second semiconductor element, to form the complete bonding part.
21. according to the method described in claim 1, it is characterized in that, the step (c) is included in group bonding technology,
During group's bonding technology, multiple complete bonding parts be formed on the first conductive structure of multiple first semiconductor elements with it is more
Between corresponding second conductive structure of a second semiconductor element.
22. according to the method for claim 21, which is characterized in that complete the group using the group's bonding tool heated
Bonding technology.
23. according to the method described in claim 1, it is characterized in that, further comprising the steps of：In first semiconductor element
Apply non-conducting material between second semiconductor element.
24. a kind of bonding system, including：
It is used to support the support construction of the first semiconductor element, first semiconductor element includes multiple first conductive structures；
Bonding tool, the bonding tool be used to carry include multiple second conductive structures the second semiconductor element, and use
In applying ultrasonic energy to second semiconductor element, with several second conductions in the multiple second conductive structure
Positioning bonding part is formed between structure several first conductive structures corresponding with the multiple first conductive structure.
25. bonding system according to claim 24, which is characterized in that after forming the positioning bonding part, the key
Conjunction tool be configured in the multiple second conductive structure described in several second conductive structures and the multiple first
In conductive structure complete bonding part is formed between several corresponding described first conductive structures.
26. bonding system according to claim 25, which is characterized in that the bonding tool is the bonding work heated
Tool, and the bonding tool applies heat to second semiconductor element, to form the complete bonding part.
27. bonding system according to claim 24, which is characterized in that further include the second bonding tool, wherein passing through
After the bonding tool forms the positioning bonding part, second bonding tool is configured in the multiple second conductive knot
Several described second conductive structures several described first conductions corresponding with the multiple first conductive structure in structure
Complete bonding part is formed between structure.
28. bonding system according to claim 27, which is characterized in that second bonding tool is the bonding heated
Tool, and second bonding tool applies heat to second semiconductor element, to form the complete bonding part.
29. bonding system according to claim 24, which is characterized in that further include group bonding tool, wherein passing through
It states after bonding tool forms the positioning bonding part, group's bonding tool is configured in multiple first semiconductor elements and phase
Complete bonding part is formed between multiple second semiconductor elements answered.
30. bonding system according to claim 29, which is characterized in that group's bonding tool is the bonding work heated
Tool, and group's bonding tool applies heat to second semiconductor element, to form the complete bonding part.
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| CN202410174466.7A CN118039509A (en) | 2017-03-14 | 2018-03-14 | System and method for soldering semiconductor elements |
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| US15/458,381 US9780065B2 (en) | 2013-10-08 | 2017-03-14 | Systems and methods for bonding semiconductor elements |
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| WO2023133977A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for semiconductor structure |
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| US20130228916A1 (en) * | 2012-03-02 | 2013-09-05 | Texas Instruments Incorporated | Two-solder method for self-aligning solder bumps in semiconductor assembly |
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- 2018-03-13 KR KR1020180029402A patent/KR102453172B1/en active IP Right Grant
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| CN1462474A (en) * | 2001-03-12 | 2003-12-17 | 索尼公司 | Method of manufacturing semiconductor device |
| US20100320258A1 (en) * | 2009-06-19 | 2010-12-23 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| CN102738025A (en) * | 2011-03-31 | 2012-10-17 | Soitec公司 | Method of forming bonded semiconductor structure, and semiconductor structure formed by such method |
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| TWI752187B (en) | 2022-01-11 |
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Application publication date: 20180925 |