CN108566167B - Low noise amplifying circuit - Google Patents
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The present invention relates to a low noise amplifying circuit. The low noise amplifying circuit comprises cascaded multistage low noise amplifiers and a first biasing unit or a second biasing unit for biasing the low noise amplifiers of each stage, wherein the first biasing unit is used for biasing the low noise amplifiers of the front stages in the multistage low noise amplifiers, the second biasing unit is used for biasing the low noise amplifiers of the rear stages in the multistage low noise amplifiers, and the second biasing unit is also used for providing biasing voltage for the first biasing unit; or the first bias unit biases the low noise amplifier of each of the plurality of stages of the low noise amplifiers. The multistage low noise amplifier in the low noise amplifying circuit can be in the optimal working state only by biasing one or two biasing units, has a simple structure and low cost, and simultaneously saves the use area of the PCB.
Description
The present application is a divisional application of patent application of the invention of the low noise amplifying circuit of the invention of the application number 2016108539300, which is the invention name of 2016 and 26.
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a low-noise amplifying circuit.
Background
The use of Ka-band broadband satellites will be an industry trend for future satellite broadband communications. The Ka band is mainly 26.5-40 GHz, which greatly improves the bandwidth of communication. A series of accessories and components have a crucial role in the construction of the entire communication network. Where for a ground station, the transceiver is a critical component in constructing the ground station. In applications for satellite broadcasting, a down-conversion block (LNB) of a transceiver is the most critical block to receive signals. The down-conversion module receives weak signals transmitted from the satellite, amplifies and down-converts the weak signals into intermediate frequency signals, and then carries out subsequent processing through the modem.
Because the noise coefficient of the receiver system is mainly determined by the low-noise amplifier, the design of the amplifier with reasonable gain, low noise, reliable and stable performance and large dynamic range is particularly important in the design of the receiving front end. The traditional low-noise amplifying circuit is composed of a plurality of complex electronic components, and has the advantages of high cost and large occupied area of a PCB.
Disclosure of Invention
Based on this, it is necessary to provide a low noise amplifying circuit for the problems of complicated circuit structure, high cost and large occupied area of the PCB.
A low noise amplifying circuit includes cascaded multi-stage low noise amplifiers, a first bias unit or a second bias unit biasing the low noise amplifiers of each stage,
the first bias unit is used for biasing a front-stage low-noise amplifier in the low-noise amplifiers, the second bias unit is used for biasing a rear-stage low-noise amplifier in the low-noise amplifiers, wherein the front-stage low-noise amplifier at least comprises a first-stage low-noise amplifier, the rear-stage low-noise amplifier at least comprises a last-stage low-noise amplifier, and the second bias unit is further used for providing bias voltage for the first bias unit; or (b)
The first bias unit biases the low noise amplifier of each of the plurality of stages of the low noise amplifiers.
In one embodiment, the first bias unit includes a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;
the base electrode of the first triode is connected with the first resistor and the second resistor respectively, the other end of the first resistor is grounded, and the other end of the second resistor is connected with the positive voltage power supply end; the collector electrode of the first triode is connected with a negative voltage power supply end through the third resistor and the fourth resistor; the emitter of the first triode is connected with the positive voltage power supply end through the fifth resistor;
the low noise amplifier is a transistor amplifier, and the source electrode of the transistor amplifier is grounded; the grid electrode of the transistor amplifier is connected with the common point of the third resistor and the fourth resistor; and the drain electrode of the transistor amplifier is connected with the emitter electrode of the first triode.
In one embodiment, the first bias unit includes a second triode; the emitter of the second triode is connected with the positive voltage power supply end through the second resistor, and the collector of the second triode is connected with the base of the second triode; and the base electrode of the second triode is respectively connected with the first resistor and the base electrode of the first triode.
In one embodiment, the second bias unit is a dc bias chip;
the direct current bias chip comprises a plurality of groups of grid bias pins and drain bias pins which are correspondingly arranged; wherein the gate bias pin provides a positive voltage to the gate of the transistor amplifier and the drain bias pin provides a negative voltage to the drain of the transistor amplifier; and
and a positive voltage output terminal and a negative voltage output terminal for providing voltage to the first bias unit.
In one embodiment, the low noise amplifying circuit comprises a first-stage transistor amplifier, a second-stage transistor amplifier and a third-stage transistor amplifier which are cascaded in three stages.
In one embodiment, the first bias unit biases the first stage transistor amplifier and the second stage transistor amplifier respectively; the third-stage transistor amplifier is biased into a second biasing unit;
the positive voltage output end of the second bias unit is connected with a fifth resistor in the first bias unit respectively; the negative voltage output end of the second bias unit is respectively connected with a fourth resistor in the first bias unit;
and the grid bias pin and the drain bias pin in any group of the second bias units are respectively connected with the grid and the drain of the third-stage transistor amplifier correspondingly.
In one embodiment, the low noise amplifying circuit comprises a PNP type universal double transistor for simultaneously biasing the first-stage transistor amplifier and the second-stage transistor amplifier; and biasing the third stage transistor amplifier to a second bias unit;
the grid electrodes of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected with the collector electrodes of the PNP type universal double transistors; the drains of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected with the emitters of the PNP type universal double transistors; the sources of the first-stage transistor amplifier and the second-stage transistor amplifier are grounded;
the positive voltage output end of the second bias unit is connected with the emitter of the PNP universal double transistor; the negative voltage output end of the second bias unit is connected with the collector electrode of the PNP type universal double transistor;
the grid bias pin and the drain bias pin in any group of the second bias units are correspondingly connected with the grid and the drain of the third transistor amplifier respectively.
In one embodiment, the first bias unit biases the low noise amplifier of each of the three stages of the low noise amplifiers;
and the emitters of the first triodes in the first bias units are all loaded with positive voltages, and the collectors of the first triodes are all loaded with negative voltages.
In one embodiment, the first stage transistor amplifier is biased by the first biasing unit; the second-stage transistor amplifier and the third-stage transistor amplifier are biased simultaneously to form a second biasing unit;
the positive voltage output end of the second bias unit is connected with a fifth resistor in the first bias unit; the negative voltage output end of the second bias unit is connected with a fourth resistor in the first bias unit;
the first group of grid bias pins and the drain bias pins in the second bias unit are correspondingly connected with the grid and the drain of the second-stage transistor amplifier respectively; and a second group of grid bias pins and drain bias pins in the second bias unit are respectively connected with the grid and the drain of the third-stage transistor amplifier correspondingly.
In one embodiment, the low noise amplifier further comprises a plurality of blocking capacitors, wherein the blocking capacitors are connected in series between two adjacent stages of the low noise amplifiers.
The low noise amplifying circuit comprises cascaded multistage low noise amplifiers and a first biasing unit or a second biasing unit for biasing the low noise amplifiers of each stage, wherein the first biasing unit is used for biasing the low noise amplifiers of the front stages in the multistage low noise amplifiers, the second biasing unit is used for biasing the low noise amplifiers of the rear stages in the multistage low noise amplifiers, and the second biasing unit is also used for providing biasing voltage for the first biasing unit; or the first bias unit biases the low noise amplifier of each of the plurality of stages of the low noise amplifiers. The multistage low noise amplifier in the low noise amplifying circuit can be in the optimal working state only by biasing one or two biasing units, has a simple structure and low cost, and simultaneously saves the use area of the PCB.
Drawings
FIG. 1 is a block diagram of a low noise amplifier circuit according to an embodiment;
FIG. 2 is a circuit diagram of a first bias unit in an embodiment;
FIG. 3 is a circuit diagram of a first bias cell in another embodiment;
FIG. 4 is a pin layout diagram of a DC offset chip according to one embodiment;
FIG. 5 is a graph of drain current versus drain voltage characteristics of a transistor amplifier according to one embodiment;
FIG. 6 is a circuit diagram of a low noise amplifier circuit according to an embodiment;
FIG. 7 is a second circuit diagram of a low noise amplifier circuit according to an embodiment;
FIG. 8 is a third circuit diagram of a low noise amplifier circuit according to an embodiment;
FIG. 9 is a circuit diagram of a low noise amplifier circuit according to an embodiment.
Detailed Description
In order that the invention may be understood more fully, the invention will be described with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
A low noise amplifying circuit amplifies a signal to be received or transmitted so that the total noise factor in the circuit is small and the power gain is high, and the low noise amplifying circuit can be used in a receiving and transmitting system in Ka band, ku band and X band.
As shown in fig. 1, which is a structural frame diagram of a low noise amplifying circuit, the low noise amplifying circuit includes cascaded multi-stage low noise amplifiers (M1, M2, …, mn) and a first bias unit 110 or a second bias unit 120 for biasing each stage of the low noise amplifiers.
The first bias unit 110 biases a front stage low noise amplifier among the multi-stage low noise amplifiers (M1, M2, …, mn), and the second bias unit 120 biases a rear stage low noise amplifier among the multi-stage low noise amplifiers (M1, M2, …, mn), wherein the front stage low noise amplifier includes at least a first stage low noise amplifier M1 and the rear stage low noise amplifier includes at least a last stage low noise amplifier Mn. The second bias unit 120 is further configured to provide a bias voltage to the first bias unit 110. Or the first biasing unit 110 biases each of the multi-stage low noise amplifiers (M1, M2, …, mn).
In the present embodiment, the Low Noise amplifying circuit is applied to a down conversion Block (LNB) of a transceiver, and amplifies a received Ka band high frequency signal by a multi-stage Low Noise amplifier (M1, M2, …, mn). The low noise amplifier is a transistor amplifier, and the transistor amplifier adopts a high electron mobility transistor (High Electron Mobility Transistor, HEMT) to amplify the high frequency signal. In other embodiments, the transistor amplifier may also be a heterojunction bipolar transistor (Heterojunction Bipolar Transistor, HBT), a pseudomorphic hemt (Pseudomorphic High Electron Mobility Transistor, pHEMT), a Metal-semiconductor Field effect transistor (Metal-Semiconductor FET), or a Junction Field Effect Transistor (JFET).
The high frequency signal is amplified by the multi-stage transistor amplifiers (M1, M2, …, mn), and each of the transistor amplifiers is provided with a corresponding first biasing unit 110 or second biasing unit 120, so that the transistor amplifiers are biased to make the transistor amplifiers in an optimal operation state, i.e., the drain voltage and the drain current operate in an optimal state. Meanwhile, the second bias unit 120 can also provide bias voltage for the first bias unit 110, so that the circuit design is simple, the design cost and the material cost are saved, and the area of the PCB is also saved.
The noise factor is the most important parameter of the low noise amplifier, and the noise factor formula of the multistage cascade low noise amplifier can be:
NF＝NF 1 +(NF 2 -1)/G 1 +(NF 3 -1)/(G 1 *G 2 )+…
wherein NF is n Noise Figure (NF), G is the n-th stage low Noise amplifier n As can be seen from the above formula, the noise of the first stage low noise amplifier and its key are the gain of the nth stage low noise amplifier. It can be seen that in order to make the total noise figure of the receiver small, the noise figure of the low noise amplifier of each stage is required to be small, and the power gain is high; the influence of the internal noise of each stage is different, the more the stages are, the greatest influence is on the total noise coefficient, so the total noise coefficient mainly depends on the first stages, which is the main reason that the receiver needs to adopt a high-gain low-noise amplifier.
Fig. 2 is a circuit diagram of a first bias unit according to an embodiment. The first bias unit 110 includes a first transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The base electrode of the first triode Q1 is respectively connected with a first resistor R1 and a second resistor R2, the other end of the first resistor R1 is grounded, and the other end of the second resistor R2 is connected with a positive voltage power supply end V OUT Connecting; the collector of the first triode Q1 is connected with the negative voltage power supply end V through a third resistor R3, a fourth resistor R4 NEG Connecting; the emitter of the first triode Q1 is connected with the positive voltage power supply end V through a fifth resistor R5 OUT And (5) connection. The source of the transistor amplifier M1 is grounded; the gate of the transistor amplifier M1, the third resistor R3 and the fourth resistorThe common point of R4 is connected; the drain of the transistor amplifier M1 is connected to the emitter of the first transistor Q1.
The transistor amplifier M1 can be operated at the drain voltage V by providing the required positive bias voltage and negative bias voltage to the transistor amplifier M1 through the first triode Q1 and the resistor in the first bias unit 110 DS ＝2V，I DS Optimal operating conditions of =10ma. Meanwhile, the first bias unit 110 also plays a role of stabilizing current, so that the transistor amplifier M1 obtains a stable direct current state. When the current of the transistor amplifier M1 increases due to the influence of the temperature change, the emitter current of the first transistor Q1 decreases, and thus the collector current of the first transistor Q1 decreases. Further, the voltage of the collector Q1 of the first triode connected with the negative voltage supply terminal is reduced, namely the gate voltage of the transistor amplifier M1 is reduced, so that the source leakage current I of the transistor amplifier M1 DS And is reduced, thereby functioning as negative feedback, so that the transistor amplifier M1 obtains a stable dc state.
A circuit diagram of a first bias cell in another embodiment is shown in fig. 3. The first bias unit 110 further includes a second transistor Q2; the emitter of the second triode Q2 is connected with the positive voltage power supply end V through a second resistor R2 OUT The collector of the second triode Q2 is connected with the base of the second triode Q2; the base electrode of the second triode Q2 is respectively connected with the first resistor R1 and the base electrode of the first triode Q1. Meanwhile, the second triode Q2 also plays roles in temperature compensation and stable working point.
In an embodiment, the first bias unit 110 further includes a sixth resistor R6 and a seventh resistor R7. The seventh resistor R7 is connected in series between the emitter of the first triode Q1 and the drain of the transistor amplifier M1, and the sixth resistor R6 is connected in series between the common point of the third resistor R3 and the fourth resistor R4 and the gate of the transistor amplifier M1. In this embodiment, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are all adjustable resistors, and can be used to adjust the current value of the output of the transistor amplifier.
In this embodiment, the first transistor Q1 and the second transistor are PNP transistors, or NPN first transistors, and PNP first transistors are adopted. In other embodiments, according to actual requirements, the first triode Q1 and the second triode are NPN type triodes, and may also be replaced by MOS transistors.
Because the source of the transistor amplifier M1 is grounded, the emitter of the first triode Q1 is connected with the positive voltage supply terminal V through the fifth resistor R5 OUT Is connected with a positive voltage power supply end V OUT A positive voltage supply terminal of 5V, in this embodiment, the positive voltage output terminal of the second bias unit 120 is a positive voltage supply terminal V OUT A voltage of 5 volts is provided. The 5V voltage is divided by the first resistor R1 and the second resistor R2 which are grounded, and the divided voltage is to the base electrode of the first triode Q1 to bias the base electrode of the first triode Q1. Meanwhile, the drain electrode of the transistor amplifier M1 is connected with the emitter electrode of the first triode Q1 through a seventh resistor R7 to obtain positive voltage bias voltage, and the grid electrode of the transistor amplifier M1 is connected with the negative voltage power supply end V through a sixth resistor R6, a fourth resistor R4 ENG In this embodiment, the negative voltage output terminal of the second bias unit 120 is the negative voltage power supply terminal V ENG Providing-2.5 volts to obtain negative bias voltage. In other embodiments, the voltages of the positive voltage supply terminal and the negative voltage supply terminal in the first bias unit 110 may also be supplied by a dc power supply, which is not limited thereto.
The second bias unit 120 is a dc bias chip U1, referring to fig. 4, the dc bias chip U1 includes multiple sets of gate bias pins and drain bias pins correspondingly arranged, and a positive voltage output terminal V for providing voltage to the first bias unit 110 OUT And a negative voltage output terminal V ENG . The drain bias pin D provides a positive voltage for the gate of the transistor amplifier, and the gate bias pin G provides a negative voltage for the drain of the transistor amplifier. In this embodiment, the dc bias chip U1 includes four sets of gate bias pins (G1, G2, G3, G4) and drain bias pins (D1, D2, D3, D4) arranged correspondingly, and a set of positive voltage output terminals V for providing voltages to the first bias unit 110 OUT And a negative voltage output terminal V ENG . Since the drain voltage of the transistor amplifier operating in the Ka band is 2V,the gate is typically negative. In this embodiment, the positive voltage output from the drain bias pin D of the dc bias chip U1 is 2 volts, and the negative voltage from the gate bias pin G is-0.6 volts.
As shown in fig. 5, the drain current-drain voltage characteristic diagram of the transistor amplifier is shown, and since each transistor amplifier has a different characteristic curve, in this embodiment, when the source of the transistor amplifier is grounded, the drain voltage is 2v, and the cell drain current is 10mA, the gate voltage of the transistor amplifier under this operating condition is-0.6 v. In other embodiments, the particular value of the dc bias voltage may be set based on the actual operating conditions of the transistor amplifier.
In this embodiment, the down-conversion module for satellite signal reception uses a three-stage transistor amplifier for amplification, and referring to fig. 6, includes a first-stage transistor amplifier M1, a second-stage transistor amplifier M2, and a third-stage transistor amplifier M3 in three-stage cascade connection. The circuit also comprises a plurality of blocking capacitors (C1 and C2), and the blocking capacitors are connected in series between the adjacent two-stage transistor amplifiers. The transistor amplifiers of each stage are cascaded through blocking capacitors (C1 and C2) so that the DC bias of the transistor amplifiers of each stage is not affected.
In order to make the total noise figure of the receiver small, the noise figures of the first stage transistor amplifier M1 and the second stage transistor amplifier M2 have a large influence on the total noise figure of the receiver, and referring to fig. 5, the first stage transistor amplifier M1 is biased to be the first biasing unit 110; biasing the second stage transistor amplifier M2 is a first biasing unit 110'; the third stage transistor amplifier M3 is biased as a second bias unit U1.
Wherein, the positive voltage output end V of the second bias unit U1 OUT Are each connected to a fifth resistor R5 in the first biasing unit (110, 110'); negative voltage output terminal V of second bias unit U1 NEG Are each connected to a fourth resistor R4 in the first biasing unit (110, 110'). The drain of the first stage transistor amplifier M1 is connected to the gate of the second stage transistor amplifier M2 via a first blocking capacitor C1. Gate bias lead in any one group of second bias units U1The pin G and the drain bias pin D are respectively connected to the gate and the drain of the third transistor amplifier M3. In the present embodiment, the gate bias pin G3 in the second bias unit U1 is connected to the gate of the third-stage transistor amplifier M3, and the drain bias pin D3 is connected to the drain of the third-stage transistor amplifier M3. The drain of the second stage transistor amplifier M2 is connected to the gate of the third stage transistor amplifier M3 via a second blocking capacitor C2. The drain of the third-stage transistor amplifier M3 outputs the amplified high-frequency signal to other devices (filters, etc.).
The first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 are all biased by the same active direct current, and the first triode Q1 is used for biasing the direct current of the transistor amplifier, so that the optimal direct current working states of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 can be ensured, and meanwhile, the temperature stability is also certain. The third-stage transistor amplifier M3 is biased by adopting a direct-current bias chip U1, the direct-current bias chip U1 directly outputs grid electrode and drain electrode bias voltages required by the third-stage transistor amplifier M3, positive voltage and negative voltage can be provided for the first triode Q1, the noise coefficient performance of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 is better, the circuit design is simplified, and the PCB area and the cost are reduced.
In one embodiment, the low noise amplifying circuit includes a PNP type universal double transistor U2 for simultaneously biasing the first stage transistor amplifier M1 and the second stage transistor amplifier M2; and the third stage transistor amplifier M3 is biased as the second bias unit U1.
The grid electrodes M1 and M2 of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected with the collector electrodes of the PNP type universal double-transistor U2; the drains of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 are respectively connected with the emitter of the PNP universal double-transistor U2; the sources of the first stage transistor amplifier M1 and the second stage transistor amplifier M2 are grounded. The positive voltage output end of the second bias unit U1 is connected with the emitter of the PNP universal double transistor U2; the negative voltage output end of the second bias unit U1 is connected with the collector of the PNP type universal double transistor U2. The gate bias pin G and the drain bias pin D in any one group of the second bias unit U1 are respectively connected to the gate and the drain of the third transistor amplifier M3 correspondingly. That is, the first bias unit 110 for biasing the first stage transistor amplifier M1 and the second stage transistor amplifier M2 may be integrated together to form one component, and referring to fig. 7, the integrated components may be replaced by one PNP type universal double transistor (NXP/PUMT 1), which simplifies the use of electronic components and reduces the use area of the PCB.
In one embodiment, referring to fig. 9, each of the three stages of low noise amplifiers is biased by a first biasing unit 110, that is, three first biasing units (110, 110', 110 ") respectively bias the three stages of transistor amplifiers (M1, M2, M3). The emitters of the first triodes (Q1, Q1 ') in the three first bias units (110, 110 ') are each loaded with a positive voltage, the collectors of the first transistors (Q1, Q1 ') are all loaded with a negative voltage. Three separated first triodes (Q1, Q1') are adopted for biasing the three-stage transistor amplifiers (M1, M2 and M3), so that the three-stage transistor amplifiers (M1, M2 and M3) can be provided with the optimal direct current working state, and meanwhile, the three-stage transistor amplifiers have certain temperature stability, and are small in total noise coefficient and high in power gain of the receiver. Wherein any adjacent two first triodes of the three first bias units (110, 110') can be replaced by a common dual first triode (NXP/PUMT 1).
In one embodiment, referring to fig. 8, the first stage transistor amplifier M1 is biased by a first biasing unit 110; the second bias unit U1 biases the second stage transistor amplifier M2 and the third stage transistor amplifier M3 simultaneously.
Wherein, the positive voltage output end V of the second bias unit U1 OUT Is connected to a fifth resistor R5 in the first bias unit 110; negative voltage output terminal V of second bias unit U1 NEG And a fourth resistor in the first bias unit 110R4 is attached. The grid bias pin G2 and the drain bias pin D2 in the first group in the second bias unit U1 are correspondingly connected with the grid and the drain of the second-stage transistor amplifier M2 respectively; the gate bias pin G3 and the drain bias pin D3 in the second group in the second bias unit U1 are respectively connected to the gate and the drain of the third transistor amplifier M3. In another embodiment, the second bias unit U1 may be used to bias the transistor amplifiers (M1, M2, M3) cascaded in three stages simultaneously, where the gate bias voltage and the drain bias unit provided by the second bias unit U1 need to meet the actual requirements. The first triode and the direct current bias chip U1 are reasonably arranged to bias the three-stage transistor amplifier, so that the use amount of electronic components on the PCB can be reduced, the circuit design is simplified, and the area and the cost of the PCB are reduced.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. A low noise amplifying circuit, comprising cascaded multistage low noise amplifiers and a first biasing unit for biasing each stage of the low noise amplifiers; wherein,,
the first bias unit comprises a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor; the base electrode of the first triode is connected with the first resistor and the second resistor respectively, the other end of the first resistor is grounded, and the other end of the second resistor is connected with the positive voltage power supply end; the collector electrode of the first triode is connected with a negative voltage power supply end through the third resistor and the fourth resistor; the emitter of the first triode is connected with the positive voltage power supply end through the fifth resistor;
the low noise amplifier is a transistor amplifier, and the source electrode of the transistor amplifier is grounded; the grid electrode of the transistor amplifier is connected with the common point of the third resistor and the fourth resistor; and the drain electrode of the transistor amplifier is connected with the emitter electrode of the first triode.
2. The low noise amplification circuit of claim 1, wherein the first bias unit further comprises a second transistor;
the emitter of the second triode is connected with the positive voltage power supply end through the second resistor, and the collector of the second triode is connected with the base of the second triode; and the base electrode of the second triode is respectively connected with the first resistor and the base electrode of the first triode.
3. The low noise amplification circuit of claim 1, wherein the first bias unit further comprises a sixth resistor and a seventh resistor;
the seventh resistor is connected in series between the emitter of the first triode and the drain of the transistor amplifier; the sixth resistor is connected in series between the common point of the third resistor and the fourth resistor and the grid electrode of the transistor amplifier.
4. A low noise amplifier circuit according to claim 3, wherein the fifth resistor, the sixth resistor and the seventh resistor are all adjustable resistors for adjusting the current value of the output of the transistor amplifier.
5. The low noise amplification circuit of claim 1, further comprising a second bias unit that provides a bias voltage for the first bias unit.
6. The low noise amplifier circuit of claim 5, wherein the second bias unit is a dc bias chip;
the DC bias chip comprises a positive voltage output end and a negative voltage output end which provide voltage for the first bias unit.
7. The low noise amplifier circuit of claim 1, wherein the low noise amplifier circuit comprises a first stage transistor amplifier, a second stage transistor amplifier and a third stage transistor amplifier in three stages of cascade connection.
8. The low noise amplifier circuit according to claim 7, wherein each of the low noise amplifiers of three stages is biased by the first biasing unit;
and the emitters of the first triodes in the first bias units are all loaded with positive voltages, and the collectors of the first triodes are all loaded with negative voltages.
9. The low noise amplifier circuit of claim 1, further comprising a plurality of dc blocking capacitors connected in series between adjacent two stages of the low noise amplifier.
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| CN201810355868.1A CN108566167B (en) | 2016-09-26 | 2016-09-26 | Low noise amplifying circuit |
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| CN201610853930.0A CN106330107B (en) | 2016-09-26 | 2016-09-26 | Low noise amplifier circuit |
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| CN108566167B (en) * | 2016-09-26 | 2023-05-16 | 深圳市华讯方舟卫星通信有限公司 | Low noise amplifying circuit |
| CN107612514B (en) * | 2017-10-30 | 2024-01-02 | 桂林电子科技大学 | Ka-band MMIC low-noise amplifier |
| CN109391236B (en) * | 2018-10-29 | 2022-04-19 | 北京无线电测量研究所 | Signal amplification circuit and millimeter wave signal amplification circuit |
| CN112332884B (en) * | 2020-11-19 | 2021-06-01 | 华南理工大学 | Gallium nitride-based radio frequency transceiving front-end structure |
| CN114513171B (en) * | 2022-02-15 | 2023-05-23 | 电子科技大学 | S-band low-noise amplifier based on HEMT |
| CN115483893A (en) * | 2022-09-02 | 2022-12-16 | 电子科技大学 | Low-temperature low-noise amplifier circuit without inductor, chip and radio frequency front-end circuit |
| CN115580233B (en) * | 2022-12-08 | 2023-06-16 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system for low-noise amplifier and dynamic bias circuit |
| CN115940827B (en) * | 2022-12-21 | 2023-08-18 | 宜确半导体（苏州）有限公司 | Low noise amplifier circuit and wireless communication system |
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| JP2004312668A (en) * | 2003-03-25 | 2004-11-04 | Sharp Corp | Low-noise converter |
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| CN206099907U (en) * | 2016-09-26 | 2017-04-12 | 深圳市华讯方舟卫星通信有限公司 | Low -noise amplifier circuit |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN106330107B (en) | 2018-07-03 |
| WO2018054151A1 (en) | 2018-03-29 |
| CN108566167A (en) | 2018-09-21 |
| CN106330107A (en) | 2017-01-11 |
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