CN108566167A - Low noise amplifier circuit - Google Patents
Low noise amplifier circuit Download PDFInfo
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- CN108566167A CN108566167A CN201810355868.1A CN201810355868A CN108566167A CN 108566167 A CN108566167 A CN 108566167A CN 201810355868 A CN201810355868 A CN 201810355868A CN 108566167 A CN108566167 A CN 108566167A
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- 238000006243 chemical reaction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
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- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The present invention relates to a kind of low noise amplifier circuits.Above-mentioned low noise amplifier circuit, the first bias unit or the second bias unit being biased including cascade multi-stage Low Noise Amplifier, to low-noise amplifier described in every level-one, wherein, it is first bias unit to be biased to prime low-noise amplifier in the multistage low-noise amplifier, it is second bias unit to be biased to rear class low-noise amplifier in the multistage low-noise amplifier, and second bias unit is additionally operable to provide bias voltage to first bias unit；Or in the multistage low-noise amplifier per level-one described in low-noise amplifier is biased is first bias unit.Multi-stage Low Noise Amplifier in the low noise amplifier circuit only needs one or two kinds of bias units to be biased for it, low-noise amplifiers at different levels can be made to be in best working condition, its is simple in structure, at low cost, while also saving the usable floor area of pcb board.
Description
The application is that on 09 26th, 2016 applying date, 2016108539300 invention and created name low noise of application number are put
The divisional application of the application for a patent for invention of big circuit.
Technical field
The present invention relates to electronic circuit technology fields, more particularly to low noise amplifier circuit.
Background technology
The utilization of Ka band broadband satellites will become the industrial trend of Future Satellite broadband connections.Ka wave bands are mainly
26.5~40GHz, which greatly enhances the bandwidth of communication.The structure of a series of corollary equipment and component for entire communication network
It builds and is of crucial importance.Wherein, for the small station of ground, transceiver is the critical component for building ground small station.
For in the application of satellite broadcasting, the down conversion module (low noise block, LNB) of transceiver to be to receive the most pass of signal
Key module.Down conversion module receives the small-signal from satellite launch, and down conversion module is amplified and down-converts to it
Intermediate-freuqncy signal carries out subsequent processing using modem.
Since receiver system noise coefficient is mainly determined by low-noise amplifier, a gain of design is reasonable, makes an uproar
Sound is low, dependable performance is stable, the amplifier of Larger Dynamic range is particularly important in the design of receiving front-end.Traditional low noise
Sound amplifying circuit is made of the electronic component of multiple complexity, and area that is of high cost, occupying pcb board is big.
Invention content
Based on this, it is necessary to which the problem complicated, of high cost for circuit structure, occupancy pcb board area is big provides a kind of low
Noise amplifier circuit.
A kind of low noise amplifier circuit, including cascade multi-stage Low Noise Amplifier, to low noise amplification described in every level-one
The first bias unit or the second bias unit that device is biased, wherein
It is first bias unit to be biased to prime low-noise amplifier in the multistage low-noise amplifier,
It is second bias unit to be biased to rear class low-noise amplifier in the multistage low-noise amplifier, wherein institute
It states prime low-noise amplifier and includes at least first order low-noise amplifier, the rear class low-noise amplifier includes at least last
Level-one low-noise amplifier, second bias unit are additionally operable to provide bias voltage to first bias unit；Or
To in the multistage low-noise amplifier per level-one described in low-noise amplifier is biased is described first
Bias unit.
In one of the embodiments, first bias unit include the first triode, first resistor, second resistance,
3rd resistor, the 4th resistance and the 5th resistance；
The base stage of first triode is connect with the first resistor, second resistance respectively, the first resistor it is another
One end is grounded, and the other end of the second resistance is connect with positive voltage feeder ear；Described in the collector warp of first triode
3rd resistor, the 4th resistance are connect with negative voltage feeder ear；The emitter of first triode is through the 5th resistance and institute
State the connection of positive voltage feeder ear；
The low-noise amplifier is crystal amplifier, and the source electrode of the crystal amplifier is grounded；The transistor
The grid of amplifier is connect with the common point of the 3rd resistor, the 4th resistance；The drain electrode of institute's crystal amplifier and described the
The emitter of one triode connects.
First bias unit, second triode in one of the embodiments,；The emitter of second triode
It is connect with the positive voltage feeder ear through the second resistance, the collector of second triode and second triode
Base stage connects；The base stage of second triode is connect with the base stage of the first resistor, the first triode respectively.
Second bias unit is direct current biasing chip in one of the embodiments,；
The direct current biasing chip includes multigroup gate bias pin being correspondingly arranged and drain electrode bias pin；Wherein, institute
State that gate bias pin provides positive voltage for the grid of the crystal amplifier, the drain electrode bias pin is the transistor
The drain electrode of amplifier provides negative voltage；And
Further include the positive voltage output end and negative voltage output end that voltage is provided for first bias unit.
The low noise amplifier circuit includes the first order transistor amplification of three-stage cascade in one of the embodiments,
Device, second level crystal amplifier, third level crystal amplifier.
In one of the embodiments, to the first order crystal amplifier, second level crystal amplifier respectively into
Row biasing is first bias unit；Be biased to the third level crystal amplifier is that the second biasing is single
Member；
Wherein, the positive voltage output end of second bias unit respectively with the 5th resistance in first bias unit
Connection；The negative voltage output end of second bias unit is connect with the 4th resistance in first bias unit respectively；
The gate bias pin, the bias pin that drains in any one group of second bias unit correspond to respectively and institute
State grid, the drain electrode connection of third level crystal amplifier.
The low noise amplifier circuit includes to the first order crystal amplifier, in one of the embodiments,
Two level crystal amplifier is carried out at the same time the general pair transistor of positive-negative-positive of biasing；And to the third level crystal amplifier
It is the second bias unit to be biased；
Wherein, the first order crystal amplifier, the grid of second level crystal amplifier are general double with positive-negative-positive respectively
The collector of transistor connects；The first order crystal amplifier, second level crystal amplifier drain electrode respectively with it is described
The emitter of the general pair transistor of positive-negative-positive connects；The source electrode of the first order crystal amplifier, second level crystal amplifier
Ground connection；
The positive voltage output end of second bias unit is connect with the emitter of the general pair transistor of the positive-negative-positive；Institute
The negative voltage output end for stating the second bias unit is connect with the collector of the general pair transistor of the positive-negative-positive；
The gate bias pin, the bias pin that drains in any one group of second bias unit correspond to respectively and institute
State grid, the drain electrode connection of third transistor amplifier.
Low-noise amplifier described in every level-one in low-noise amplifier described in three-level is carried out in one of the embodiments,
Biasing is first bias unit；
The emitter of the first triode in first bias unit loads positive voltage, the collector of the first triode
Load negative voltage.
Be biased in one of the embodiments, to the first order crystal amplifier is that first biasing is single
Member；It is the second bias unit to be carried out at the same time biasing to the second level crystal amplifier, third level crystal amplifier；
The positive voltage output end of second bias unit is connect with the 5th resistance in first bias unit；It is described
The negative voltage output end of second bias unit is connect with the 4th resistance in first bias unit；
Gate bias pin described in first group, the drain electrode bias pin be corresponding respectively in second bias unit and institute
State grid, the drain electrode connection of second level crystal amplifier；Gate bias pin described in second group in second bias unit,
The drain electrode bias pin is corresponding respectively to be connected with the grid of the third level crystal amplifier, drain electrode.
Further include multiple capacitances in one of the embodiments, the capacitance is serially connected with described in adjacent two-stage
Between low-noise amplifier.
Above-mentioned low noise amplifier circuit, including cascade multi-stage Low Noise Amplifier, to low noise amplification described in every level-one
The first bias unit or the second bias unit that device is biased, wherein to prime low noise in the multistage low-noise amplifier
It is first bias unit that acoustic amplifier, which is biased, to rear class low-noise amplifier in the multistage low-noise amplifier
It is second bias unit to be biased, and second bias unit is additionally operable to provide biasing to first bias unit
Voltage；Or in the multistage low-noise amplifier per level-one described in low-noise amplifier is biased is described first partially
Set unit.Multi-stage Low Noise Amplifier in the low noise amplifier circuit only needs one or two kinds of bias units inclined for its progress
It sets, low-noise amplifiers at different levels can be made to be in best working condition, it is simple in structure, at low cost, while also saving PCB
The usable floor area of plate.
Description of the drawings
Fig. 1 is the structural framing figure of an embodiment low noise amplifier circuit；
Fig. 2 is the circuit diagram of the first bias unit in an embodiment；
Fig. 3 is the circuit diagram of the first bias unit in another embodiment；
Fig. 4 is direct current biasing chip pin layout viewing in an embodiment；
Fig. 5 is the drain current versus drain voltage characteristic curve of crystal amplifier in an embodiment；
Fig. 6 is one of the circuit diagram of low noise amplifier circuit in an embodiment；
Fig. 7 is two of the circuit diagram of low noise amplifier circuit in an embodiment；
Fig. 8 is three of the circuit diagram of low noise amplifier circuit in an embodiment；
Fig. 9 is four of the circuit diagram of low noise amplifier circuit in an embodiment.
Specific implementation mode
To facilitate the understanding of the present invention, invention is described more fully below with reference to relevant drawings.It is given in attached drawing
The preferred embodiment of invention is gone out.But the present invention can realize in many different forms, however it is not limited to described herein
Embodiment.It is made the disclosure of the present invention more thorough and comprehensive on the contrary, purpose of providing these embodiments is.
Unless otherwise defined, all of technologies and scientific terms used here by the article and belong to the technical field of the present invention
The normally understood meaning of technical staff is identical.Description to be intended merely in the term used in the description of invention specific herein
Embodiment purpose, it is not intended that limitation the present invention.Term as used herein "and/or" includes one or more relevant
Any and all combinations of Listed Items.
A kind of low noise amplifier circuit is amplified processing to the signal that receives or will send, makes in its circuit
Overall noise factor is small, power gain is high, and low noise amplifier circuit can be used in the transmitting-receiving system in Ka wave bands, Ku wave bands, X-band
It unites medium.
As shown in Figure 1 is the structural framing figure of low noise amplifier circuit, wherein low noise amplifier circuit includes cascade
Multi-stage Low Noise Amplifier (M1, M2 ..., Mn) and the first bias unit that every level-one low-noise amplifier is biased
110 or second bias unit 120.
Be biased to prime low-noise amplifier in multi-stage Low Noise Amplifier (M1, M2 ..., Mn) is the first biasing
Unit 110, it is the second biasing to be biased to rear class low-noise amplifier in multi-stage Low Noise Amplifier (M1, M2 ..., Mn)
Unit 120, wherein prime low-noise amplifier includes at least first order low-noise amplifier M1, and rear class low-noise amplifier is extremely
Include afterbody low-noise amplifier Mn less.Second bias unit 120 is additionally operable to provide biased electrical to the first bias unit 110
Pressure.Or it is first partially to what is be biased per level-one low-noise amplifier in multi-stage Low Noise Amplifier (M1, M2 ..., Mn)
Set unit 110.
In the present embodiment, low noise amplifier circuit apply transceiver down conversion module (Low Noise Block,
LNB in), the Ka wave band high-frequency signals of reception are amplified by multistage low noise amplifier (M1, M2 ..., Mn).Wherein, low noise
Amplifier is crystal amplifier, and crystal amplifier uses high electron mobility transistor (High Electron
Mobility Transistor, HEMT) processing is amplified to high-frequency signal.In other embodiments, crystal amplifier is also
Can be Heterojunction Bipolar Transistors (Heterojunction Bipolar Transistor, HBT), the high electronics of pseudo-crystal type
Mobility transistor (Pseudomorphic High Electron Mobility Transistor, pHEMT), metal-are partly led
Body field-effect transistor (Metal-Semiconductor FET) or junction field effect transistor (Junction Field-
Effect Transistor, JFET).
High-frequency signal is amplified by multi-level transistor amplifier (M1, M2 ..., Mn), while per stage transistor
Amplifier is equipped with 110 or second bias unit 120 of corresponding first bias unit, is biased, makes to crystal amplifier
Crystal amplifier is in best working condition, i.e. drain voltage and drain current is operated in optimum state.Meanwhile second
Bias unit 120 can also be that the first bias unit 110 provide bias voltage, circuit design is simple, save design cost with
And Material Cost, while the area of PCB is saved again.
Wherein, noise coefficient is the most important parameter of low-noise amplifier, the noise of multi-stage cascade low-noise amplifier
Coefficient formula can be：
NF=NF1+(NF2-1)/G1+(NF3-1)/(G1*G2)+…
Wherein, NFnFor the noise coefficient (Noise Figure, NF) of n-th grade of low-noise amplifier, GnFor n-th grade of low noise
The gain of amplifier, from above-mentioned formula as can be seen that the noise and its key of first order low-noise amplifier.It can be seen that in order to make to connect
The overall noise factor of receipts machine is small, it is desirable that the noise coefficient of low-noise amplifiers at different levels is small, and power gain is high；And internal noises at different levels
Influence it is different, series is more forward, and influence to overall noise factor is maximum, so before overall noise factor depends primarily on most
Face what, here it is receiver will use high-gain low-noise amplifier the main reason for.
As shown in Figure 2 is the circuit diagram of the first bias unit in an embodiment.First bias unit 110 includes the one or three
Pole pipe Q1, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4 and the 5th resistance R5.First triode Q1's
Base stage is connect with first resistor R1, second resistance R2 respectively, the other end ground connection of first resistor R1, the other end of second resistance R2
With positive voltage feeder ear VOUTConnection；The collector of first triode Q1 is powered through 3rd resistor R3, the 4th resistance R4 and negative voltage
Hold VNEGConnection；The emitter of first triode Q1 is through the 5th resistance R5 and positive voltage feeder ear VOUTConnection.Crystal amplifier
The source electrode of M1 is grounded；The grid of crystal amplifier M1 is connect with the common point of 3rd resistor R3, the 4th resistance R4；Transistor is put
The drain electrode of big device M1 is connect with the emitter of the first triode Q1.
By the first triode Q1 and resistance in the first bias unit 110, can be provided for crystal amplifier M1 needs
The positive pressure bias voltage and negative pressure bias voltage wanted, make crystal amplifier M1 be operated in drain voltage VDS=2V, IDS=10mA
Best operating condition.Meanwhile first bias unit 110 also act the effect of stabling current, so that crystal amplifier M1 is obtained
Obtain stable DC state.If the electric current of crystal amplifier M1 rises because being acted upon by temperature changes so that the one or three
The emitter current of pole pipe Q1 becomes smaller, and then, the first triode Q1 collector currents also become smaller therewith.So that connection negative electricity
It presses the voltage of the first transistor collector Q1 of feeder ear also to reduce, that is, reduces the grid voltage of crystal amplifier M1, make
Obtain the source-drain current I of crystal amplifier M1DSIt reduces, to play the role of negative-feedback so that crystal amplifier M1 is obtained
Obtain stable DC state.
As shown in Figure 3 is the circuit diagram of the first bias unit in another embodiment.First bias unit 110 further includes
Two triode Q2；The emitter of second triode Q2 is through second resistance R2 and positive voltage feeder ear VOUTConnection, the second triode Q2
Collector connect with the base stage of the second triode Q2；The base stage of second triode Q2 respectively with first resistor R1, the one or three pole
The base stage of pipe Q1 connects.It is also to play the role of temperature-compensating and stable operating point that the second triode Q2 is arranged simultaneously.
In one embodiment, the first bias unit 110 further includes the 6th resistance R6 and the 7th resistance R7.7th resistance R7 strings
It is connected between the emitter and the drain electrode of crystal amplifier M1 of the first triode Q1, the 6th resistance R6 is serially connected with 3rd resistor
R3, the 4th resistance R4 common point and the grid of crystal amplifier M1 between.In the present embodiment, the 5th resistance R5, the 6th
Resistance R6, the 7th resistance R7 are adjustable resistance, can be used for adjusting the current value of the output of crystal amplifier.
In the present embodiment, the first triode Q1, the second triode are for PNP type triode, or NPN type
One triode, it is the first triode of positive-negative-positive to use.In other embodiments, can according to actual demand, the first triode Q1,
Second triode is NPN type triode, can also also be substituted with metal-oxide-semiconductor.
Since the source electrode of crystal amplifier M1 is grounded, the emitter of the first triode Q1 is through the 5th resistance R5 and positive voltage
Feeder ear VOUTConnection, wherein positive voltage feeder ear VOUTIt is biased in the present embodiment by second for 5 volts of positive voltage feeder ear
The positive voltage output end of unit 120 is positive voltage feeder ear VOUT5 volts of voltages are provided.5 volts of voltages pass through with the first resistor R1 on ground,
Second resistance R2 is divided, and is divided to the base stage of the first triode Q1, is the base bias of the first triode Q1.Meanwhile it is brilliant
The drain electrode of body pipe amplifier M1 is connect by the 7th resistance R7 with the emitter of the first triode Q1, obtains positive pressure bias voltage,
The grid of crystal amplifier M1 is through the 6th resistance R6, the 4th resistance R4 and negative voltage feeder ear VENGConnection, in the present embodiment
In, it is negative voltage feeder ear V by the negative voltage output end of the second bias unit 120ENG- 2.5 volt voltages are provided, it is inclined to obtain negative pressure
Set voltage.In other embodiments, the voltage of the positive voltage feeder ear in the first bias unit 110 and negative voltage feeder ear is also
It can be powered by DC power supply, however it is not limited to this.
Second bias unit 120 is direct current biasing chip U1, and with reference to figure 4, direct current biasing chip U1 includes that multigroup correspondence is set
The gate bias pin and drain electrode bias pin set and the positive voltage output end V that voltage is provided for the first bias unit 110OUT
With negative voltage output end VENG.Wherein, bias pin D provides positive voltage for the grid of crystal amplifier, gate bias is drawn for drain electrode
Foot G provides negative voltage for the drain electrode of crystal amplifier.In the present embodiment, direct current biasing chip U1 is correspondingly arranged including four groups
Gate bias pin (G1, G2, G3, G4) and drain electrode bias pin (D1, D2, D3, D4), also one group be the first bias unit
110 provide the positive voltage output end V of voltageOUTWith negative voltage output end VENG.Due to being operated in the crystal amplifier of Ka wave bands
Drain voltage be 2V, grid is generally negative.In the present embodiment, the drain electrode bias pin D of direct current biasing chip U1 is exported
Positive voltage is 2 volts, and the negative voltage of gate bias pin G is -0.6 volt.
As shown in Figure 5 is the drain current versus drain voltage characteristic figure of crystal amplifier, since each transistor is put
Big device has different characteristic curves, in the present embodiment, when the source electrode ground connection of crystal amplifier, drain voltage be 2 volts,
When first drain current is 10mA, the grid voltage of the crystal amplifier under this operating condition is -0.6 volt.In other implementations
It, can be according to the actual operating conditions of crystal amplifier, to set the concrete numerical value of DC offset voltage in example.
In the present embodiment, it is put using three-level crystal amplifier for the down conversion module of satellite signal receiving
Greatly, with reference to figure 6, including the first order crystal amplifier M1 of three-stage cascade, second level crystal amplifier M2, third level crystal
Pipe amplifier M3.Wherein, further include multiple capacitances (C1, C2), capacitance is serially connected with adjacent two-staged transistor amplifier
Between.It is cascaded by capacitance (C1, C2) per between level-one crystal amplifier so that the transistor per level-one amplifies
Device direct current biasing is independent of each other.
In order to keep the overall noise factor of receiver small, first order crystal amplifier M1, second level crystal amplifier
The noise coefficient of M2 is affected to the overall noise factor of receiver, with reference to figure 5, is carried out to first order crystal amplifier M1 inclined
It is the first bias unit 110 to set；It is the first bias unit 110 ' to be biased to second level crystal amplifier M2；To
It is the second bias unit U1 that three-level crystal amplifier M3, which is biased,.
Wherein, the positive voltage output end V of the second bias unit U1OUTWith in the first bias unit (110,110 ')
Five resistance R5 connections；The negative voltage output end V of second bias unit U1NEGWith in the first bias unit (110,110 ')
Four resistance R4 connections.The drain electrode of first order crystal amplifier M1 is through the first capacitance C1 and second level crystal amplifier M2
Grid connection.Gate bias pin G in second any one group of bias unit U1, drain electrode bias pin D corresponding and third respectively
The grid of crystal amplifier M3, drain electrode connection.In the present embodiment, the gate bias pin G3 in the second bias unit U1 with
The grid of third level crystal amplifier M3 connects, and the drain electrode of drain electrode bias pin D3 and third level crystal amplifier M3 connects
It connects.Grid of the drain electrode of second level crystal amplifier M2 through the second capacitance C2 and third level crystal amplifier M3 connects
It connects.The high-frequency signal that the drain electrode of third level crystal amplifier M3 exports amplification gives other equipment (filter etc.).
First order crystal amplifier M1, second level crystal amplifier M2 are all made of identical active direct current biasing, lead to
It crosses the first triode Q1 and direct current biasing is carried out to crystal amplifier, can ensure first order crystal amplifier M1, the second level
The best DC operation state of crystal amplifier M2, while also there is certain temperature stability.Third level transistor amplifies
Device M3 is biased using direct current biasing chip U1, and direct current biasing chip U1 is directly exported needed for third level crystal amplifier M3
Grid and drain bias voltage, while positive voltage and negative voltage can also be provided for the first triode Q1, meet the first order
While crystal amplifier M1, second level crystal amplifier M2 noise-figure performances are preferable, circuit design is simplified, is reduced
PCB surface product and cost.
In a wherein embodiment, low noise amplifier circuit includes to first order crystal amplifier M1, second level crystal
Pipe amplifier M2 is carried out at the same time the general pair transistor U2 of positive-negative-positive of biasing；And third level crystal amplifier M3 is carried out inclined
It is the second bias unit U1 to set.
Wherein, first order crystal amplifier M1, the grid M2 of second level crystal amplifier are logical with the positive-negative-positive respectively
It is connected with the collector of pair transistor U2；First order crystal amplifier M1, second transistor amplifier M2 drain electrode respectively with
The emitter of the general pair transistor U2 of positive-negative-positive connects；The source of first order crystal amplifier M1, second level crystal amplifier M2
Pole is grounded.The positive voltage output end of second bias unit U1 is connect with the general pair transistor U2 emitters of positive-negative-positive；Second biasing is single
The negative voltage output end of first U1 is connect with the collector of the general pair transistor U2 of positive-negative-positive.In second any one group of bias unit U1
Gate bias pin G, drain electrode bias pin D corresponding respectively connected with the grid of third transistor amplifier M3, drain electrode.
I.e., it is possible to the first bias unit 110, the second level crystal amplifier M2 that will be biased to first order crystal amplifier M1
Two the first triodes (Q1, Q1 ') being biased in the first bias unit 110 ' can integrate, and form a first device
Part, with reference to figure 7, a general pair transistor of positive-negative-positive (NXP/PUMT1) may be used to replace in integrated component, simplifies
The use of electronic component, while also reducing the usable floor area of pcb board.
It is inclined to being carried out per level-one low-noise amplifier in three-level low-noise amplifier with reference to figure 9 in a wherein embodiment
What is set is the first bias unit 110, that is, three the first bias units (110,110 ', 110 ") are brilliant to reply three-level respectively
Body pipe amplifier (M1, M2, M3) is biased.The first triode in three the first bias units (110,110 ', 110 ")
The emitter of (Q1, Q1 ', Q1 ") loads positive voltage, and the collector of the first triode (Q1, Q1 ', Q1 ") loads negative voltage.
The first triodes (Q1, Q1 ', Q1 ") of three separation are all made of to three-level crystal amplifier (M1, M2, M3) to be biased,
The DC operation state that three-level crystal amplifier (M1, M2, M3) can be supplied to best, while also having certain temperature steady
It is qualitative, it is that the overall noise factor of receiver is small, power gain is high.Wherein, three the first bias units (110,110 ', 110 ")
In, two the first triodes of arbitrary neighborhood can be replaced with general double first triodes (NXP/PUMT1).
In a wherein embodiment, with reference to figure 8, it is that the first biasing is single to be biased to first order crystal amplifier M1
Member 110；It is the second bias unit to be carried out at the same time biasing to second level crystal amplifier M2, third level crystal amplifier M3
U1。
Wherein, the positive voltage output end V of the second bias unit U1OUTConnect with the 5th resistance R5 in the first bias unit 110
It connects；The negative voltage output end V of second bias unit U1NEGIt is connect with the 4th resistance R4 in the first bias unit 110.Second partially
It is corresponding with second level crystal amplifier M2 respectively to set in unit U1 gate bias pin G2 in first group, drain electrode bias pin D2
Grid, drain electrode connection；Gate bias pin G3, drain electrode bias pin D3 are corresponded to respectively in second group in second bias unit U1
It is connected with the grid of third level crystal amplifier M3, drain electrode.In another embodiment, the second bias unit U1 can also be used
Pair the crystal amplifier (M1, M2, M3) of three-stage cascade is biased simultaneously, the gate bias that the second bias unit U1 is provided
Voltage, drain electrode bias unit need to meet actual demand.U1 pairs three of first triode and direct current biasing chip through reasonable settings
Grade crystal amplifier is biased, and can be reduced the usage amount of electronic component on pcb board, be simplified circuit design, is reduced
The area and cost of pcb board.
Each technical characteristic of embodiment described above can be combined arbitrarily, to keep description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (9)
1. a kind of low noise amplifier circuit, which is characterized in that including cascade multi-stage Low Noise Amplifier and to every level-one institute
State the first bias unit that low-noise amplifier is biased；Wherein,
First bias unit includes the first triode, first resistor, second resistance, 3rd resistor, the 4th resistance and the 5th
Resistance；The base stage of first triode is connect with the first resistor, second resistance respectively, the other end of the first resistor
Ground connection, the other end of the second resistance are connect with positive voltage feeder ear；The collector of first triode is through the third
Resistance, the 4th resistance are connect with negative voltage feeder ear；The emitter of first triode through the 5th resistance with it is described just
Power voltage supply end connects；
The low-noise amplifier is crystal amplifier, and the source electrode of the crystal amplifier is grounded；The transistor amplification
The grid of device is connect with the common point of the 3rd resistor, the 4th resistance；The drain electrode of institute's crystal amplifier and the described 1st
The emitter of pole pipe connects.
2. low noise amplifier circuit according to claim 1, which is characterized in that first bias unit further includes second
Triode；
The emitter of second triode is connect through the second resistance with the positive voltage feeder ear, second triode
Collector connect with the base stage of second triode；The base stage of second triode respectively with the first resistor,
The base stage of one triode connects.
3. low noise amplifier circuit according to claim 1, which is characterized in that first bias unit further includes the 6th
Resistance and the 7th resistance；
7th resistance is serially connected between the emitter and the drain electrode of the crystal amplifier of first triode；It is described
6th resistance be serially connected with the 3rd resistor, the 4th resistance common point and the grid of the crystal amplifier between.
4. low noise amplifier circuit according to claim 3, which is characterized in that the 5th resistance, the 6th resistance, the 7th
Resistance is adjustable resistance, the current value of the output for adjusting the crystal amplifier.
5. low noise amplifier circuit according to claim 1, which is characterized in that further include being carried for first bias unit
For the second bias unit of bias voltage.
6. low noise amplifier circuit according to claim 5, which is characterized in that second bias unit is direct current biasing
Chip；
The direct current biasing chip includes positive voltage output end and the negative voltage output that voltage is provided for first bias unit
End.
7. low noise amplifier circuit according to claim 1, which is characterized in that the low noise amplifier circuit includes three
The cascade first order crystal amplifier of grade, second level crystal amplifier, third level crystal amplifier.
8. low noise amplifier circuit according to claim 7, which is characterized in that every in low-noise amplifier described in three-level
What low-noise amplifier described in level-one was biased is first bias unit；
The emitter of the first triode in first bias unit loads positive voltage, and the collector of the first triode adds
Load with voltage.
9. low noise amplifier circuit according to claim 1, which is characterized in that further include multiple capacitances, it is described every
Between straight capacitance series low-noise amplifier described in adjacent two-stage.
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| CN201810355868.1A CN108566167B (en) | 2016-09-26 | 2016-09-26 | Low noise amplifying circuit |
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|---|---|---|---|
| CN201610853930.0A CN106330107B (en) | 2016-09-26 | 2016-09-26 | Low noise amplifier circuit |
| CN201810355868.1A CN108566167B (en) | 2016-09-26 | 2016-09-26 | Low noise amplifying circuit |
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| CN201610853930.0A Division CN106330107B (en) | 2016-09-26 | 2016-09-26 | Low noise amplifier circuit |
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| CN108566167B CN108566167B (en) | 2023-05-16 |
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Cited By (2)
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| CN114513171A (en) * | 2022-02-15 | 2022-05-17 | 电子科技大学 | Low noise amplifier of S wave band based on HEMT |
| CN115940827A (en) * | 2022-12-21 | 2023-04-07 | 宜确半导体（苏州）有限公司 | Low Noise Amplifier Circuit and Wireless Communication System |
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| CN108566167B (en) * | 2016-09-26 | 2023-05-16 | 深圳市华讯方舟卫星通信有限公司 | Low noise amplifying circuit |
| CN107612514B (en) * | 2017-10-30 | 2024-01-02 | 桂林电子科技大学 | Ka-band MMIC low-noise amplifier |
| CN109391236B (en) * | 2018-10-29 | 2022-04-19 | 北京无线电测量研究所 | Signal amplification circuit and millimeter wave signal amplification circuit |
| CN112332884B (en) * | 2020-11-19 | 2021-06-01 | 华南理工大学 | Gallium nitride-based radio frequency transceiving front-end structure |
| CN115483893A (en) * | 2022-09-02 | 2022-12-16 | 电子科技大学 | Low-temperature low-noise amplifier circuit without inductor, chip and radio frequency front-end circuit |
| CN115580233B (en) * | 2022-12-08 | 2023-06-16 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system for low-noise amplifier and dynamic bias circuit |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108566167B (en) | 2023-05-16 |
| CN106330107B (en) | 2018-07-03 |
| WO2018054151A1 (en) | 2018-03-29 |
| CN106330107A (en) | 2017-01-11 |
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Effective date of registration: 20230616 Address after: 518101 room 404, building 37, chentian Industrial Zone, chentian community, Xixiang street, Bao'an District, Shenzhen, Guangdong Province Patentee after: Shenzhen Huaxun ark Photoelectric Technology Co.,Ltd. Patentee after: SHENZHEN HUAXUN ARK SATELLITE TELECOMMUNICATIONS Co.,Ltd. Address before: 518101 Room 208, Building 36, Chentian Industrial Zone, Baotian 1st Road, Xixiang Street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN HUAXUN ARK SATELLITE TELECOMMUNICATIONS Co.,Ltd. Patentee before: CHINA COMMUNICATION TECHNOLOGY Co.,Ltd. |