CN108563607A - A kind of device and method for improving communication and processing speed in avionics system - Google Patents
A kind of device and method for improving communication and processing speed in avionics system Download PDFInfo
- Publication number
- CN108563607A CN108563607A CN201810333245.4A CN201810333245A CN108563607A CN 108563607 A CN108563607 A CN 108563607A CN 201810333245 A CN201810333245 A CN 201810333245A CN 108563607 A CN108563607 A CN 108563607A
- Authority
- CN
- China
- Prior art keywords
- data
- module
- fpga
- channel
- airborne equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
Abstract
The invention discloses the device and method for improving communication and processing speed in avionics system, can improve communication process speed, increase the airborne equipment quantity of processing, and keep the stability and reliability of avionics system.The device includes the FPGA and CPU connected by SRIO interfaces；Wherein, FPGA has：Multiple serial input interfaces, multiple order caching modules being connect with serial input interface, first group of packet module being connect with each order caching module；CPU has：Unpack module, data processing module, second group of packet module；FPGA further comprises：Decoding module for reading the control data for being directed to each airborne equipment in the second heartbeat data packets, and is sent to corresponding transmission cache module；Multiple transmission cache modules are respectively connected to multiple serial output interfaces and at least one Ethernet interface, and for sending control data to each airborne equipment at a predetermined rate according to communication protocol corresponding with interface.
Description
Technical field
The present invention relates to avionics fields, more particularly to one kind in avionics system for improving communication and handling
The device and method of speed.
Background technology
The information of various avionic devices on aircraft is carried out at unified usually using unified processor on modern aircraft
Reason combines the same or similar equipment of function in a component, over the display the relevant parameter of synthesis display, and each
It is transmitted for information about by airborne databus between avionic device, to make all aviation electronics on entire aircraft set
Standby performance reaches higher level, and such system is known as integrated avionic system.
Integrated avionic system includes the numerous various airborne equipments of function, such as synthetical display control unit, data connect
Mouthful unit, double remaining air data systems, INS/GNSS integrated navigation systems, comprehensive wireless electric system, head-up display unit, with
And cockpit monitoring system etc., these equipment are often required for summarizing connection by data interface unit DIU, and receive from not
The communication data of same equipment.The data that existing data interface unit sends each equipment generally by CPU therein
Carry out time-division processing.Since most of airborne equipment is required for being connected to data-interface list using serial data interfaces such as RS-422
Member, CPU directly receives such low speed asynchronous bus mode and communicates the time that can occupy CPU in real time, and RS-422 communication speed ratios
CPU processing speeds are many slowly, therefore can reduce its processing capacity and place due to interrupting excessively and very disruptive CPU processing procedures
Manage speed.For example, the 5 road serial line interfaces of DIU are connected to 5 serial data channels of airborne equipment, each channel fix with
The period transmission data of 10ms, but each channel data length is different, the data packet such as Fig. 1 first halves received in CPU each periods
Shown in point；There may be 5 different points of interruption (to be sent per road 10ms cycle datas within the period of 10ms by so CPU
Time point, as shown in the lower half portion Fig. 1), after CPU receives data, every 2ms (10ms/5=2ms) is needed to interrupt primary carry out 5 times
Data processing (P1~P5) increases cpu data reception and toggles number of processes with processing, and when interruption times and processing
Between can with external device quantity increase and increase.
Moreover, with the continuous promotion of integrated avionic system complexity, the various equipment of required connection and corresponding number
It is also continuously increased according to number of channels, causes the processing capacity of data interface unit and the slower problem of data processing speed that can not expire
The communication process demand of the more airborne equipments of foot, and then integrated avionic system overall performance and reliability is caused to be unable to reach higher
The requirement of standard avionics system.
Invention content
An object of the present invention at least that, for how to overcome the above-mentioned problems of the prior art, provide one kind
Device and method for improving communication and processing speed in avionics system can improve communication process speed, increase processing
Airborne equipment quantity, and keep the stability and reliability of avionics system.
To achieve the goals above, the technical solution adopted by the present invention includes following aspects.
A kind of device for improving communication and processing speed in avionics system comprising connected by SRIO interfaces
FPGA and CPU；
Wherein, FPGA has：Multiple serial input interfaces, the number sent for receiving multiple airborne equipment data channel
According to；Multiple order caching modules being connect with serial input interface, for carrying out temporal cache to the data from each channel；With
First group of packet module of each order caching module connection, for the data of caching to package according to preset coding mode
To obtain the first heartbeat data packets, and the first heartbeat data packets are passed through between FPGA and CPU according to scheduled heart beat cycle
SRIO interfaces are sent to CPU；
CPU has：Module is unpacked, for being read from the first heartbeat data packets from FPGA according to preset coding mode
The data in each channel；Data processing module is handled for the data to each channel, generates the control for each airborne equipment
Data processed；Second group of packet module packages for that will control data according to preset coding mode, to obtain the second beats
It is sent to FPGA according to packet, and according to scheduled second heart beat cycle；
FPGA further comprises：The decoding module being connect with each transmission cache module, for reading the second heartbeat data
It is directed to the control data of each airborne equipment in packet, and is sent to corresponding transmission cache module；Multiple transmission cache modules, point
Be not connected to multiple serial output interfaces and at least one Ethernet interface, and according to communication protocol corresponding with interface with
Scheduled rate sends control data to each airborne equipment.
A method of for improving communication and processing speed in avionics system comprising following steps：
The data sent by the multiple airborne equipment data channel of multiple serial input interfaces of FPGA；Multiple and string
The order caching module of row input interface connection carries out temporal cache to the data from each channel；With each order caching module
First group of packet module of connection packages the data of caching according to preset coding mode to obtain the first heartbeat data packets,
And the first heartbeat data packets are sent to by CPU by the SRIO interfaces between FPGA and CPU according to scheduled heart beat cycle；
Unpacking module in CPU reads according to preset coding mode from the first heartbeat data packets from FPGA each logical
The data in road；Data processing module handles the data in each channel, generates the control data for each airborne equipment；Second
Group packet module packages data are controlled according to preset coding mode, to obtain the second heartbeat data packets, and according to predetermined
The second heart beat cycle be sent to FPGA；
In FPGA each machine is directed to each send in decoding module the second heartbeat data packets of reading that cache module is connect
The control data of equipment are carried, and are sent to corresponding transmission cache module；Multiple transmission cache modules are respectively connected to multiple strings
Row output interface and at least one Ethernet interface, and according to communication protocol corresponding with interface at a predetermined rate to each
Airborne equipment sends control data.
In conclusion by adopting the above-described technical solution, the present invention at least has the advantages that：
By the way that FPGA to be combined with CPU, and high-speed bus communications technology is combined to carry out the caching of data and organize to wrap, it can
When carrying out a large amount of airborne equipment communication data processing, CPU processing speeds are improved, and the capacity of equipment quantity handled can be opposite
Increase, and improves avionics system overall performance and stability.
Description of the drawings
Fig. 1 is the time diagram that data interface unit is communicated and handled in existing avionics system.
Fig. 2 is the application connection diagram of data interface unit DIU according to the ... of the embodiment of the present invention.
Fig. 3 is according to the ... of the embodiment of the present invention for raising to communicate in avionics system and the apparatus structure of processing speed shows
It is intended to.
Fig. 4 is that device and method according to the ... of the embodiment of the present invention are applied and led in the data interface unit of avionics system
The time diagram of letter and processing.
Specific implementation mode
With reference to the accompanying drawings and embodiments, the present invention will be described in further detail, so that the purpose of the present invention, technology
Scheme and advantage are more clearly understood.It should be appreciated that described herein, specific examples are only used to explain the present invention, and does not have to
It is of the invention in limiting.
Fig. 2 shows the application connection diagram of data interface unit DIU according to the ... of the embodiment of the present invention, data-interface lists
First DIU by serial communication interface be connected to inertial navigation system/Global Satellite Navigation System integrated navigation system INS/GNSS,
Air data computer ADC, aeroengine parameter collector DTC, data logger VMS and comprehensive wireless electric system CNS, and
It is connected to synthetical display control cells D U by Ethernet interface.Comprehensive wireless electric system CNS includes mainly VHF radio
VHF, multimode rake receiver VOR/ILS, radio altimeter RA, Automatic Direction Finder ADF, range finder DME, aviation management answering machine XPDR and
The equipment such as flight interphone ACU are integrated into an integrating device jointly, unified to pass through data processor and DIU and other external equipments
Carry out data interaction.
Fig. 3 is according to the ... of the embodiment of the present invention for raising to communicate in avionics system and the apparatus structure of processing speed shows
It is intended to, which is applied to improve communication and processing speed in data interface unit DIU, to increase avionics system
The quantity for the airborne equipment that system can be handled, and keep higher stability and reliability.The device includes passing through SRIO interfaces
The FPGA and CPU of (Serial Rapid I/O, serially rapidly input output interface) connection；FPGA is mainly responsible for the receipts of data
Hair, caching, heartbeat data group packet；CPU be substantially carried out data processing (data are verified, according to preset condition in the future
Specified equipment is sent to by corresponding channel from the data of distinct device).
Wherein, FPGA has：Multiple serial input interfaces (RS_RX-1 to RS_RX-n, for example, n be 20), it is more for receiving
The data that a airborne equipment data channel is sent；
Multiple order caching modules being connect with serial input interface, for being delayed to the data from each channel temporarily
It deposits；
First group of packet module being connect with each order caching module, the data for that will cache are according to preset coding staff
Formula packages to obtain the first heartbeat data packets, and according to scheduled first heart beat cycle (such as 5ms or 2ms) by first
Heartbeat data packets are sent to CPU by the communication interface between FPGA and CPU；
CPU has：Module is unpacked, for being read from the first heartbeat data packets from FPGA according to preset coding mode
The data in each channel；
Data processing module, handled for the data to each channel (such as including：Data are verified, assignment,
Data fusion, format conversion, protocol conversion etc.), generate the control data for each airborne equipment；
Group packet module, packages for that will control data according to preset coding mode, to obtain the second heartbeat data
Packet, and sent according to scheduled second heart beat cycle (such as 5ms, 2ms, 1ms, the first heart beat cycle can be less than or equal to)
To FPGA；
FPGA further comprises：The decoding module being connect with each transmission cache module, for reading the second heartbeat data
It is directed to the control data of each airborne equipment in packet, and is sent to corresponding transmission cache module；
Multiple transmission cache modules, being respectively connected to multiple serial output interfaces, (RS_TX-1 to RS_TX-m, such as m are small
In or equal to n) and at least one Ethernet interface (ETH), and according to communication protocol corresponding with interface with scheduled speed
Rate sends control data to each airborne equipment.
In order to access the airborne equipment of measures of dispersion evidence, FPGA can also have more discrete magnitude input interfaces and it is corresponding from
Dissipate amount output interface.
BRAM (Block RAM, block random access memory) may be used in order caching module and transmission cache module
Temporal cache is done, neither packet loss nor affects on communication delay.Since the communication between FPGA and CPU uses SRIO interfaces, communication
Speed is 1.25Gbps (speed also can be improved to 3.125Gbps), because DMA (Direct can be used in the SRIO interfaces of CPU side
Memory Access, direct memory access) mode, sending and receiving for data packet be not take up the CPU time, wrapped in real time completely
The data packet can also be dealt into CPU by FPGA immediately after receiving data packet under tupe, and communication speed is fast, real-time.And
And P2020NXN2MHC chips may be used in CPU, ISO3080DWR communication modules may be used in serial input, output interface,
XC7A100T-2FGG484I chips may be used in FPGA.
First group of packet module packages to obtain the first heartbeat data packets, specifically includes：According to each airborne equipment pair
The data update period of data channel is answered to determine whether to read the data in the channel, for example, the data packet length in the 1st channel is
The heart beat cycle of 30 bytes, update cycle 10ms, FPGA is 5ms, then every a heartbeat data packets, just from order caching
The data in the 1st channel are read in module.For another example, the data packet length in the 2nd channel is 30 bytes, and the update cycle is
The heart beat cycle of 1ms, FPGA are 2ms, then each heartbeat data packets are read from order caching module in the 2nd channel
Data, and each heartbeat data packets include the data in the 2nd channel twice cached in order caching module.
Specifically, the channel data of each airborne equipment corresponding channel could be provided as identical format, for example, the first word
Section is airborne equipment port numbers, and the second byte is the high byte of channel data length, and third byte is the low of channel data length
Byte, nybble are package number, and the 5th to n bytes is data load.
The first acquired heartbeat data packets format is as shown in table 1 below, wherein data channel corresponds to each airborne equipment
Each item data, the hardware connecting interface of physical channel, that is, each airborne equipment and DIU.Event is expressed as event triggering update, that is, has
Data can update at any time.First group of packet module in FPGA is that the data of each data channel of caching distribute different packet starting points
Location is to form heartbeat data packets.
Table 1
Fig. 4 shows the communication process schematic diagram of device according to the ... of the embodiment of the present invention.It is similar with such as Fig. 1,5 tunnels of DIU
Serial line interface is connected to 5 serial data channels of airborne equipment, and each channel is fixed with the period transmission data of 10ms, but each
Channel data length is different, and the data packet of the order caching module reception of FPGA is as shown in Fig. 4 top halfs.The heartbeat week of FPGA
When phase is respectively 10ms and 5ms, the data that CPU is received are as shown in the lower half portion Fig. 4, by the way that the data of caching are passed through coding staff
Formula re-groups package, and channel ID, channel data length wise, channel reception Bale No. are contained in the packet newly organized.FPGA is according to each logical
The data length in road does preliminary caching, gives mono- complete data packet of CPU as possible, mitigates cpu load, and CPU need not be each logical
Track data generates interruption temporarily, and carry out task toggles.
In various embodiments, which may further include：System detectio unit, for right during powering on
The working condition of internal each component is detected, and in the process of work to the linking status of equipment and board whether in place into
Row detection, and can be also used for real-time monitoring system temperature (including temperature of processor, power source temperature and environment temperature etc.)；
Storage unit, for selectively being deposited to the data and handling result of acquisition according to preset instruction or rule
It stores up (for example, in order to carry out test analysis and malfunction elimination)；
Clock unit, for providing reference clock signal for data interface unit；
Debugging module, for carrying out digital simulation input and exporting handling result, to be joined with ground checkout equipment
Close debugging.
Further, the embodiment of the present invention, which also discloses, applies the device of the various embodiments described above in avionics system
The method that communication and processing speed are improved in DIU is combined by using FPGA with CPU, is improving the same of CPU processing speeds
When, the airborne equipment quantity of avionics system processing also accordingly increases.
Specifically, the data that multiple airborne equipment data channel are sent are received by FPGA；To the data from each channel
Carry out temporal cache；The data of caching are packaged according to preset coding mode to obtain the first heartbeat data packets, and root
The first heartbeat data packets are sent to CPU by the SRIO interfaces between FPGA and CPU according to scheduled heart beat cycle；
CPU reads the data in each channel from the first heartbeat data packets；The data in each channel are handled, generation is directed to
The control data of each airborne equipment；Control data are packaged according to preset coding mode, to obtain the second heartbeat data
Packet, and FPGA is sent to according to scheduled second heart beat cycle；
FPGA reads the control data that each airborne equipment is directed in the second heartbeat data packets, is sent to corresponding send and delays
Storing module, and control data are sent to each airborne equipment according to communication protocol corresponding with interface at a predetermined rate.
The above, the only detailed description of the specific embodiment of the invention rather than limitation of the present invention.The relevant technologies
The technical staff in field is not in the case where departing from the principle and range of the present invention, various replacements, modification and the improvement made
It should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of device for improving communication and processing speed in avionics system, which is characterized in that described device includes logical
Cross the FPGA and CPU of the connection of SRIO interfaces；
Wherein, FPGA has：Multiple serial input interfaces, the data sent for receiving multiple airborne equipment data channel；It is more
A order caching module being connect with serial input interface, for carrying out temporal cache to the data from each channel；With it is each
First group of packet module of order caching module connection, for being packaged the data of caching according to preset coding mode to obtain
The first heartbeat data packets are taken, and the first heartbeat data packets are passed through by the SRIO between FPGA and CPU according to scheduled heart beat cycle
Interface is sent to CPU；
CPU has：Module is unpacked, it is each for being read from the first heartbeat data packets from FPGA according to preset coding mode
The data in channel；Data processing module is handled for the data to each channel, generates the control number for each airborne equipment
According to；Second group of packet module packages for that will control data according to preset coding mode, to obtain the second heartbeat data
Packet, and FPGA is sent to according to scheduled second heart beat cycle；
FPGA further comprises：The decoding module being connect with each transmission cache module, for reading in the second heartbeat data packets
For the control data of each airborne equipment, and it is sent to corresponding transmission cache module；Multiple transmission cache modules, connect respectively
It is connected to multiple serial output interfaces and at least one Ethernet interface, and according to communication protocol corresponding with interface with predetermined
Rate to each airborne equipment send control data.
2. the apparatus according to claim 1, which is characterized in that the FPGA further comprises that multiple discrete magnitude inputs connect
Mouthful, the measures of dispersion evidence sent for receiving multiple airborne equipment data channel；Multiple discrete magnitude output interfaces are used for multiple
The measures of dispersion evidence that airborne equipment data channel is sent.
3. the apparatus according to claim 1, which is characterized in that first heart beat cycle is 5ms or 2ms.
4. device according to claim 3, which is characterized in that second heart beat cycle is less than or equal to the first heartbeat week
Phase.
5. the apparatus according to claim 1, which is characterized in that the order caching module and transmission cache module are all made of
Block random access memory BRAM does temporal cache.
6. the apparatus according to claim 1, which is characterized in that the CPU uses P2020NXN2MHC chips, serial defeated
Enter, output interface use ISO3080DWR communication modules, FPGA use XC7A100T-2FGG484I chips.
7. a kind of for improving communication and the method for processing speed in avionics system, which is characterized in that the method includes with
Lower step：
The data sent by the multiple airborne equipment data channel of multiple serial input interfaces of FPGA；It is multiple with it is serial defeated
The order caching module of incoming interface connection carries out temporal cache to the data from each channel；It is connect with each order caching module
First group of packet module the data of caching are packaged according to preset coding mode to obtain the first heartbeat data packets, and root
The first heartbeat data packets are sent to CPU by the SRIO interfaces between FPGA and CPU according to scheduled heart beat cycle；
Unpacking module in CPU reads each channel according to preset coding mode from the first heartbeat data packets from FPGA
Data；Data processing module handles the data in each channel, generates the control data for each airborne equipment；Second group of packet
Module packages data are controlled according to preset coding mode, to obtain the second heartbeat data packets, and according to scheduled the
Two heart beat cycles are sent to FPGA；
In FPGA with it is each send the decoding module that cache module connect and read each airborne set is directed in the second heartbeat data packets
Standby control data, and it is sent to corresponding transmission cache module；Multiple transmission cache modules are respectively connected to multiple serial defeated
Outgoing interface and at least one Ethernet interface, and according to communication protocol corresponding with interface at a predetermined rate to each airborne
Equipment sends control data.
8. the method according to the description of claim 7 is characterized in that further comprising packaging to obtain in first group of packet module
It, should to determine whether to read according to the data update period in each airborne equipment corresponding data channel when taking the first heartbeat data packets
The data in channel.
9. the method according to the description of claim 7 is characterized in that the channel data of each airborne equipment corresponding channel is set as
Identical format, and the first byte is airborne equipment port numbers, the second byte is the high byte of channel data length, third byte
For the low byte of channel data length, nybble is package number, and the 5th to n bytes is data load, and n is less than or equal to
128。
10. the method according to any one of claim 7 to 9, which is characterized in that the method is applied in avionics system
In data interface unit DIU, and DIU is connected to inertial navigation system/Global Satellite Navigation System group by serial communication interface
Close navigation system INS/GNSS, air data computer ADC, aeroengine parameter collector DTC, data logger VMS and comprehensive
Radio system CNS is closed, and synthetical display control cells D U is connected to by Ethernet interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810333245.4A CN108563607A (en) | 2018-04-13 | 2018-04-13 | A kind of device and method for improving communication and processing speed in avionics system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810333245.4A CN108563607A (en) | 2018-04-13 | 2018-04-13 | A kind of device and method for improving communication and processing speed in avionics system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108563607A true CN108563607A (en) | 2018-09-21 |
Family
ID=63535017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810333245.4A Pending CN108563607A (en) | 2018-04-13 | 2018-04-13 | A kind of device and method for improving communication and processing speed in avionics system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108563607A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110309086A (en) * | 2019-05-17 | 2019-10-08 | 全球能源互联网研究院有限公司 | A kind of multichannel low speed mouth and single channel high speed port data interactive method |
| CN110399323A (en) * | 2019-07-31 | 2019-11-01 | 哈尔滨工业大学 | A kind of high-speed information channel based on SRIO |
| CN111651390A (en) * | 2020-05-19 | 2020-09-11 | 北京北方华创微电子装备有限公司 | Serial port data acquisition method, device and equipment of semiconductor equipment |
| CN112231263A (en) * | 2020-10-29 | 2021-01-15 | 山东超越数控电子股份有限公司 | FPGA intermediate layer card extends device |
| CN112685265A (en) * | 2021-03-17 | 2021-04-20 | 中国人民解放军国防科技大学 | Navigation receiver host and standby machine switching and testing method based on bidirectional communication serial port |
| CN112882740A (en) * | 2021-02-05 | 2021-06-01 | 明峰医疗***股份有限公司 | Remote data updating method and system for PET (positron emission tomography) equipment and computer-readable storage medium |
| CN113452628A (en) * | 2021-06-22 | 2021-09-28 | 中国船舶重工集团公司第七0七研究所 | Multifunctional interface adapter and control method thereof |
| CN114168518A (en) * | 2021-11-08 | 2022-03-11 | 陕西千山航空电子有限责任公司 | Airspeed data transmission method and system |
| CN115442351A (en) * | 2022-08-06 | 2022-12-06 | 中国船舶重工集团公司第七一五研究所 | High-speed RS-422 serial port communication module based on FPGA and CPU |
| CN116193000A (en) * | 2023-04-25 | 2023-05-30 | 湖北微源卓越科技有限公司 | FPGA-based intelligent packet rapid forwarding system and forwarding method |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030046380A1 (en) * | 2001-08-14 | 2003-03-06 | Perry Steger | Measurement module interface protocol database and registration system |
| CN101989945A (en) * | 2009-08-05 | 2011-03-23 | 中国商用飞机有限责任公司 | Communication network for aircraft |
| CN102932489A (en) * | 2012-10-28 | 2013-02-13 | 中国电子科技集团公司第十研究所 | Multi-channel ARINC429 bus interface |
| CN107211594B (en) * | 2010-01-25 | 2014-04-09 | 西北工业大学 | Airborne information processing method based on a variety of Avionics data bus |
| CN104391477A (en) * | 2014-11-12 | 2015-03-04 | 上海交通大学 | Drive-control integrated networked intelligent controller |
| CN104699649A (en) * | 2015-03-16 | 2015-06-10 | 中煤科工集团上海研究院 | Multi-branch serial bus interface and data exchange method |
| CN106021172A (en) * | 2016-05-31 | 2016-10-12 | 积成电子股份有限公司 | Data communication method and device |
| CN106713010A (en) * | 2016-11-23 | 2017-05-24 | 北京润科通用技术有限公司 | Communication method and system for avionics network system |
| CN107220154A (en) * | 2017-06-26 | 2017-09-29 | 太仓市同维电子有限公司 | The system for managing multiple address identical two-wire serial interface optical modules |
| CN107844447A (en) * | 2017-09-29 | 2018-03-27 | 北京计算机技术及应用研究所 | Multi-channel serial bus high speed data sampling and processing system and method |
-
2018
- 2018-04-13 CN CN201810333245.4A patent/CN108563607A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030046380A1 (en) * | 2001-08-14 | 2003-03-06 | Perry Steger | Measurement module interface protocol database and registration system |
| CN101989945A (en) * | 2009-08-05 | 2011-03-23 | 中国商用飞机有限责任公司 | Communication network for aircraft |
| CN107211594B (en) * | 2010-01-25 | 2014-04-09 | 西北工业大学 | Airborne information processing method based on a variety of Avionics data bus |
| CN102932489A (en) * | 2012-10-28 | 2013-02-13 | 中国电子科技集团公司第十研究所 | Multi-channel ARINC429 bus interface |
| CN104391477A (en) * | 2014-11-12 | 2015-03-04 | 上海交通大学 | Drive-control integrated networked intelligent controller |
| CN104699649A (en) * | 2015-03-16 | 2015-06-10 | 中煤科工集团上海研究院 | Multi-branch serial bus interface and data exchange method |
| CN106021172A (en) * | 2016-05-31 | 2016-10-12 | 积成电子股份有限公司 | Data communication method and device |
| CN106713010A (en) * | 2016-11-23 | 2017-05-24 | 北京润科通用技术有限公司 | Communication method and system for avionics network system |
| CN107220154A (en) * | 2017-06-26 | 2017-09-29 | 太仓市同维电子有限公司 | The system for managing multiple address identical two-wire serial interface optical modules |
| CN107844447A (en) * | 2017-09-29 | 2018-03-27 | 北京计算机技术及应用研究所 | Multi-channel serial bus high speed data sampling and processing system and method |
Non-Patent Citations (5)
| Title |
|---|
| 吕鹏: "基于SRIO总线的全交换路由设计与实现", 《无线电通信技术》 * |
| 张静: "数字信号处理模块中的串行RapidIO设计", 《火控雷达技术》 * |
| 杜金艳等: "基于Zynq-7000的SRIO高速数据传输设计与实现", 《电子设计工程》 * |
| 陈庆旭等: "一种CPU和FPGA的快速交换数据方法", 《单片机与嵌入式***应用》 * |
| 陈震南: "基于嵌入式的1553B_RS485总线转换设备的研制", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110309086A (en) * | 2019-05-17 | 2019-10-08 | 全球能源互联网研究院有限公司 | A kind of multichannel low speed mouth and single channel high speed port data interactive method |
| CN110399323A (en) * | 2019-07-31 | 2019-11-01 | 哈尔滨工业大学 | A kind of high-speed information channel based on SRIO |
| CN111651390A (en) * | 2020-05-19 | 2020-09-11 | 北京北方华创微电子装备有限公司 | Serial port data acquisition method, device and equipment of semiconductor equipment |
| CN112231263A (en) * | 2020-10-29 | 2021-01-15 | 山东超越数控电子股份有限公司 | FPGA intermediate layer card extends device |
| CN112882740B (en) * | 2021-02-05 | 2023-10-20 | 明峰医疗***股份有限公司 | Remote data updating method and system for PET (polyethylene terephthalate) equipment and computer readable storage medium |
| CN112882740A (en) * | 2021-02-05 | 2021-06-01 | 明峰医疗***股份有限公司 | Remote data updating method and system for PET (positron emission tomography) equipment and computer-readable storage medium |
| CN112685265B (en) * | 2021-03-17 | 2021-06-18 | 中国人民解放军国防科技大学 | Navigation receiver host and standby machine switching and testing method based on bidirectional communication serial port |
| CN112685265A (en) * | 2021-03-17 | 2021-04-20 | 中国人民解放军国防科技大学 | Navigation receiver host and standby machine switching and testing method based on bidirectional communication serial port |
| CN113452628A (en) * | 2021-06-22 | 2021-09-28 | 中国船舶重工集团公司第七0七研究所 | Multifunctional interface adapter and control method thereof |
| CN114168518A (en) * | 2021-11-08 | 2022-03-11 | 陕西千山航空电子有限责任公司 | Airspeed data transmission method and system |
| CN115442351A (en) * | 2022-08-06 | 2022-12-06 | 中国船舶重工集团公司第七一五研究所 | High-speed RS-422 serial port communication module based on FPGA and CPU |
| CN116193000A (en) * | 2023-04-25 | 2023-05-30 | 湖北微源卓越科技有限公司 | FPGA-based intelligent packet rapid forwarding system and forwarding method |
| CN116193000B (en) * | 2023-04-25 | 2023-06-23 | 湖北微源卓越科技有限公司 | FPGA-based intelligent packet rapid forwarding system and forwarding method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108563607A (en) | A kind of device and method for improving communication and processing speed in avionics system | |
| CN110545152B (en) | Upper computer with real-time transmission function in Ethernet and Ethernet system | |
| US9465662B2 (en) | Processor with efficient work queuing | |
| US10135711B2 (en) | Technologies for sideband performance tracing of network traffic | |
| WO1995011554A1 (en) | Error detection and correction apparatus for an asynchronous transfer mode (atm) network device | |
| US20170187587A1 (en) | Technologies for inline network traffic performance tracing | |
| US8885480B2 (en) | Packet priority in a network processor | |
| CN107087306A (en) | The method dispatched for wireless information source | |
| CN106464412B (en) | Sending method, equipment, processing method and the optical switching device of light packet | |
| CN102104427B (en) | FPGA-based nuclear magnetic resonance data communication implementation device and method | |
| CN107888337B (en) | FPGA, FPGA information processing method and accelerating device | |
| US7933276B2 (en) | Dynamic bandwidth allocation processor | |
| CN105207954A (en) | Transmitting data packet and throughput test method and device | |
| CN106230913B (en) | Data processing transmission method and device | |
| US20160373322A1 (en) | Controlling generation of filtered result packets | |
| CN111884952B (en) | Multichannel calculation accelerating equipment based on FPGA | |
| US6754743B2 (en) | Virtual insertion of cells from a secondary source into a FIFO | |
| US20160285767A1 (en) | Technologies for network packet pacing during segmentation operations | |
| Cooke et al. | Characterizing latency overheads in the deployment of FPGA accelerators | |
| CN112653536B (en) | FPGA-based SpaceFibre satellite-borne network node testing system and method | |
| CN105282053A (en) | Method and system for preventing output head-of-line of network exchange chip from blocking | |
| CN105556902B (en) | It is transmitted via the data of communication device | |
| CN110034987A (en) | A kind of CAN communication controller based on FPGA | |
| Janik et al. | LwIP based network solution for MicroBlaze | |
| CN110661689B (en) | Communication device and method for master station and slave station |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180921 |