CN108550579B - Three-dimensional storage and its manufacturing method - Google Patents
Three-dimensional storage and its manufacturing method Download PDFInfo
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- CN108550579B CN108550579B CN201810466713.5A CN201810466713A CN108550579B CN 108550579 B CN108550579 B CN 108550579B CN 201810466713 A CN201810466713 A CN 201810466713A CN 108550579 B CN108550579 B CN 108550579B
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- 238000003860 storage Methods 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 230000004888 barrier function Effects 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 33
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 239000011148 porous material Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 145
- 238000000034 method Methods 0.000 description 18
- 239000010408 film Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 10
- 230000015654 memory Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of three-dimensional storage and its manufacturing method, the three-dimensional storage includes substrate, form edge over the substrate and the alternately stacked conductive layer and insulating layer in direction of the substrate transverse, along the channel hole for running through the alternately stacked conductive layer and insulating layer with the direction of the substrate transverse, and the storage string being formed in the channel hole；The storage string includes the charge storage layer and channel layer sequentially formed along the direction in side wall to the axle center in the channel hole, and the channel layer has p-type doping area, which directly contacts with the substrate, and the substrate is p-substrate.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of three-dimensional memory structure and preparation method thereof, especially
It is a kind of preparation process in channel hole.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and pursue being produced into for lower unit storage unit
This, a variety of different three-dimensional memory structures come into being, such as 3D NOR (3D or non-) flash memory and 3D NAND (3D and non-) dodge
It deposits.
The storage unit of 3D flash memory includes the conductive layer and interlayer insulating film and break-through conductive layer and interlayer of alternating deposit
The vertical-channel hole (hereinafter referred to as channel hole) of insulating layer.In channel hole by PECVD, HDPCVD, UHVCVD, MOCVD,
The techniques such as MBE, ALD are formed with charge storage layer.Charge storage layer includes tunnel insulation layer, electric charge capture layer and charge barrier
Layer.Tunnel insulation layer plays the energy potential barrier layer of charge F-N tunnelling, can be formed by silica.Electric charge capture layer can be with
It is the nitride layer that can capture charge.Electric charge barrier layer, which rises, prevents the charge being stored in electric charge capture layer to be moved to grid
Effect, can be formed by silica.The charge being made of tunnel insulation layer, electric charge capture layer and electric charge barrier layer is deposited below
Reservoir is referred to as ONO layer.
In general, needing for example, by selective epitaxial growth after forming channel hole in channel hole bottom grown monocrystalline silicon
To form bottom selection transistor.
Summary of the invention
The technical problems to be solved by the invention
Using above method manufacture storage unit, due to the epitaxial growth technology not only cost of monocrystalline silicon
Height, and to be difficult to safeguard, therefore improve the manufacturing cost and technology difficulty of three-dimensional storage.
The present invention completes to solve the above-mentioned problems, and its purpose is to provide one kind without in channel hole bottom selectivity
The three-dimensional storage and its manufacturing method of epitaxial growth monocrystalline silicon.
Solve technological means used by technical problem
Three-dimensional storage of the invention includes substrate, and the direction for forming edge and the substrate transverse over the substrate is handed over
For the conductive layer and insulating layer of stacking, run through the alternately stacked conductive layer and insulating layer along with the direction of the substrate transverse
Channel hole, and the storage string being formed in the channel hole；The storage string includes the side wall along the channel hole to axis
The charge storage layer and channel layer that the direction of the heart sequentially forms, the channel layer have p-type doping area, the p-type doping area and institute
It states substrate directly to contact, the substrate is p-substrate.
In an at least embodiment of the invention, the substrate is p-type substrate.
In an at least embodiment of the invention, formed in the p-type substrate far from the side of the storage string
There is peripheral circuit layer.
In an at least embodiment of the invention, it is formed between the peripheral circuit layer and the p-type substrate
Interconnection layer.
In an at least embodiment of the invention, the p-type doping area is for constituting bottom selection transistor.
In an at least embodiment of the invention, the charge storage layer is directly contacted with the substrate.
In an at least embodiment of the invention, the charge storage layer includes that the side wall along the channel hole arrives axle center
Electric charge barrier layer, electric charge capture layer and the tunnel insulation layer that direction sequentially forms, the electric charge barrier layer and the substrate are direct
Contact.
The manufacturing method of three-dimensional storage of the invention includes: offer substrate, and the substrate is p-substrate；In the lining
On bottom formed as the first insulating layer and second insulating layer it is alternately laminated made of laminated body；Formed along with the substrate transverse
At least one channel hole of the laminated body is run through in direction；Charge storage layer and channel layer are sequentially formed in the channel hole；
P-type doping area is formed in the channel layer, which directly contacts with the substrate.
In an at least embodiment of the invention, by thermal diffusion to the channel layer implanted dopant to form the p-type
Doped region.
In an at least embodiment of the invention, by carrying out p-type ion implanting to the channel layer to form the p-type
Doped region.
In an at least embodiment of the invention, the step of forming the channel hole further include: be used for over the substrate
The position for forming channel hole forms etching barrier layer；After forming channel pore structure on the etching barrier layer, the quarter is removed
Lose barrier layer.
In an at least embodiment of the invention, the step of forming the channel hole further include: form first part's stacking
Body forms first part's channel hole in first part's laminated body, and etching resistance is formed in first part's channel hole
Barrier obtains the stepped construction with etching barrier layer；Second part laminated body is formed in the stepped construction, described the
The top in first part's channel hole forms second part channel hole in two part laminated bodies, reveals the etching barrier layer
Out；The etching barrier layer is removed, first part's channel hole and second part channel hole is made to constitute the channel hole.
In an at least embodiment of the invention, the substrate is p-type substrate.
In an at least embodiment of the invention, the p-type doping area is for constituting bottom selection transistor.
In an at least embodiment of the invention, the etching barrier layer is alumina layer.
Invention effect
According to the present invention, using p-substrate, and p-type doping is carried out by the channel layer to channel hole bottom, to replace
It is formed after the CH of channel hole and constitutes bottom selection transistor (BSG) in the channel hole bottom CH selective epitaxial growth monocrystalline silicon, from
And it simplifies technique and reduces costs.
In addition, by being, for example, aluminium oxide forming NO heap prestack to form the position formation in channel hole on the surface of a substrate
The channel hole etching barrier layer of layer, and remove the channel hole etching barrier layer after the completion of channel hole etches, it can prevent from serving as a contrast
Bottom surface because channel hole etch due to become out-of-flatness, be conducive to the film thickness monitoring in subsequent technique, and can eliminate storage unit it
Between individual difference.
In addition, peripheral circuit, interconnection can further be arranged below substrate as substrate by using p-type
The structures such as layer.
Detailed description of the invention
Fig. 1 is the figure for indicating the structure of three-dimensional storage as a reference example.
Fig. 2 is the figure for indicating the structure of three-dimensional storage involved in embodiment of the present invention 1.
Fig. 3 to Fig. 6 is the process flow for indicating the manufacturing method of three-dimensional storage involved in embodiment of the present invention 1
Figure.
Fig. 7 to Fig. 9 is the section for indicating three-dimensional storage involved in embodiment of the present invention 2 in different manufacturing processes
Figure.
Figure 10 is the figure for indicating the structure of three-dimensional storage of variation of the invention.
Specific embodiment
In the following, being carried out based on embodiment and its variation of the attached drawing to three-dimensional storage and its manufacturing method of the invention
Illustrate, identical label is marked to same or equivalent component, position to be illustrated in the various figures.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
It should be noted that in order to simplify herein disclosed statement, to help to one or more inventive embodiments
Understanding, above in the description of the embodiment of the present application, sometimes by various features merger to one embodiment, attached drawing or to it
Description in.But what this disclosure method was not meant to refer in aspect ratio claim required for the application object
Feature is more.In fact, the feature of embodiment will be less than whole features of the single embodiment of above-mentioned disclosure.
Fig. 1 is shown as the structure of the storage unit of the three-dimensional storage of reference example.When manufacturing the storage array, use
Following steps:
(1) substrate 101 is provided；
(2) the alternately laminated grid being for example made of silicon nitride reserves layer 102 and for example by silica structure on substrate 101
At interlayer insulating film 103 come formed NO stack；
(3) NO stacking is performed etching along the direction perpendicular to substrate 101 to form channel hole CH；
(4) bottom selection transistor 201 is formed in the channel hole bottom CH selective epitaxial growth monocrystalline silicon；
(5) barrier layer 202, electric charge capture layer 203, tunnel layer 204 are sequentially formed as electricity along channel hole CH side wall
Lotus accumulation layer；
(6) channel layer 205 is further formed in tunnel layer 204 and 201 surface of bottom selection transistor；
(7) tunnel oxide is filled, top channel layer is formed, and p-type doping is carried out to top channel layer to form drain electrode
206；
(8) removal grid is reserved layer 102 and is replaced with metal layer, as grid layer.
However it needs to form bottom in the channel hole bottom CH selective epitaxial growth monocrystalline silicon using above-mentioned manufacturing method
Selection transistor (BSG).Present inventor is to reduce cost and technology difficulty, is improved the manufacturing method, is mentioned
Following implementation out.
Embodiment 1
Fig. 2 is the figure for indicating the structure of three-dimensional storage involved in embodiment of the present invention 1.
As shown in Fig. 2, be formed on substrate 101a by grid reserve layer 102 and interlayer insulating film 103 it is alternately laminated and
At NO stack.Grid is reserved layer 102 and is for example made of silicon nitride, and interlayer insulating film 103 is for example made of silica.Grid is pre-
It stays layer 102 that can remove in the subsequent process, and replaces with metal as grid layer.Along the direction perpendicular to substrate 101a
(stacking direction) is formed at least one channel hole CH.Grid reserves layer 102 and the material of interlayer insulating film 103 is without being limited thereto,
It is also possible to other insulating materials.
In the CH of channel hole, from side wall to axle center be sequentially formed with barrier layer 202, electric charge capture layer 203, tunnel layer 204, with
And channel layer 205.Drain electrode 206 is formed at the top of the CH of channel hole.204 structure of barrier layer 202, electric charge capture layer 203 and tunnel layer
At charge storage layer.The charge storage layer is directly contacted with substrate 101a.Channel layer 205 is, for example, polysilicon layer.Drain electrode 206
It can such as be formed by carrying out p-type doping to the channel layer 205 at the top of the CH of channel hole.Hereafter also by the structure in the CH of channel hole
Referred to as storage string.
Present embodiment the difference is that, substrate 101a does not use monocrystalline substrate, but p-substrate.Such as it can
To be p-type Si substrate, p-type Ge substrate, p-type SiGe substrate etc..In addition, to the portion positioned at the channel hole bottom CH of channel layer 205
Divide and carried out p-type doping, obtains p-type doping area 2051.The p-type doping area 2051 is connected with substrate 101a.
It is illustrated below with manufacturing method of the Fig. 3 to Fig. 6 to the three-dimensional storage of present embodiment.
Firstly, as shown in figure 3, provide the substrate 101a of p-type, and formed on substrate 101a and 102 (example of layer reserved by grid
Such as the first insulating layer or sacrificial layer) and interlayer insulating film 103 (such as second insulating layer) it is alternately laminated made of NO stack.P-type
Substrate 101a can for example be formed by doping in situ, can also be by carrying out p-type ion implanting or thermal diffusion to substrate
To be formed.Grid is reserved layer 102 and is for example made of silicon nitride, and interlayer insulating film 103 is for example made of silica.Grid reserves layer
102 and the formation process of interlayer insulating film 103 thin film deposition processes, including but not limited to chemical vapour deposition technique can be used
(CVD), one of physical vaporous deposition (PVD), atomic layer deposition method (ALD) and electroplating technology or a variety of combinations.
Then, the NO heap of layer 102 and interlayer insulating film 103 is reserved in grid as shown in figure 4, etching by dry/wet
Stacked on formation at least one channel hole CH (2 being shown in figure, but an only example).
Then, it as shown in figure 5, in the CH of channel hole, is sequentially formed along from the direction in side wall to the axle center of channel hole CH
Barrier layer 202, electric charge capture layer 203, tunnel layer 204 and channel layer 205.Electric charge capture layer 203 plays substantive database
Effect, tunnel layer 204 play the energy potential barrier layer of charge F-N tunnelling, and barrier layer 202, which is risen, to prevent from being stored in electric charge capture layer
Charge in 203 is moved to the effect of grid.Barrier layer 202, electric charge capture layer 203 and tunnel layer 204 constitute charge storage
Layer.Electric charge capture layer 203 can be the nitride layer that can capture charge, and tunnel layer 204 can be formed by silicon oxide layer.Ditch
Channel layer 205 can for example be formed by polysilicon layer.In some embodiments, tunnel oxide, shape are filled into channel layer 205
At separation layer 207.
Then, as shown in fig. 6, carrying out p-type doping to the part of the bottom positioned at channel hole CH of channel layer 205 to be formed
P-type doping area 2051.In present embodiment, thermal expansion is carried out by the part of the bottom positioned at channel hole CH to channel layer 205
It dissipates to inject boron, to obtain p-type doping area 2051.Certainly the present invention is not limited to which, such as can also increase to channel
The channel layer 205 of the hole bottom CH carries out the step of p-type ion implanting.Hereafter the step of, is identical as previous technique, such as can be after
Continue and form drain electrode etc. at top, which is not described herein again.
According to the present embodiment, using p-substrate, and p-type doping area 2051 is further formed to channel layer, makes itself and p
Type substrate is connected.P-type doping area 2051 can replace selective epitaxial growth to constitute bottom in the monocrystalline silicon of the channel hole bottom CH
Portion's selection transistor.Therefore, it can be omitted in the technique of channel hole bottom selective epitaxial growth monocrystalline silicon, so as to simplify work
Skill simultaneously reduces cost.
Embodiment 2
Fig. 7 to Fig. 9 is the section for indicating three-dimensional storage involved in embodiment of the present invention 2 in different manufacturing processes
Figure.
In the embodiment 1, channel hole is formed by etching, therefore after etching, the surface of substrate 101a is as shown in Figure 4
Become out-of-flatness.Since the selective epitaxial growth monocrystalline silicon on substrate 101a, this out-of-flatness can be to not rear by the present invention
Continuous technique impacts, such as is difficult to control the film forming thickness of channel layer, and individual can be generated between each storage unit
Deviation.Also, the presence stacked due to NO, it is difficult to eliminate the out-of-flatness of this substrate surface.
For this purpose, forming NO heap prestack in present embodiment, forming channel on substrate 101a in advance as shown in Figure 7
The position of hole CH forms channel hole etching barrier layer 104.Channel hole etching barrier layer 104, which can choose, has channel hole etching liquid
There are the material of tolerance, such as aluminium oxide.The formation of channel hole etching barrier layer 104 can be using already known processes such as photoetching.
It as an example, such as can be as shown in fig. 7, being initially formed pre- by insulating layer 103 between from level to level and one layer of grid
It stays layer 102 to be laminated laminated body (first part's laminated body), and forms channel hole (first part's channel in the laminated body
Hole) above-mentioned channel hole etching barrier layer 104 is then formed in the channel hole.
It is reserved there is illustrated the insulating layer 103 between from level to level and one layer of grid in the thickness range of layer 102 and forms channel
The structure of hole etching barrier layer 104.But this is only an example, can according to need the number of plies of selection first part's laminated body
With the thickness of channel hole etching barrier layer 104.
Then, the top of structure shown in Fig. 7 forms NO and stacks (second part laminated body) in a manner of same with Fig. 3,
And channel hole (second part channel hole) etching is carried out, obtain structure shown in Fig. 8.Due to channel hole etching barrier layer 104
In the presence of the surface that etching proceeds to channel hole etching barrier layer 104 stops, to protect the substrate 101a of lower section will not be because carving
It loses and is damaged.Channel hole etching barrier layer 104 is removed using wet etching later, exposes the substrate 101a of bottom.Later
Step is identical as Fig. 5 and Fig. 6, and which is not described herein again.
The three-dimensional storage obtained using present embodiment is as shown in figure 9, on the basis of embodiment 1, substrate 101a
Surface it is flat, be conducive to subsequent technique, and the individual difference between storage unit can be eliminated, electric property is more excellent.
Figure 10 shows the structure of three-dimensional storage involved by variation of the invention.The variation and embodiment 1 and
Embodiment 2 the difference is that, substrate 101b uses p-type substrate, other structures and embodiment 1 and embodiment party
Formula 2 is identical.The variation is suitable for being arranged below core memory area the structure, i.e. PUC (Periphery of peripheral circuit
Under Core).In other words, peripheral circuit can be further set in the lower section of substrate 101b, i.e. far from the side of storage string
Layer, further can also be arranged interconnection layer between peripheral circuit layer and substrate 101b, the two is connected.This is because monocrystalline
Silicon can not be formed directly on metal layer, and polysilicon does not have this limitation, such as can directly form polycrystalline on the metal layer
Silicon layer, in the substrate that can be used as core memory area after p-type doping.
The preferred embodiment of the present invention has been described above in detail.It should be appreciated that the present invention is not departing from its broad sense essence
Various embodiments and deformation can be used in the case where mind and range.Those skilled in the art are not necessarily to creative work
It according to the present invention can conceive and make many modifications and variations.Therefore, all those skilled in the art are under this invention's idea
On the basis of existing technology by the available technical solution of logical analysis, reasoning, or a limited experiment, all should belong to
In the protection scope determined by claims of the present invention.
Label declaration
101 substrates
101a substrate
101b substrate
102 grids reserve layer
103 interlayer insulating films
104 channel hole etching barrier layers
201 bottom selection transistors
202 barrier layers
203 electric charge capture layers
204 tunnel layers
205 channel layers
2051 p-type doping areas
206 drain electrodes
207 separation layers
CH channel hole
Claims (14)
1. a kind of three-dimensional storage, which is characterized in that including substrate, form edge over the substrate and the substrate transverse
The alternately stacked conductive layer and insulating layer in direction, along and the substrate transverse direction through the alternately stacked conductive layer and
The channel hole of insulating layer, and the storage string being formed in the channel hole；The storage string includes along the side in the channel hole
The charge storage layer and channel layer that the direction in wall to axle center sequentially forms,
The substrate is p-substrate,
The channel layer has p-type doping area, which directly contacts to constitute bottom selection crystal with the substrate
Pipe.
2. three-dimensional storage as described in claim 1, which is characterized in that
The substrate is p-type substrate.
3. three-dimensional storage as claimed in claim 2, which is characterized in that in the p-type substrate far from the storage
The side of string is formed with peripheral circuit layer.
4. three-dimensional storage as claimed in claim 3, which is characterized in that in the peripheral circuit layer and the p-type
Interconnection layer is formed between substrate.
5. three-dimensional storage as described in claim 1, which is characterized in that
The charge storage layer is directly contacted with the substrate.
6. three-dimensional storage as described in claim 1, which is characterized in that the charge storage layer includes along the channel hole
Electric charge barrier layer, electric charge capture layer and the tunnel insulation layer that the direction in side wall to axle center sequentially forms, the electric charge barrier layer with
The substrate directly contacts.
7. a kind of manufacturing method of three-dimensional storage characterized by comprising
Substrate is provided, the substrate is p-substrate；
Formed over the substrate as the first insulating layer and second insulating layer it is alternately laminated made of laminated body；
It is formed along at least one the channel hole for running through the laminated body with the direction of the substrate transverse；
Charge storage layer and channel layer are sequentially formed in the channel hole；
P-type doping area is formed in the channel layer, which directly contacts brilliant to constitute bottom selection with the substrate
Body pipe.
8. the manufacturing method of three-dimensional storage as claimed in claim 7, which is characterized in that
The p-type doping area is formed to the channel layer implanted dopant by thermal diffusion.
9. the manufacturing method of three-dimensional storage as claimed in claim 7, which is characterized in that
By carrying out p-type ion implanting to the channel layer to form the p-type doping area.
10. the manufacturing method of three-dimensional storage as claimed in claim 7, which is characterized in that
The step of forming the channel hole further include: the position for being used to form channel hole over the substrate forms etch stopper
Layer；
After forming channel pore structure on the etching barrier layer, the etching barrier layer is removed.
11. the manufacturing method of three-dimensional storage as claimed in claim 10, which is characterized in that
The step of forming the channel hole further include: form first part's laminated body, formed in first part's laminated body
First part's channel hole forms etching barrier layer in first part's channel hole, obtains the stacking with etching barrier layer
Structure；
Second part laminated body, first part's channel in the second part laminated body are formed in the stepped construction
The top in hole forms second part channel hole, exposes the etching barrier layer；
The etching barrier layer is removed, first part's channel hole and second part channel hole is made to constitute the channel
Hole.
12. the manufacturing method of three-dimensional storage as claimed in claim 7, which is characterized in that
The substrate is p-type substrate.
13. the manufacturing method of three-dimensional storage as claimed in claim 7, which is characterized in that the charge storage layer with it is described
Substrate directly contacts.
14. the manufacturing method of three-dimensional storage as claimed in claim 10, which is characterized in that
The etching barrier layer is alumina layer.
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| CN201810466713.5A CN108550579B (en) | 2018-05-16 | 2018-05-16 | Three-dimensional storage and its manufacturing method |
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| CN109712990A (en) * | 2019-01-02 | 2019-05-03 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
| CN110379814B (en) * | 2019-06-19 | 2020-06-09 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN111180463A (en) * | 2020-01-03 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106469729A (en) * | 2015-08-19 | 2017-03-01 | 三星电子株式会社 | Nonvolatile memory devices and its Nonvolatile memory system of inclusion |
| CN106847820A (en) * | 2017-03-07 | 2017-06-13 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
| CN107068684A (en) * | 2015-11-10 | 2017-08-18 | 三星电子株式会社 | Vertical Memory Device |
| CN107342291A (en) * | 2016-04-29 | 2017-11-10 | 三星电子株式会社 | Nonvolatile memory devices |
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| CN106887435B (en) * | 2015-12-15 | 2020-01-07 | 北京兆易创新科技股份有限公司 | 3DNand flash memory device and manufacturing method thereof |
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| CN107068684A (en) * | 2015-11-10 | 2017-08-18 | 三星电子株式会社 | Vertical Memory Device |
| CN107342291A (en) * | 2016-04-29 | 2017-11-10 | 三星电子株式会社 | Nonvolatile memory devices |
| CN106847820A (en) * | 2017-03-07 | 2017-06-13 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
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