CN108461405B - 线路载板及其制造方法 - Google Patents
线路载板及其制造方法 Download PDFInfo
- Publication number
- CN108461405B CN108461405B CN201710093630.1A CN201710093630A CN108461405B CN 108461405 B CN108461405 B CN 108461405B CN 201710093630 A CN201710093630 A CN 201710093630A CN 108461405 B CN108461405 B CN 108461405B
- Authority
- CN
- China
- Prior art keywords
- layer
- circuit
- circuit layer
- solder mask
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 50
- 238000005253 cladding Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 6
- 229920001187 thermosetting polymer Polymers 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000003466 welding Methods 0.000 claims 10
- 239000000084 colloidal system Substances 0.000 claims 3
- 238000004806 packaging method and process Methods 0.000 claims 3
- 238000003825 pressing Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 230000004907 flux Effects 0.000 claims 1
- 238000005192 partition Methods 0.000 claims 1
- 230000005611 electricity Effects 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- DEVSOMFAQLZNKR-RJRFIUFISA-N (z)-3-[3-[3,5-bis(trifluoromethyl)phenyl]-1,2,4-triazol-1-yl]-n'-pyrazin-2-ylprop-2-enehydrazide Chemical compound FC(F)(F)C1=CC(C(F)(F)F)=CC(C2=NN(\C=C/C(=O)NNC=3N=CC=NC=3)C=N2)=C1 DEVSOMFAQLZNKR-RJRFIUFISA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710093630.1A CN108461405B (zh) | 2017-02-21 | 2017-02-21 | 线路载板及其制造方法 |
TW106114228A TWI658557B (zh) | 2017-02-21 | 2017-04-28 | 線路載板及其製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710093630.1A CN108461405B (zh) | 2017-02-21 | 2017-02-21 | 线路载板及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108461405A CN108461405A (zh) | 2018-08-28 |
CN108461405B true CN108461405B (zh) | 2020-04-10 |
Family
ID=63228847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710093630.1A Active CN108461405B (zh) | 2017-02-21 | 2017-02-21 | 线路载板及其制造方法 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN108461405B (zh) |
TW (1) | TWI658557B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110265365A (zh) * | 2019-06-12 | 2019-09-20 | 江门建滔电子发展有限公司 | 一种高耐热封装载板 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101789383A (zh) * | 2009-01-23 | 2010-07-28 | 欣兴电子股份有限公司 | 具有凹穴结构的封装基板的制作方法 |
TW201113312A (en) * | 2009-07-06 | 2011-04-16 | Showa Denko Kk | Thermosetting composition for protective film for wiring board |
CN103687344A (zh) * | 2012-09-26 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板制作方法 |
CN104241219A (zh) * | 2014-08-26 | 2014-12-24 | 日月光半导体制造股份有限公司 | 元件嵌入式封装结构和其制造方法 |
CN104244582A (zh) * | 2013-06-13 | 2014-12-24 | 宏启胜精密电子(秦皇岛)有限公司 | 埋入式高密度互连印刷电路板及其制作方法 |
CN104332412A (zh) * | 2013-07-22 | 2015-02-04 | 宏启胜精密电子(秦皇岛)有限公司 | 封装基板、封装结构以及封装基板的制作方法 |
CN106298692A (zh) * | 2015-04-24 | 2017-01-04 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及其制作方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100557540B1 (ko) * | 2004-07-26 | 2006-03-03 | 삼성전기주식회사 | Bga 패키지 기판 및 그 제작 방법 |
-
2017
- 2017-02-21 CN CN201710093630.1A patent/CN108461405B/zh active Active
- 2017-04-28 TW TW106114228A patent/TWI658557B/zh active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101789383A (zh) * | 2009-01-23 | 2010-07-28 | 欣兴电子股份有限公司 | 具有凹穴结构的封装基板的制作方法 |
TW201113312A (en) * | 2009-07-06 | 2011-04-16 | Showa Denko Kk | Thermosetting composition for protective film for wiring board |
CN103687344A (zh) * | 2012-09-26 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板制作方法 |
CN104244582A (zh) * | 2013-06-13 | 2014-12-24 | 宏启胜精密电子(秦皇岛)有限公司 | 埋入式高密度互连印刷电路板及其制作方法 |
CN104332412A (zh) * | 2013-07-22 | 2015-02-04 | 宏启胜精密电子(秦皇岛)有限公司 | 封装基板、封装结构以及封装基板的制作方法 |
CN104241219A (zh) * | 2014-08-26 | 2014-12-24 | 日月光半导体制造股份有限公司 | 元件嵌入式封装结构和其制造方法 |
CN106298692A (zh) * | 2015-04-24 | 2017-01-04 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201832337A (zh) | 2018-09-01 |
TWI658557B (zh) | 2019-05-01 |
CN108461405A (zh) | 2018-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8823187B2 (en) | Semiconductor package, semiconductor package manufacturing method and semiconductor device | |
US7719104B2 (en) | Circuit board structure with embedded semiconductor chip and method for fabricating the same | |
US9258899B2 (en) | Method of fabricating a wiring board | |
KR101168263B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
KR20070078711A (ko) | 배선 기판 및 반도체 장치 | |
KR101070098B1 (ko) | 인쇄회로기판 및 그의 제조 방법 | |
US20130170148A1 (en) | Package carrier and manufacturing method thereof | |
JP2008085089A (ja) | 樹脂配線基板および半導体装置 | |
KR20140021910A (ko) | 코어기판 및 이를 이용한 인쇄회로기판 | |
JP2005150718A (ja) | 超薄型半導体パッケージ及びその製造方法 | |
JPWO2010052942A1 (ja) | 電子部品内蔵配線板及びその製造方法 | |
JP5117270B2 (ja) | 配線基板、半導体装置、ならびに半導体装置の製造方法 | |
US10062623B2 (en) | Semiconductor package substrate, package system using the same and method for manufacturing thereof | |
JP2010093292A (ja) | 回路装置 | |
WO2017006391A1 (ja) | 半導体装置 | |
US7714417B2 (en) | Substrate for mounting semiconductor element and method of manufacturing the same | |
CN108461405B (zh) | 线路载板及其制造方法 | |
US20080000874A1 (en) | Printed wiring board and method of manufacturing the same | |
JP2010135347A (ja) | 配線基板およびその製造方法 | |
JP2007214568A (ja) | 回路基板構造 | |
JP4467540B2 (ja) | 回路装置 | |
JP2007081150A (ja) | 半導体装置及び基板 | |
JPS58134450A (ja) | 半導体装置およびその製造方法 | |
JP2016225398A (ja) | 半導体装置 | |
KR101617023B1 (ko) | 금속 포스트를 구비하는 인쇄회로기판 및 이의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20210707 Address after: 518105 area B, Room 403, block B, Rongchao Binhai building, No. 2021, haixiu Road, n26 District, Haiwang community, Xin'an street, Bao'an District, Shenzhen City, Guangdong Province Patentee after: Liding semiconductor technology (Shenzhen) Co.,Ltd. Patentee after: Qi Ding Technology Qinhuangdao Co.,Ltd. Address before: No.18, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province 066004 Patentee before: Qi Ding Technology Qinhuangdao Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20240206 Address after: SL11, No. 8 Langdong Road, Yanchuan Community, Yanluo Street, Bao'an District, Shenzhen City, Guangdong Province, 518105 Patentee after: Liding semiconductor technology (Shenzhen) Co.,Ltd. Country or region after: China Patentee after: Liding semiconductor technology Qinhuangdao Co.,Ltd. Address before: 518105 area B, Room 403, block B, Rongchao Binhai building, No. 2021, haixiu Road, n26 District, Haiwang community, Xin'an street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: Liding semiconductor technology (Shenzhen) Co.,Ltd. Country or region before: China Patentee before: Qi Ding Technology Qinhuangdao Co.,Ltd. |
|
TR01 | Transfer of patent right |