CN108447873A - 一种阵列基板及制备方法 - Google Patents
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Abstract
本发明提供一种阵列基板及制备方法,所述阵列基板包括:基板;金属遮光层,设置于所述基板表面;多晶硅层,设置于所述金属遮光层之上;其中,所述金属遮光层的面积大于等于所述多晶硅层的面积,且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内,所述多晶硅层的膜层厚度均一。从而避免了所述多晶硅层在所述金属遮光层边缘位置的膜层偏薄的问题,改善了TFT电性,提高了产品良率。
Description
技术领域
本发明涉及阵列基板制造技术领域,尤其涉及一种阵列基板及制备方法。
背景技术
低温多晶硅面板借着其高分辨率,高迁移率,低功耗等诸多优点已成为了目前平板显示产品中的明星产品,被广泛应用在例如苹果、三星、华为、小米、魅族等各大手机及平板电脑上,但由于低温多晶硅器件制程复杂,目前多采用顶栅结构,因此需要在玻璃表面首先成膜一层LS(遮光层金属膜,后面简称为LS),LS位于低温多晶硅面板制程的第一道成膜,位于阵列所有膜层的最下面,传统设计中Poly(多晶硅薄膜,后面简称Poly)都会跨过LS边缘,在LS边缘位置会造成Poly膜层偏薄甚至断掉,导致Poly在LS边缘爬坡位置会发生电性异常,从而引起群亮暗点等不良。
因此,有必要提供一种阵列基板及制备方法,以解决现有技术所存在的问题。
发明内容
本发明提供一种阵列基板及制备方法,能够避免多晶硅薄膜经过金属遮光层边缘,从而避免多晶硅薄膜在金属遮光层边缘膜层偏薄的问题,进而实现改善产品性能,提高产品良率的目的。
为解决上述问题,本发明提供的技术方案如下:
本发明提供一种阵列基板,包括:
基板;
金属遮光层,设置于所述基板表面;
多晶硅层,设置于所述金属遮光层之上;
其中,所述金属遮光层的面积大于等于所述多晶硅层的面积,且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内,所述多晶硅层的膜层厚度均一。
根据本发明一优选实施例,所述金属遮光层的形状为U形。
根据本发明一优选实施例,所述金属遮光层的宽度比所述多晶硅层的宽度宽0.5微米~2微米。
根据本发明一优选实施例,所述金属遮光层的边缘为直线、折线或者弧线。
根据本发明一优选实施例,所述金属遮光层的形状为矩形或梯形。
本发明还提供一种阵列基板的制备方法,所述方法包括以下步骤:
步骤S1、提供一基板,在所述基板上制备间隔分布的金属遮光层;
步骤S2、在所述基板上制备一层与所述金属遮光层厚度相同的缓冲层,进行图案化,将对应所述金属遮光层上方的所述缓冲层去除,形成与所述金属遮光层同平面的缓冲层图案;
步骤S3、在所述缓冲层图案以及所述金属遮光层上再制备一层预设厚度的缓冲层;
步骤S4、在所述缓冲层上对应所述金属遮光层的相应位置制备多晶硅层,其中,形成的所述多晶硅层的膜层厚度均一。
根据本发明一优选实施例,所述金属遮光层的形状为U形或矩形,或者梯形。
根据本发明一优选实施例,所述金属遮光层的边缘为直线、折线或者弧线。
根据本发明一优选实施例,所述多晶硅层在所述基板上的投影落入所述金属遮光层在所述基板上的投影的范围内。
根据本发明一优选实施例,所述多晶硅层在所述基板上的投影与所述金属遮光层在所述基板上的投影不完全重叠。
本发明的有益效果为:相较于现有的阵列基板,本发明的阵列基板通过将金属遮光层设计为U形或者矩形或梯形,形状略大于多晶硅层(1微米即可),使金属遮光层完全遮挡多晶硅层图案,保证了多晶硅层不会跨过金属遮光层的边缘,避免了多晶硅层在金属遮光层边缘位置处的膜层偏薄的问题。或者,将缓冲层分两次制备,第一次制备一层与金属遮光层膜层厚度相同的缓冲层,然后图案化形成与金属遮光层共平面的缓冲层图案,之后在金属遮光层与缓冲层图案形成的平坦的表面上进行第二次缓冲层制备,使得多晶硅层形成在平坦的基底上,从而使多晶硅层的膜层厚度保持均一,进而改善多晶硅层的电性,提高产品良率。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术的阵列基板的结构俯视图;
图2为现有技术的阵列基板的结构截面图;
图3为本发明提供的阵列基板局部的结构俯视图;
图4为本发明提供的阵列基板沿A-A线的截面图;
图5为本发明提供的阵列基板沿B-B线的截面图;
图6为本发明提供的阵列基板结构示意图;
图7为本发明提供的阵列基板的制备方法流程图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明针对现有技术的多晶硅薄膜晶体管,存在多晶硅层在设置时膜层会跨过金属遮光层的边缘,导致多晶硅层在金属遮光层边缘位置处的膜层偏薄甚至断掉,从而导致多晶硅层的电性不良,容易引起群亮暗点等显示异常的技术问题,本实施例能够解决该缺陷。
如图1所示,为现有技术的阵列基板的结构俯视图。所述阵列基板包括:金属遮光层11,所述金属遮光层11为间隔设置的矩形;多晶硅层12,设置于所述金属遮光层11之上;栅极13,绝缘的设置于所述多晶硅层12的上方。其中,所述多晶硅层12在所述金属遮光层11上的投影会经过所述金属遮光层11的边缘。
具体请参照图2所示,为现有技术的阵列基板的结构截面图。其中,金属遮光层21与多晶硅层23之间还设置有缓冲层22,由于所述金属遮光层21的设置会使基板的相应位置形成凸起,造成膜层的不平整,所以后续所述缓冲层22也会在相应位置形成一定的凸起,在所述多晶硅层23制备的时候,由于所述多晶硅层23需要对应跨过所述金属遮光层21的边缘,导致所述多晶硅层23对应所述金属遮光层21的边缘位置处的膜层存在爬坡现象,即该位置的膜层存在一定的倾斜角,使得该位置对应的膜层偏薄甚至断线,造成所述多晶硅层23电性不良,容易引起群亮暗点等显示异常的现象。
如图3所示,为本发明提供的阵列基板局部的结构俯视图。所述阵列基板包括:基板30;金属遮光层31;多晶硅层32,设置于所述金属遮光层31之上;源极33,设置于所述多晶硅层32的源区;漏极34,设置于所述多晶硅层32的漏区;栅极35,绝缘的设置于所述多晶硅层32的上方;其中,所述金属遮光层31的面积大于等于所述多晶硅层32的面积,所述金属遮光层31随所述多晶硅层32分布,所述多晶硅层32与所述源极33以及所述漏极34分布呈U形,优选的,所述金属遮光层31的形状为U形,且所述多晶硅层32在所述金属遮光层31上的投影落入所述金属遮光层31的范围内。所述金属遮光层31的宽度比所述多晶硅层32的宽度宽0.5微米~2微米。优选的,所述金属遮光层31的宽度比所述多晶硅层32的宽度宽1微米。
所述金属遮光层31的边缘为直线、折线或者弧线等,所述金属遮光层31的形状还可以为矩形或梯形等,此处不做限制,只要能完全遮挡所述多晶硅层32即可。
所述阵列基板沿A-A线的截面图如图4所示,金属遮光层41与多晶硅层42绝缘设置,且所述金属遮光层41在A-A方向上的宽度大于所述多晶硅层42,使得所述多晶硅层42在基板上的投影落入所述金属遮光层41在所述基板上的投影,从而使所述多晶硅层42的膜层厚度保持均一。
所述多晶硅薄膜晶体管沿B-B线的截面图如图5所示,金属遮光层51与多晶硅层52绝缘设置,且所述金属遮光层51在B-B方向上的宽度大于所述多晶硅层52,使得所述多晶硅层52在基板上的投影落入所述金属遮光层51在所述基板上的投影,从而使所述多晶硅层52的膜层厚度保持均一。从而改善所述多晶硅层52的电性,提高产品良率。
如图6所示,为本发明提供的阵列基板结构示意图,所述阵列基板包括:基板61;金属遮光层62,间隔的设置于所述基板61表面;缓冲层63,设置于所述金属遮光层62与所述基板61表面;多晶硅层64,对应所述金属遮光层62设置于所述缓冲层63表面;源极65,设置于所述多晶硅层64的源区;漏极66,设置于所述多晶硅层64的漏区;栅极67,绝缘设置于所述多晶硅层64的上方;其中,所述金属遮光层62的面积大于等于所述多晶硅层64的面积,且所述多晶硅层64在所述金属遮光层62上的投影落入所述金属遮光层62的范围内。优选的,所述金属遮光层62的形状为U形。所述金属遮光层62的形状还可以为矩形或梯形等形状。其中,所述金属遮光层62的宽度比所述多晶硅层64的宽度宽0.5微米~2微米,优选为1微米。本实施例的所述阵列基板的所述多晶硅层64的膜层厚度保持均一,从而改善所述多晶硅层64的电性,提高产品良率。
本发明还提供一种阵列基板的制备方法,如图7所示,为本发明提供的阵列基板的制备方法流程图,所述方法包括以下步骤:
步骤S1、提供一基板,在所述基板上制备间隔分布的金属遮光层;
步骤S2、在所述基板上制备一层与所述金属遮光层厚度相同的缓冲层,进行图案化,将对应所述金属遮光层上方的所述缓冲层去除,形成与所述金属遮光层同平面的缓冲层图案;
步骤S3、在所述缓冲层图案以及所述金属遮光层上再制备一层预设厚度的缓冲层;
步骤S4、在所述缓冲层上对应所述金属遮光层的相应位置制备多晶硅层,其中,形成的所述多晶硅层的膜层厚度均一。
具体地,先提供一基板,在所述基板上形成间隔设置的金属遮光层,所述金属遮光层的形状为U形或矩形,或者梯形。所述金属遮光层的边缘为直线、折线或者弧线等形状。之后在所述基板上进行两次缓冲层的制备,首先在所述基板上制备一层与所述金属遮光层的膜层厚度相同的缓冲层,对该缓冲层进行图案化,刻蚀掉对应所述金属遮光层上方的所述缓冲层,形成与所述金属遮光层共平面的缓冲层图案;之后进行缓冲层的第二次制备,在所述金属遮光层与所述缓冲层图案形成的平坦的表面上再制备一层预设厚度的缓冲层,由此,在所述基板上就形成了表面平坦的缓冲层,在所述缓冲层对应所述金属遮光层的位置制备多晶硅层。因为是以平坦的所述缓冲层作为所述多晶硅层的基底,所以所述多晶硅层的膜层厚度能够保持均一,从而改善了所述多晶硅层的电性。因此,所述多晶硅层在所述基板上的投影可以落入所述金属遮光层在所述基板上的投影的范围内;或者,所述多晶硅层在所述基板上的投影与所述金属遮光层在所述基板上的投影也可以不完全重叠。采用该方法制备的所述阵列基板,对所述金属遮光层以及所述多晶硅层的大小形状不做限制。
相较于现有的阵列基板,本发明的阵列基板通过将金属遮光层设计为U形或者矩形或梯形,形状略大于多晶硅层(1微米即可),使金属遮光层完全遮挡多晶硅层图案,保证了多晶硅层不会跨过金属遮光层的边缘,避免了多晶硅层在金属遮光层边缘位置处的膜层偏薄的问题。或者,将缓冲层分两次制备,第一次制备一层与金属遮光层膜层厚度相同的缓冲层,然后图案化形成与金属遮光层共平面的缓冲层图案,之后在金属遮光层与缓冲层图案形成的平坦的表面上进行第二次缓冲层制备,使得多晶硅层形成在平坦的基底上,从而使多晶硅层的膜层厚度保持均一,进而改善多晶硅层的电性,提高产品良率。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种阵列基板,其特征在于,包括:
基板;
金属遮光层,设置于所述基板表面;
多晶硅层,设置于所述金属遮光层之上;
其中,所述金属遮光层的面积大于等于所述多晶硅层的面积,且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内。
2.根据权利要求1所述的阵列基板,其特征在于,所述金属遮光层的形状为U形。
3.根据权利要求1所述的阵列基板,其特征在于,所述金属遮光层的宽度比所述多晶硅层的宽度宽0.5微米~2微米。
4.根据权利要求1所述的阵列基板,其特征在于,所述金属遮光层的边缘为直线、折线或者弧线。
5.根据权利要求1所述的阵列基板,其特征在于,所述金属遮光层的形状为矩形或梯形。
6.一种阵列基板的制备方法,其特征在于,所述方法包括以下步骤:
步骤S 1、提供一基板,在所述基板上制备间隔分布的金属遮光层;
步骤S2、在所述基板上制备一层与所述金属遮光层厚度相同的缓冲层,进行图案化,将对应所述金属遮光层上方的所述缓冲层去除,形成与所述金属遮光层同平面的缓冲层图案;
步骤S3、在所述缓冲层图案以及所述金属遮光层上再制备一层预设厚度的缓冲层;
步骤S4、在所述缓冲层上对应所述金属遮光层的相应位置制备多晶硅层,其中,形成的所述多晶硅层的膜层厚度均一。
7.根据权利要求6所述的制备方法,其特征在于,所述金属遮光层的形状为U形或矩形,或者梯形。
8.根据权利要求6所述的制备方法,其特征在于,所述金属遮光层的边缘为直线、折线或者弧线。
9.根据权利要求6所述的制备方法,其特征在于,所述多晶硅层在所述基板上的投影落入所述金属遮光层在所述基板上的投影的范围内。
10.根据权利要求6所述的制备方法,其特征在于,所述多晶硅层在所述基板上的投影与所述金属遮光层在所述基板上的投影不完全重叠。
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Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103018989A (zh) * | 2012-12-07 | 2013-04-03 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法和液晶显示装置 |
CN103268855A (zh) * | 2012-12-19 | 2013-08-28 | 上海天马微电子有限公司 | 多晶硅形成方法、tft阵列基板制造方法及显示装置 |
CN103474430A (zh) * | 2012-06-07 | 2013-12-25 | 群康科技(深圳)有限公司 | 薄膜晶体管基板及其制作方法以及显示器 |
CN103531640A (zh) * | 2013-11-01 | 2014-01-22 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及其制造方法和显示装置 |
CN104157696A (zh) * | 2014-07-16 | 2014-11-19 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及制备方法、阵列基板、液晶显示装置 |
CN104678643A (zh) * | 2015-03-27 | 2015-06-03 | 合肥京东方光电科技有限公司 | 显示基板及显示面板的制作方法 |
CN105093659A (zh) * | 2015-09-07 | 2015-11-25 | 武汉华星光电技术有限公司 | 一种液晶显示面板及其制造方法 |
CN105093755A (zh) * | 2015-08-28 | 2015-11-25 | 深圳市华星光电技术有限公司 | 薄膜晶体管阵列基板及液晶显示面板 |
CN106206456A (zh) * | 2016-08-10 | 2016-12-07 | 京东方科技集团股份有限公司 | 一种阵列基板的制作方法、阵列基板及显示装置 |
CN106653695A (zh) * | 2016-12-27 | 2017-05-10 | 武汉华星光电技术有限公司 | 一种低温多晶硅阵列基板及其制作方法 |
CN107248373A (zh) * | 2017-06-08 | 2017-10-13 | 京东方科技集团股份有限公司 | 一种显示面板及制作方法、显示装置 |
CN107302032A (zh) * | 2017-06-19 | 2017-10-27 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制作方法、阵列基板、显示面板 |
CN107331668A (zh) * | 2017-06-09 | 2017-11-07 | 武汉华星光电技术有限公司 | 一种tft基板及制作方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004318067A (ja) * | 2003-03-31 | 2004-11-11 | Toshiba Matsushita Display Technology Co Ltd | 画像表示装置およびその製造方法 |
US7123314B2 (en) * | 2003-07-11 | 2006-10-17 | Nec Corporation | Thin-film transistor with set trap level densities, and method of manufactures |
CN105140298B (zh) * | 2015-09-24 | 2018-08-07 | 武汉华星光电技术有限公司 | 薄膜晶体管和阵列基板 |
CN105679765A (zh) * | 2016-01-12 | 2016-06-15 | 武汉华星光电技术有限公司 | Tft阵列基板结构 |
CN106206622B (zh) * | 2016-09-23 | 2019-05-10 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置 |
-
2018
- 2018-03-19 CN CN201810223632.2A patent/CN108447873A/zh active Pending
- 2018-04-12 WO PCT/CN2018/082734 patent/WO2019178904A1/zh active Application Filing
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103474430A (zh) * | 2012-06-07 | 2013-12-25 | 群康科技(深圳)有限公司 | 薄膜晶体管基板及其制作方法以及显示器 |
CN103018989A (zh) * | 2012-12-07 | 2013-04-03 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法和液晶显示装置 |
CN103268855A (zh) * | 2012-12-19 | 2013-08-28 | 上海天马微电子有限公司 | 多晶硅形成方法、tft阵列基板制造方法及显示装置 |
CN103531640A (zh) * | 2013-11-01 | 2014-01-22 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及其制造方法和显示装置 |
CN104157696A (zh) * | 2014-07-16 | 2014-11-19 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及制备方法、阵列基板、液晶显示装置 |
CN104678643A (zh) * | 2015-03-27 | 2015-06-03 | 合肥京东方光电科技有限公司 | 显示基板及显示面板的制作方法 |
CN105093755A (zh) * | 2015-08-28 | 2015-11-25 | 深圳市华星光电技术有限公司 | 薄膜晶体管阵列基板及液晶显示面板 |
CN105093659A (zh) * | 2015-09-07 | 2015-11-25 | 武汉华星光电技术有限公司 | 一种液晶显示面板及其制造方法 |
CN106206456A (zh) * | 2016-08-10 | 2016-12-07 | 京东方科技集团股份有限公司 | 一种阵列基板的制作方法、阵列基板及显示装置 |
CN106653695A (zh) * | 2016-12-27 | 2017-05-10 | 武汉华星光电技术有限公司 | 一种低温多晶硅阵列基板及其制作方法 |
CN107248373A (zh) * | 2017-06-08 | 2017-10-13 | 京东方科技集团股份有限公司 | 一种显示面板及制作方法、显示装置 |
CN107331668A (zh) * | 2017-06-09 | 2017-11-07 | 武汉华星光电技术有限公司 | 一种tft基板及制作方法 |
CN107302032A (zh) * | 2017-06-19 | 2017-10-27 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制作方法、阵列基板、显示面板 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230113781A1 (en) * | 2021-10-13 | 2023-04-13 | AUO Corporation | Transparent display panel |
US11916084B2 (en) * | 2021-10-13 | 2024-02-27 | AUO Corporation | Transparent display panel |
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