CN108447848A - The preparation method of antifuse device - Google Patents

Abstract

The preparation method of antifuse device, is related to semiconductor technology, and the present invention includes the following steps：A, polycrystalline silicon deposit；B, N+ injections are carried out to the poly on place, forms antifuse bottom crown；C, the deposit silicon nitride layer on poly, as antifuse medium；D, etching is synchronized to polysilicon and silicon nitride；E, the extra silicon nitride on polysilicon is removed；F, contact tungsten plug is formed；G, it deposited metal and etches.The invention has the advantages that with standard CMOS process highly compatible, and there is excellent performance, there is good economy.

Description

The preparation method of antifuse device

Technical field

The present invention relates to semiconductor technologies.

Background technology

Anti-fuse cell is a kind of semiconductor devices being made of two conductive layers and the insulating medium layer between.Not When programming, conductive layer is since insulating medium layer separates, the open circuit of antifuse both ends.In the case of plus high-pressure (when programming), absolutely Edge medium is punctured by high electric field, forms conductive channel, and the resistance of antifuse is minimum at this time, is formed and is electrically connected between the conductive layer of both sides It connects, antifuse short circuit (being melt through).This process that is melt through is physically disposable, permanent, irreversible, therefore this Structure has natural immunity to ionising radiation, has high anti-radiation performance, and special with good high- and low-temperature resistance Property.Logical zero and logical one are respectively represented using antifuse switching two states, antifuse read-only memory can be designed The antifuse devices such as PROM and anti-fuse FPGA.These antifuse devices have the advantages that highly anti-radiation, highly reliable, are very suitable for Applied to space flight, return in the radiation environments such as satellite, space safety field, Space Target Surveillance aspect, remote sensing satellite system.

Industrial quarters mainly applies following three kinds of anti-fuse structures at present：1. polysilicon/dielectric layer/N+ diffusion layer structures； 2.MTM structures；3.MOS grid oxygen type structures.They have their own characteristics.

1. polysilicon/dielectric layer/N+ diffusion layer structures

Polysilicon and N+ diffusion layers are pole plate, and dielectric opens two electrode isolations.Dielectric layer is usually silica-nitrogen SiClx-silica (ONO).ONO dielectrics include the SiO of bottom thermal oxide growth₂Layer, intermediate LPCVD (low pressure chemical gas Mutually deposit) Si₃N₄The SiO of layer and a top layer thermal oxide₂Layer.

Due to Si₃N₄Dielectric constant be more than SiO₂So that this ONO structure is dense, excellent in terms of forming resistance In the SiO of same thickness single layer₂, there is higher dielectric constant and lower leakage current.ONO layer thickness ordinarily is about Unprogrammed antifuse shows as capacitance characteristic, and impedance can reach Ω grades of G, can be effectively isolated electrode.When to anti-fuse cell When programming, the ONO antifuse average resistances after program current 5mA breakdown are about 500 Ω.

Compared to common CMOS process, ONO antifuse technique must additionally increase by three reticles, make N-type antifuse and expand It dissipates and antifuse polycrystalline needs two additional versions, make programming high voltage transistor thick grating oxide layer and need a reticle.

2.MTM structures

MTM (Metal-To-Metal) structure is medium/metal layer/metal structure.The generally micro- non-crystalline silicon of dielectric layer.Metal Electrode is usually multilayered structure, is metal connecting layer/metal barrier/metal electrode, metal connecting layer Ti, Cr, metal electricity Extremely 4000~6000 angstroms Al, Pt, W, Mo or its silicide or polysilicon, the TiW or TiN that metal barrier is 100 angstroms, The alloying component of middle TiW is 10%Ti and 90%W.

Mainly there are two advantages relative to ONO antifuse for MTM antifuse：First, MTM antifuse are directly and interconnection metal layer It is connected, and there are one parasitic capacitances to exist for meeting between ONO antifuse and wiring layer；Second, MTM antifuse are attached directly to low resistance Metal layer makes it be easier to reduce the conducting resistance of antifuse using the program current of bigger.

Non-crystalline silicon antifuse technique need to increase by two processing steps and improve a technique on the basis of standard CMOS process Step.Improved processing step be tungsten plug flatening process because MTM antifuse need it is more flat than stand CMOS Surface.Increased processing step is the deposition and etching of non-crystalline silicon.

3.MOS grid oxygen type anti-fuse structures

Mos gate oxygen type antifuse is to form antifuse using metal-oxide-semiconductor gate oxide medium the most.Gate oxide breakdown Before, grid and source-drain electrode isolation show as capacitance characteristic；By applying high-voltage breakdown gate oxide, grid and source-drain electrode to grid Breakdown shows as resistance characteristic.With the development of semiconductor integrated circuit technique, the gate oxide thickness of metal-oxide-semiconductor is gradually reduced, Its breakdown voltage is gradually lowered.It is 7nm from the gate oxide thickness of 0.35 μm of technique, arrives the gate oxide of current 22nm techniques Only several atomic thickness, and device operating voltages are only reduced to 1V or so from 5V, this makes gate oxide be directly used as instead Fuse cell is possibly realized.Simultaneously as the commercial CMOS technology using standard manufactures, additional mask and special is not needed Technique has very strong autgmentability, the disposable programmable memory of high density, low cost, high reliability may be implemented.

But gate oxide antifuse due to using gate oxide medium the most, deposit resistance after programming it is too big (>1k Ω), and The dispersion of resistance very big (1k-100k Ω) the problems such as, considerable restraint is received in application range, such as can not be by gate oxide Antifuse is directly used in FPGA.

As seen from the above, polysilicon/dielectric layer/N+ diffusion layers structure and MTM structure antifuse function admirables, but with CMOS technology is incompatible, and economy and scalability are poor.Mos gate oxygen type structure antifuse is compatible with CMOS technology, but performance It is very poor.

Invention content

The technical problem to be solved by the present invention is to propose a kind of and standard CMOS process highly compatible, and with excellent The anti-fuse structures and its implementation of performance.

The present invention solve the technical problem the technical solution adopted is that, the preparation method of antifuse device, feature exists In including the following steps：

A, polycrystalline silicon deposit；

B, N+ injections are carried out to the poly on place, forms antifuse bottom crown；

C, the deposit silicon nitride layer on poly, as antifuse medium；

D, etching is synchronized to polysilicon and silicon nitride；

E, the extra silicon nitride on polysilicon is removed；

F, contact tungsten plug is formed；

G, it deposited metal and etches.

The invention has the advantages that with standard CMOS process highly compatible, and there is excellent performance, there is good warp Ji property.

Description of the drawings

Fig. 1 is the antifuse device structural profile illustration of the present invention.

Fig. 2 is using the diagrammatic cross-section after standard CMOS process polysilicon deposition process.

Fig. 3 is the diagrammatic cross-section carried out to the POLY on place after the completion of N+ injections.

Fig. 4 is the silicon chip sectional view after deposit silicon nitride.

Fig. 5 is the silicon chip sectional view after polysilicon etching synchronous with silicon nitride,

Fig. 6 is NMOS tube layout design schematic diagram.

Fig. 7 is the sectional view after the extra silicon nitride removed on N metal-oxide-semiconductor polysilicon gates.

Fig. 8 is PMOS tube layout design schematic diagram.

Fig. 9 is the sectional view after the extra silicon nitride removed on P metal-oxide-semiconductor polysilicon gates.

Figure 10 is to contact the sectional view after tungsten plug is formed.

Figure 11 is the sectional view after Metal deposition and etching.

Specific implementation mode

The present invention proposes a kind of with standard CMOS process highly compatible, and anti-fuse structures with excellent performance and in fact It is named as MIP (metal-dielectric-polycrystalline) type antifuse by existing method, the present invention.Fig. 1 is the cross-section structure of MIP antifuse, It is located at the place on silicon wafer, and lower electrode is made of polysilicon, middle layer be insulating medium layer (including silicon nitride, silica, High K dielectric etc.), power on extremely tungsten plug and its connection metal (metal layer 1).

All using the technology of standard CMOS process highly compatible, lift dielectric layer below is the manufacturing process of MIP antifuse It is described for silicon nitride, the case where other media, other than the technique different from of somatomedin, remaining processing step one It causes.

The manufacturing process steps of MIP antifuse are：

After the completion of the polycrystalline silicon deposit of standard CMOS process, silicon chip sectional view is as shown in Figure 2 (at this time under MIP antifuse The poly of electrode has been formed, and sees the poly layers in Fig. 2 on STI).Need to increase by 1,2,3,4 following processes later to form MIP Lower electrode, the dielectric layer of antifuse, but without additional development technology and increase release.Common CMOS process flow is returned to later In, the electrode of metal of MIP antifuse is formed using common CMOS process.

1, referring to Fig. 3, polysilicon N+ injections.

N+ injections are carried out to the poly on place using the reticle of place, increase the electric conductivity of poly, it is anti-to form MIP The bottom crown of fuse.

2, referring to Fig. 4, silicon nitride deposition

LPCVD (low-pressure chemical vapor phase deposition) is used to deposit one layer of thin silicon nitride layer as the medium of MIP antifuse.This step Silicon chip sectional view after the completion of rapid is as shown in Figure 4.(note：The silicon nitride layer thickness of diagram is the needs clearly showed that, actual Silicon nitride layer thickness only has tens angstroms.)

3, polysilicon etching synchronous with silicon nitride

Using polysilicon reticle, etching is synchronized to polysilicon and silicon nitride, silicon chip sectional view such as Fig. 5 after the completion It is shown.

4, remove the extra silicon nitride on polysilicon layer

4.1 utilize the extra silicon nitride on N+ illumination versions removal N metal-oxide-semiconductor polysilicon gates

It is clean in order to achieve the purpose that remove the extra silicon nitride on N metal-oxide-semiconductor polysilicon gates using N+ illumination version, it is setting When counting NMOS tube domain, polysilicon gate is completely covered in the areas Ying Jiang N+, as shown in Figure 6.

The sectional view removed after the extra silicon nitride on N metal-oxide-semiconductor polysilicon gates is as shown in Figure 7.

4.2 utilize the extra silicon nitride on P+ illumination versions removal PMOS tube polysilicon gate

It is clean in order to achieve the purpose that remove the extra silicon nitride on PMOS tube polysilicon gate using P+ illumination version, it is designing When PMOS tube domain, the areas Ying Jiang P+ cover polysilicon gate, as shown in Figure 8.

The sectional view removed after the extra silicon nitride on P metal-oxide-semiconductor polysilicon gates is as shown in Figure 9.

The dielectric layer of MIP antifuse has been formed at this time, and following technique returns to standard CMOS process flow, carries out N+, P+ The techniques such as injection, and produce the electrode of metal of MIP antifuse.

5, contact tungsten plug is formed

Contact tungsten plug is formed using standard CMOS process.Section after the completion of this step is as shown in Figure 10：

6, metal accumulation simultaneously etches

Using standard CMOS process accumulation metal and after etching, as shown in figure 11：

So far, the three-decker of MIP antifuse all makes and finishes.

Claims (1)

1. the preparation method of antifuse device, which is characterized in that include the following steps：

A, polycrystalline silicon deposit；

B, N+ injections are carried out to the poly on place, forms antifuse bottom crown；

C, the deposit silicon nitride layer on poly, as antifuse medium；

D, etching is synchronized to polysilicon and silicon nitride；

E, the extra silicon nitride on polysilicon is removed；

F, contact tungsten plug is formed；

G, it deposited metal and etches.