CN108447767A - 一种制造半导体结构的方法 - Google Patents
一种制造半导体结构的方法 Download PDFInfo
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- CN108447767A CN108447767A CN201711039533.0A CN201711039533A CN108447767A CN 108447767 A CN108447767 A CN 108447767A CN 201711039533 A CN201711039533 A CN 201711039533A CN 108447767 A CN108447767 A CN 108447767A
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Abstract
一种制造半导体结构的方法,包括形成导电结构于第一钝化层上方,沉积第一介电膜连续地位于导电结构上方,沉积第二介电膜连续地位于第一介电膜上方,以及沉积第三介电膜于第二介电膜上方。一部分的第三介电膜是与一部分的第一介电膜接触。
Description
技术领域
本揭示是关于一种制造半导体结构的方法,特别是关于一种制造具有接触垫的半导体结构的方法。
背景技术
在集成电路(IC)装置的制造制程完成后,接触垫形成于最上方的金属间介电层(inter metal dielectric,IMD)的上方,并用于导线接合(wire bonding)或覆晶接合(flip-chip bonding)。在覆晶尺度(flip-chip scale)封装制程中,形成导电凸块(conductive bump),以建立介于接触垫与基板或封装的引线框架之间的电性连接。为了满足增加功能性与降低生产成本的市场需求,通过形成后钝化互连结构(post passivationinterconnect,PPI)及/或凸块下金属层结构(under bump metallurgy,UBM)于接触垫上方,引入晶圆级晶片尺度(wafer-level chip scale packaging,WLCSP)封装制程。在某些情况下,将晶片切割成晶粒,以接合至印刷电路板。
发明内容
本揭示提供了一种制造半导体结构的方法,此方法包括:形成导电结构于第一钝化层的上方;沉积第一介电膜,连续地位于导电结构上方;沉积第二介电膜,连续地位于第一介电膜上方;以及沉积第三介电膜于第二介电膜上方,其中一部分的第三介电膜是接触一部分的第一介电膜。
附图说明
当结合附图阅读时,自以下详细描述可以最佳地理解本揭示的态样。应当注意,根据工业中标准实务,各特征未按比例绘制。事实上,为论述的清楚性,各特征的尺寸可任意地增加或缩减。
图1是根据一个或多个实施方式的半导体装置的横截面图;
图2是根据一个或多个实施方式的半导体装置的制造方法的流程图;
图3A至图3D是根据一个或多个实施方式,半导体装置在各制造阶段的横截面图;
图4是根据一个或多个实施方式的半导体装置的横截面图。
具体实施方式
以下揭示提供许多不同实施方式或实施例,用于实现本揭示的不同特征。以下叙述部件、数值、操作、材料、配置或其类似的具体实施例,以简化本揭示。这些当然仅为实施例,并且不是意欲作为限制。亦考量了其他部件、数值、操作、材料、配置或其类似。举例而言,在随后的叙述中,第一特征在第二特征上方或在第二特征上的形成,可包括第一特征及第二特征形成为直接接触的实施方式,亦可包括有另一特征可形成在第一特征及第二特征之间,以使得第一特征及第二特征可不直接接触的实施方式。另外,本揭示在各实施例中可重复参考标号及/或字母。此重复是为了简化及清楚的目的,且本身不指示所论述各实施方式及/或配置之间的关系。
此外,本文中可使用空间性相对用词,例如“下方(beneath)”、“低于(below)”、“下(lower)”、“之上(above)”、“上(upper)”及其类似用语,是利于叙述附图中一个元件或特征与另一个元件或特征的关系。这些空间性相对用词本意上涵盖除了图中所绘示的位向之外,也涵盖使用或操作中的装置的不同位向。
集成电路(IC)结构包括具有例如晶体管与二极管的主动元件与例如电容器与电阻器的被动元件的半导体晶粒,初始时为彼此隔离,随后通过互连结构而彼此电性耦合及/或至另一集成电路结构,以建立功能性电路。第一钝化层形成于互连结构上方,以保护互连结构不受损伤。多个接触垫形成于第一钝化层上方,并受到第二钝化层的覆盖,以保护接触垫。一个或多个用于减少在封装制程时所引入的失配应力(stress mismatch)的应力缓冲层设置于第二钝化层上方。
在一些实施方式中,第二钝化层包括至少四个绝缘膜,依序形成于接触垫的顶表面上。第二绝缘膜是不连续地配置于第一绝缘膜与第三绝缘膜之间。在接触垫具有梯形剖面,并且顶部分具有的宽度小于底部分的一些实施方式中,第二钝化层是沿着接触垫的梯形剖面。在这样的方式中,相邻的接触垫之间的空间是不具有孔洞(void)的,这是因为第二钝化层不具有从接触垫的顶部分向外延伸的悬突(overhang)。因此,在后续的生产制程时,可以保护第一钝化层不受到所使用的酸性溶液。相较于其他方式,第二钝化层协助减少缺陷,例如应力破裂(stress cracking)及/或接触垫的底部分的剥离(peeling),从而改善装置可靠度与产量。
图1是根据一个或多个实施方式的半导体装置100的横截面图。半导体装置100包括金属间介电层110(Inter Metal Dielectric,IMD)、第一钝化层120、至少一接触垫130与第二钝化层140。金属间介电层110是堆叠于基板上的多个金属间介电层的最上方层。金属间介电层110经配置以将一个互连结构与另一个互连结构在实体上与电性上隔绝,此互连结构例如导电线路或通路插塞(via plug)。在一些实施方式中,金属间介电层110包括硅氧化物(SiOx,x等于或小于2)。在一些实施方式中,金属间介电层110包括低介电常数(低-κ)介电质(相较于二氧化硅),例如磷酸硅酸盐玻璃(phophosilicate glass,PSG)、硼硅酸盐玻璃(borosilicate glass,BSG)、硼磷酸硅酸盐玻璃(borophosphosilicate glass,BPSG)、氟化硅酸盐玻璃(fluorinated silicate glass,FSG)、碳氧化硅(siliconoxycarbide,SiOxCy)、四乙氧基硅烷(tetraethyl orthosilicate,TEOS)、其一组合或另一合适的材料。最上方的导电线路112是位于金属间介电层110内。在一些实施方式中,导电线路112连接至主动装置或一部分的被动装置。在一些实施方式中,导电线路112是虚拟图案或防护密封圈(guard seal ring structure)的一部分。在一些实施方式中,导电线路112包括铜、铝、钨、钛、其一组合或另一合适的材料。
第一钝化层120是位于金属间介电层110上方,并位于接触垫130与第二钝化层140下方。这意即第一钝化层120的第一部分是和接触垫130直接接触,而第一钝化层120的第二部分是和第二钝化层140直接接触。在一些实施方式中,第一钝化层120的第一部分的顶表面与第一钝化层120的第二部分的顶表面之间的厚度T10为约100nm至约300nm。在一些情况下,较大的差距增加了充填相邻的接触垫130之间的空间的困难度。在一些实施方式中,第一钝化层120经配置以保护互连结构不受损害与污染。在一些实施方式中,第一钝化层120进一步提供保护,以协助防止或减少位于其下的电子装置的水气、机械或辐射损伤。在一些实施方式中,第一钝化层120的厚度为约500nm至约1200nm。在一些情况下,较厚的第一钝化层120增加了生产成本,且没有显著的效益。在一些情况下,较薄的第一钝化层120对底下的结构所提供的保护不足。在一些实施方式中,第一钝化层120包括介电材料,例如硅氧化物、无掺杂硅酸盐玻璃(undoped silicate glass,USG)、硅氮化物、氮氧化硅、聚合物、其一组合或另一合适的材料。在一些实施方式中,第一钝化层120包括单一材料。在一些实施方式中,第一钝化层120包括多个材料。
接触垫130是位于第一钝化层120上方,亦称为接合垫(bonding pad)或输入/输出垫(input/output,I/O)。在一些实施方式中,通路插塞(via plug)132是位于第一钝化层120内,并经配置以电性连接至接触垫130与导电线路112。在一些实施方式中,通路插塞132是接触垫130的一部分。这意即接触垫130的底部分延伸通过第一钝化层120,而接触垫130的上部分延伸于第一钝化层120上方。在一些实施方式中,接触垫130包括铝、铜、铝合金、铜合金、其一组合或另一合适的导电材料。在一些实施方式中,接触垫130包括与导电线路112相同的材料。在一些实施方式中,接触垫130包括与导电线路112不同的材料。
第二钝化层140是位于接触垫130与第一钝化层120上方,以保护接触垫130不受损伤。在一些实施方式中,第二钝化层140经配置以吸收或释放由切割与封装制程所导致的热应力及/或机械应力。第二钝化层140包括第一绝缘膜142、第二绝缘膜144、第三绝缘膜146及第四绝缘膜148。在各个实施方式中,第一绝缘膜142经配置以保护接触垫130不受高密度等离子的损伤。在各个实施方式中,第二绝缘膜144经配置为提供第一绝缘膜142进一步的物理隔绝,防止原子扩散进入接触垫130。在各个实施方式中,第三绝缘膜146经配置以形成第二钝化层140的梯形剖面,从而协助防止悬突及/或孔洞的形成。
第一绝缘膜142包括与第一钝化层120直接接触的第一部分142a、与接触垫130的顶表面直接接触的第二部分142b以及与接触垫130的侧壁直接接触的第三部分142c。第二绝缘膜144包括第一部分144a,位于第一部分142a上方并与第一部分142a直接接触;以及第二部分144b,位于第二部分144b上方并与第二部分144b直接接触。在一些实施方式中,第二绝缘膜144的整体是实质上平行于第一钝化层120的顶表面。第三绝缘膜146是位于第一部分144a、第二部分142b与第三部分142c的上方。换言之,除了接触垫130的侧壁部分,第二绝缘膜144是介于第一绝缘膜142与第三绝缘膜146之间。在接触垫130的侧壁部分,第三绝缘膜146是与第一绝缘膜142直接接触。第四绝缘膜148是与第三绝缘膜146连续地直接接触,并是位于相对软的薄膜150之下,以作为应力缓冲。在一些实施方式中,相对软的薄膜包括聚酰亚胺(polyimide,PI)、苯并环丁烯(benzocyclobutene,BCB)、聚苯并恶唑(polybenzoxazole,PBO)、环氧树脂、硅氧树脂、丙烯酸酯、纳米充填酚树脂(nano-filledphenolic resin)或其他合适的材料的至少一者。在一些实施方式中,第四绝缘膜148具有上部与下部的比值(bottom-up ratio),也就是厚度T44与厚度T42的比值,其范围为约0.75至约1.1。在一些实施方式中,第二钝化层140的每一个绝缘膜包括硅氧化物、硅氮化物、氮氧化硅或另一合适的材料。在一些实施方式中,第二钝化层140的至少一个绝缘膜包括与第一钝化层120相同的材料。在相邻的第一绝缘膜142、第二绝缘膜144、第三绝缘膜146包括相同材料的一些实施方式中,参照横截面图,基于不同的膜密度,是存在一个界面以将一个绝缘膜与另一个绝缘膜分隔。在一些实施方式中,这个界面是通过不同的沉积制程所形成。在一些实施方式中,第二钝化层140的每一个绝缘膜包括与第一钝化层120不同的材料。在至少一个实施方式中,第一绝缘膜142、第二绝缘膜144及第三绝缘膜146包括硅氧化物,而第四绝缘膜148包括硅氮化物。在一些实施方式中,第四绝缘膜的侧壁部分与底部分之间的角度θ是大于95度。在一些情况下,较小的角度增加了后续制程的困难度,例如聚合物层的充填。
在第一绝缘膜142、第二绝缘膜144及第三绝缘膜146包括硅氧化物的一些实施方式中,第二绝缘膜144的折射率是比第一绝缘膜142高出约8%至约15%。在一些实施方式中,第二绝缘膜144的折射率是大于第三绝缘膜146。在一些实施方式中,第二绝缘膜144的折射率为约1.6至约1.7。在一些情况下,较小的折射率增加了后续的等离子制程所产生的击穿电压的变异。在一些实施方式中,第二绝缘膜144的折射率为约1.7至约1.8。在第一绝缘膜142与第三绝缘膜146包括硅氧化物的一些实施方式中,第一绝缘膜142及/或第三绝缘膜146的折射率独立地为约1.4至约1.5。在一些情况下,较大或较小的折射率改变半导体装置100的剖面。在一些实施方式中,第一绝缘膜142与第三绝缘膜146具有相同的折射率。在一些实施方式中,第一绝缘膜142与第三绝缘膜146具有不同的折射率。举例而言,在一些实施方式中,第一绝缘膜142的折射率是小于第三绝缘膜146。
在第一绝缘膜142、第二绝缘膜144及第三绝缘膜146包括硅氧化物的一些实施方式中,为了具有比第一绝缘膜142与第三绝缘膜146相对来得高的折射率,第二绝缘膜144具有比第一绝缘膜142或第三绝缘膜146较小的氧硅比(oxygen-to-silicon ratio)。在一些实施方式中,第二绝缘膜144具有比第一绝缘膜142或第三绝缘膜146较大的介电常数。因为硅原子构成比氧原子较大的空置空间,因此介电常数是与氧硅比成反比。在第二绝缘膜144与第三绝缘膜146包括硅氧化物的一些实施方式中,第二绝缘膜144或第三绝缘膜146的至少一者具有约2500nm至约2900nm的傅立叶转换红外光频谱(Fourier transform infraredspectroscopy,FTIR)吸收带。在一些实施方式中,第一绝缘膜142、第二绝缘膜144及第三绝缘膜146个别具有约8000nm至约13333nm的FTIR吸收带。
第二钝化层140具有从第一钝化层120的顶表面量测的厚度T20。在一些实施方式中,厚度T20与接触垫130的厚度T30的比值为约0.7至约1.3。在一些情况下,较大的比值增加了充填相邻的接触垫130之间的空间的困难度。在一些情况下,较小的比值对接触垫130所提供的保护不足。第二钝化层140的侧壁之间的最大距离T42是从第四绝缘膜148的顶表面量测,而第二钝化层140的平坦部分的宽度W44是从第四绝缘膜148的顶部分量测。在一些实施方式中,宽度W42与宽度W44的比值为约3:1至约4:1。在一些情况下,较小的比值增加了在接触垫130的上角落的悬突的出现。
图2是根据一个或多个实施方式,制造半导体装置的方法200的流程图。所属技术领域中具有通常知识者将能理解的是,在图2所绘示的方法200之前、之中及/或之后,能够执行额外的操作。根据一些实施方式,以下参照图3A至图3D与图4,提供制造制程的额外细节。
方法200包括操作210,其中导电结构,例如图1中的接触垫130,是形成于第一钝化层上方,例如图1中的第一钝化层120。在一些实施方式中,第一钝化层是设置于最上方的金属间介电层与最上方的导电线路的上方,金属间介电层与导电线路是堆叠于基板上方,以形成互连结构。在一些实施方式中,第一钝化层的厚度为约500nm至约1200nm。在一些情况下,较厚的第一钝化层增加生产成本,且没有显著的效益。在一些情况下,较薄的第一钝化层对底下的互连结构所提供的保护不足。在一些实施方式中,在第一钝化层的沉积之前先形成衬垫(liner),并作为蚀刻停止层,以提供蚀刻选择性。
利用微影制程与蚀刻制程来移除第一钝化层的一部份,以形成至少一个开口,暴露出最上方的导电线路。蚀刻制程包括使用化学蚀刻剂的湿蚀刻,或将第一钝化层暴露至离子轰击的干蚀刻。在开口形成于第一钝化层内之后,导电材料例如铝、铝合金、铜或铜合金设置于第一钝化层上方,充填开口以电性连接至最上方的导电线路。导电材料的沉积包括溅射(sputtering)、物理气相沉积(physical vapor deposition,PVD)、化学气相沉积(chemical vapor deposition,CVD)、原子层沉积(atomic layer deposition,ALD)、电解电镀(electrolytic plating)、无电电镀(electroless plating)或另一合适的制程。在一些实施方式中,沉积导电材料至约1000nm至约3000nm的厚度。在一些情况下,较大的厚度增加生产成本,且对电性性能没有显著的效益。在一些情况下,较小的厚度所提供的保护不足以对抗布线制程(wiring process)时所产生的应力。在导电材料的厚度是小于开口的深度的一些实施方式中,导电结构的中心部分突出朝向第一钝化层,产生位于导电结构的顶表面的凹槽。在一些实施方式中,在沉积导电材料之后执行平坦化制程,例如化学机械研磨(chemical mechanical polishing,CMP),使得导电结构的顶表面是实质上平坦的。接下来,导电层(conductive layer)受到图案化与蚀刻,以形成导电结构,其对应于通过第一钝化层而形成的开口。蚀刻制程包括湿蚀刻与干蚀刻,例如等离子增强(plasma-enhanced)蚀刻制程。在一些实施方式中,从俯视视角来看,导电结构具有圆形、八角形、矩形或另一合适的形状。
方法200包括操作220,其中第一介电膜,例如图1中的第一绝缘膜142是设置于导电结构上方。在至少一实施方式中,第一介电膜是连续并共形地地沿着第一钝化层的顶表面与侧壁,以及导电结构的顶表面而沉积。在一些实施方式中,第一介电膜的沉积包括化学气相沉积,例如等离子增强化学气相沉积(plasma-enhanced CVD,PECVD)、低压化学气相沉积(low pressure CVD,LPCVD)或另一合适的制程。在一些实施方式中,第一介电膜的沉积包括原子层沉积或高纵深比制程(high aspect ratio process,HARP)。
方法200包括操作230,其中第二介电膜,例如图1中的第二绝缘膜144是设置于第一介电膜上方。在一些实施方式中,第二介电膜包括无掺杂硅酸盐玻璃(USG)。第二介电膜的沉积包括化学气相沉积,例如高密度等离子化学气相沉积(high density plasma CVD,HDPCVD)、等离子增强化学气相沉积(PECVD)或另一合适的制程。在第二介电膜包括硅氧化物的一些实施方式中,第二介电膜的氧硅比是小于第一介电膜。所以在沉积时,硅来源与氧来源的用量比足以产生约1.6至约1.8的折射率,硅来源例如硅烷、乙硅烷、丙硅烷或二氯硅烷,氧来源例如氧或一氧化二氮。在一些实施方式中,在后续的制程中,第二介电膜协助防止硅原子扩散至导电结构。在一些实施方式中,第二介电膜提供在离子轰击下的蚀刻选择性或蚀刻耐受性,以实现半导体装置的梯形剖面。
方法200包括操作240,其中第三介电膜,例如图1中的第三绝缘膜146是设置于第二介电膜上方。沉积包括高密度等离子化学气相沉积(HDPCVD)、等离子增强化学气相沉积(PECVD)或另一合适的制程。通过使用高密度等离子化学气相沉积(HDPCVD),第三介电膜是比第一介电膜较密,减少了散布于第一钝化层上的应力,并具有较少的缺陷。在一些实施方式中,在第三介电膜的沉积时,使用电子回旋共振技术(electron cyclotron resonance,ECR)或感应耦合等离子技术(induced coupling plasma,ICP)的高密度等离子化学气相沉积提供了具有射频偏压(radio frequency bias)的离子轰击,移除了一部分的第二介电膜。在第三介电膜包括硅氧化物的一些实施方式中,高密度等离子化学气相沉积使用硅烷作为硅前驱物,并使用氧作为氧前驱物。加入惰性气体至制程中,例如氢,以增强溅射蚀刻效应。在一些实施方式中,在第三介电膜的沉积时,移除沿着导电结构的侧壁的一部分的第二介电膜。因此,一部分的第三介电膜接触第一介电膜。在至少一实施方式中,第三介电膜是以用于第二介电膜的相同方法而沉积。然而,参照横截面图,虽然第三介电膜与第二介电膜是在相同的腔体内受到沉积,并具有相同的材料,但是这两个膜之间存在一个界面。通过移除一部分的第二介电膜,第二钝化层的一组合沿着导电结构的形状,从而减少形成从第二钝化层的上角落向外延伸的悬突的风险。位于相邻的导电垫(例如接触垫)之间的空间具有较少的针孔(pinholes),相较于以其他方式制造的半导体装置。
在一些实施方式中,方法200包括额外的操作,例如第四介电膜设置于第三介电膜上方。作为另一实施例,图案化第四介电膜,并蚀刻第二钝化层,以形成开口,从而暴露导电结构的中心部分,以便耦合至再分布线。
图3A至图3D是根据一个或多个实施方式,半导体装置300在各制造阶段的横截面图。半导体装置300包括相似于半导体装置100的元素,并且相似元素的末两码是相同的。图3A是根据一些实施方式,在操作210后的半导体装置300的横截面图。半导体装置300包括金属间介电层310、导电线路312、第一钝化层320、多个接触垫330及通路插塞332。在一些实施方式中,导电材料是完全地形成于第一钝化层320的顶表面上方。接着执行微影制程与蚀刻制程,以形成接触垫330。在一些实施方式中,使用双重镶嵌技术(dual damascene)形成接触垫330。在一些实施方式中,接触垫330具有约1000nm至约3000nm的厚度。在一些情况下,较大的厚度增加生产成本,且对产量没有显著的效益。在一些情况下,较小的厚度增加在导线接合制程中被损伤的风险。在一些实施方式中,相邻的接触垫130之间的间距S30是相等或大于500nm。在一些情况下,较小的间距增加后续充填制程的困难度。在一些实施方式中,暴露一部分的第一钝化层320,并且在形成接触垫330时,移除此暴露部分。因此,第一钝化层320的暴露部分的顶表面是低于接触垫330的底表面。
图3B是根据一些实施方式,在操作220后,半导体装置300的横截面图。第一绝缘膜342是连续地并共形地沿着第一钝化层的顶表面与侧壁,以及接触垫330的顶表面。在一些实施方式中,第一绝缘膜342具有约50nm至约300nm的厚度。在一些情况下,较大的厚度增加了在相邻的接触垫130之间产生孔洞的可能性。在一些情况下,较小的厚度对接触垫130所提供的保护不足。在一些实施方式中,第一绝缘膜342的底部分是低于接触垫330的底表面,其与第一钝化层320直接接触。
图3C是根据一些实施方式,在操作230后,半导体装置300的横截面图。第二绝缘膜344是连续地并共形地沿着第一绝缘膜342。在一些实施方式中,第二绝缘膜344具有约20nm至约80nm的均匀厚度。在一些情况下,较大的厚度增加了在相邻的接触垫330之间产生孔洞的可能性。在一些情况下,较小的厚度增加了在后续的制程中原子扩散的风险。特定而言,第二绝缘膜344包括接近于并实质上平行于第一钝化层320第一部分344a、位于接触垫330的顶表面上方并实质上平行于第一部分344a的第二部分344b、以及沿着接触垫330的侧壁的第三部分344c。在一些实施方式中,全部的第一部分344a是低于接触垫330的底表面。
图3D是根据一些实施方式,在操作240后,半导体装置300的横截面图。第三绝缘膜346是连续地位于第一绝缘膜342上方。在一些实施方式中,第三绝缘膜346具有约500nm至约1500nm的厚度。在一些情况下,较大的厚度增加了在相邻的接触垫330之间产生孔洞的可能性。第三绝缘膜346的侧壁部分与底部分之间的角度是大于95度。在一些实施方式中,第三绝缘膜346相邻的侧壁部分之间的间距S32是相等或大于250nm。由于在形成第三绝缘膜346时移除了第三部分344c,因此第二绝缘膜344不连续地呈现于第一绝缘膜342上方。因此,第三绝缘膜346的最上方的部分与最底下部分是接触第二绝缘膜344,而第三绝缘膜346的侧壁部分是直接接触第一绝缘膜342。在一些实施方式中,第三绝缘膜346最下方的部分是低于接触垫330的底表面。
图4是根据一个或多个实施方式的半导体装置400的横截面图。半导体装置400包括相似于半导体装置100的元素,并且相似元素的末两码是相同的。相较于图1中的半导体装置100,半导体装置400进一步包括位于第三绝缘膜446与第四绝缘膜448之间的第五绝缘膜447。为了维持相似于半导体装置100的剖面,第三绝缘膜446的厚度比图1中的第三绝缘膜146减少了约100nm。在沉积第三绝缘膜446之后,第五绝缘膜447是连续并共形地地沉积于第三绝缘膜446上方。参照横截面图,第五绝缘膜447具有弯曲的形状。在一些实施方式中,第五绝缘膜447是使用与第二绝缘膜444相同的沉积方法。在一些实施方式中,第五绝缘膜447是使用与第二绝缘膜444不同的沉积方法。举例而言,在一些实施方式中,使用高密度等离子化学气相沉积(HDPCVD)来沉积第二绝缘膜444,并使用等离子增强化学气相沉积(PECVD)来沉积第五绝缘膜。在一些实施方式中,第五绝缘膜具有约20nm至约80nm的厚度。在一些情况下,较大的厚度增加了在相邻的接触垫430之间的产生孔洞的可能性。在一些情况下,较小的厚度增加了在后续的制程中原子扩散的风险。接下来,第四绝缘膜448是设置于第五绝缘膜447上方。在一些实施方式中,第四绝缘膜448是使用与第五绝缘膜447相同的沉积方法。然而,参照横截面图,虽然第四绝缘膜448与第五绝缘膜447是在相同的腔体内受到沉积,但是这两个膜之间存在一个界面。在一些实施方式中,第四绝缘膜448是使用与第五绝缘膜447不同的沉积方法。举例而言,使用等离子增强化学气相沉积(PECVD)来沉积第四绝缘膜448,并使用高密度等离子化学气相沉积(HDPCVD)来沉积第五绝缘膜447。在至少一实施方式中,相较于图1中的半导体装置100,第四绝缘膜448的厚度比第四绝缘膜148的厚度更薄。因此,由于第三绝缘膜446的顶表面是实质上平坦的,因此第五绝缘膜447亦以平坦的形式位于第三绝缘膜446上方。
此叙述的一个态样是关于制造半导体结构的方法。此方法包括形成导电结构于第一钝化层上方,沉积第一介电膜连续地位于导电结构上方,沉积第二介电膜连续地位于第一介电膜上方,以及沉积第三介电膜于第二介电膜上方。一部分的第三介电膜是与一部分的第一介电膜接触。在一些实施方式中,第三介电膜的沉积包括沉积第三介电膜至具有小于第二介电膜的折射率。在一些实施方式中,第三介电膜的沉积包括移除一部分的第二介电膜,以暴露第一介电膜的部分。在一些实施方式中,第二介电膜的沉积与第三介电膜的沉积包括使用高密度等离子化学气相沉积(HDPCVD)来沉积第二介电膜与第三介电膜。在一些实施方式中,第三介电膜的沉积包括沉积第三介电膜至具有比第二介电膜较大的氧硅比。在一些实施方式中,第二介电膜的沉积包括沉积第二介电膜至具有约1.6至约1.7的折射率。在一些实施方式中,第一介电膜与第三介电膜的沉积包括沉积第一介电膜至具有约1.4至约1.5的折射率,以及沉积第三介电膜至具有约1.4至约1.5的折射率。在一些实施方式中,第二介电膜的沉积包括沉积第二介电膜至具有小于第一介电膜或第三介电膜的至少一者的介电常数。
此叙述的另一个态样是关于半导体装置的方法。此方法包括形成两个导电结构于基板上方,沉积第一硅氧化物膜于这两个导电结构上方,沉积第二硅氧化物膜于第一硅氧化物膜上方,其中第二硅氧化物膜具有比第一硅氧化物膜较小的氧硅比,沉积第三硅氧化物膜于第二硅氧化物膜上方,以及沉积硅氮化物膜于第三硅氧化物膜上方。在一些实施方式中,沉积第三硅氧化物膜于第二硅氧化物膜上方包括沉积第三硅氧化物膜,至具有比第二硅氧化物膜较大的氧硅比。在一些实施方式中,此方法进一步包括沉积第四硅氧化物膜于第三硅氧化物膜上方,其中第四硅氧化物膜具有比第一硅氧化物膜或第三硅氧化物膜的至少一者较小的氧硅比。在一些实施方式中,第二硅氧化物膜的沉积包括沉积第二硅氧化物膜至具有比第一硅氧化物膜高出约8%至约15%的折射率。
本叙述的再一个态样是关于半导体结构。半导体结构包括位于第一钝化层上方的导电结构,以及位于导电结构与第一钝化层上方的第二钝化层,其中第二钝化层具有第一氧化物膜,沿着第一钝化层的顶表面与侧壁、以及导电结构的顶表面延伸;第二氧化物膜,位于第一氧化物膜的顶表面与导电结构的顶表面上方;以及第三氧化物膜,沿着第二氧化物膜的顶表面与侧壁,以及导电结构的顶表面延伸。在一些实施方式中,第一氧化物膜的侧壁部分是直接接触第三氧化物膜的侧壁部分。在一些实施方式中,位于第一钝化层上方的第二钝化层的厚度与导电结构的厚度的比值为约0.5至约1。在一些实施方式中,间距与位于第一钝化层上方的第二钝化层的厚度的比值为约0.7至约1.3,其中此间距是介于导电结构与相邻的导电结构之间。在一些实施方式中,进一步包括硅氮化物膜,位于第三氧化物膜上方,其中硅氮化物膜的侧壁部分与底部分之间的角度是大于95度。在一些实施方式中,第二钝化层进一步包括硅氮化物膜,位于第三氧化物膜上方,其中硅氮化物膜的上部与下部的比值(bottom-up ratio)为约0.75至约1.1。在一些实施方式中,第二氧化物膜与第三氧化物膜具有约2500nm至约2900nm的FTIR吸收带。在一些实施方式中,第二氧化物膜具有约20nm至约100nm的厚度。
前述内容概述若干实施例或实例的特征,以使得熟悉此项技术者可较佳理解本揭示的态样。熟悉此技艺者应理解,他们可容易地使用本揭示作为设计或修改用于执行本文所介绍的实施方式相同目的及/或达成相同优点的其他制程及结构的基础。熟悉此技艺者应同时认识到,这些的等效构造并不偏离本揭示的精神及范畴,且其可在不偏离本揭示的精神及范畴的情况下于本文中进行各种变化、替换及变更。
Claims (1)
1.一种制造半导体结构的方法,其特征在于,该方法包含:
形成一导电结构于一第一钝化层的上方;
沉积一第一介电膜,连续地位于该导电结构上方;
沉积一第二介电膜,连续地位于该第一介电膜上方;以及
沉积一第三介电膜于该第二介电膜上方,其中一部分的该第三介电膜是接触一部分的该第一介电膜。
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US11410878B2 (en) | 2022-08-09 |
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US20200161177A1 (en) | 2020-05-21 |
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US11784089B2 (en) | 2023-10-10 |
TW201832302A (zh) | 2018-09-01 |
TWI734856B (zh) | 2021-08-01 |
US20210125860A1 (en) | 2021-04-29 |
US20180233466A1 (en) | 2018-08-16 |
US10553479B2 (en) | 2020-02-04 |
CN108447767B (zh) | 2022-06-10 |
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