CN108389864B - Method for manufacturing three-dimensional flash memory device - Google Patents
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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Abstract
The present invention relates to a method for manufacturing a three-dimensional flash memory device, in which a dielectric filler for filling a dielectric is filled by a low-temperature high-pressure heat treatment, by forming the dielectric filler of the three-dimensional flash memory device having a very large aspect ratio in a supercritical evaporation process or a high-pressure densification process using an oxide composition ratio optimization technique based on high-pressure supercritical, thereby improving the characteristics and reliability of the three-dimensional flash memory device.
Description
Technical Field
The present invention relates to a method for manufacturing a three-dimensional flash memory device in which a void-free (void-free) Dielectric gap is filled under a high Aspect ratio (Aspect ratio), and more particularly, to a method for manufacturing a three-dimensional flash memory device in which a Dielectric filler (Dielectric filler) of a three-dimensional flash memory device having a very large Aspect ratio is formed by a supercritical evaporation process or a high-pressure Densification (Densification) process using a high-pressure supercritical oxide composition ratio optimization technique.
Background
In general, flash memory (flash memory) devices are classified into a NAND (NAND) type and a NOR (NOR) type according to a cell structure and operation.
Further, the memory devices are classified into a floating gate type memory device, a Metal Oxide Nitride Semiconductor (MONOS) type memory device, and a Silicon Nitride Semiconductor (SONOS) type memory device according to the type of material used for the charge storage layer (charge storage film) of the unit cell.
A memory device of the floating gate type is a device which exhibits memory characteristics by using a potential well (potential well), and a memory characteristic is exhibited by using a floating gate which is present in a volume (bulk) of a silicon nitride film which is a dielectric film, or a floating gate which is present at an interface between a dielectric film and the dielectric film, or the like. The metal oxide nitride semiconductor refers to a case where the control gate is formed of a metal, and the silicon nitride semiconductor refers to a case where the control gate is formed of polysilicon.
In particular, the silicon nitride semiconductor or metal oxide nitride semiconductor type has advantages of relatively easy scaling and improved endurance characteristics (endransance) and uniform threshold voltage distribution, compared to the floating gate type flash memory. However, when the thicknesses of the tunnel insulating film and the blocking insulating film are made thin for high integration, the characteristics are degraded in terms of recording storage stability (retentivity) and durability.
Recently, flash memory devices are used as memories for storage in various fields to realize large capacity due to continuous expansion, and mass production of 20 nm-class 128Gbit products is expected to be expanded to a level of 10nm or less by floating gate technology (floating gate technology).
Also, in order to realize high integration of the flash memory device, a two-dimensional structure is changed into a three-dimensional structure, and since a NAND (NAND) flash memory device can connect memory cells in a string form without forming a contact (contact) for each memory cell (cell), various three-dimensional structures in a vertical direction can be realized.
Such a three-dimensional nand flash memory is formed in a form in which an N + junction (junction) diffusion layer is disposed in an Si volume and used as a common source line. This structure has an advantage, but the resistance of the diffusion layer is large, and thus a phenomenon occurs in which the memory cell characteristics deteriorate.
On the other hand, technological developments are also being made to reduce the size of isolation regions for electrically isolating the individual devices of a memory cell. In a local oxidation of silicon (LOCOS) process for forming a magnetic field oxide film in the isolation region, bird's beak legs (bird's shoes) are problematic in that the effective area of the active region into which the magnetic field oxide film penetrates the active region is reduced. In order to solve the problem of the local oxidation of silicon, a Shallow Trench Isolation (STI) process is proposed. In the shallow trench isolation process, as the design rule (design rule) is reduced, the width of the trench is reduced, but the depth of the trench is almost constant, thereby causing the aspect ratio of the trench to gradually increase. Therefore, it becomes increasingly difficult to completely fill the space in the trench with the insulator.
An example of such a technique is disclosed in the following documents and the like.
For example, patent document 1 discloses a shallow trench isolation method including: a step of forming a shallow trench by a conventional photolithography process after laminating a plurality of insulating films on a surface of a semiconductor substrate; forming an oxide film on the bottom surface and the inner side surface of the shallow trench; forming a predetermined film having no underlayer dependency on the surface of the oxide film; and a step of stacking a predetermined insulating film in a predetermined thickness so as to fill the shallow trench in which the predetermined film is formed.
Further, patent document 2 discloses a method for processing a semiconductor substrate, the method including: a step (a) of providing a substrate including a feature portion having one or more features (features), the substrate having feature opening portions for the features; a step (b) of exposing the substrate to a cobalt-containing precursor in order to partially fill the plurality of features; exposing the substrate to a nitrogen-containing gas and a plasma; a step (d) of selectively repeating the step (b) and the step (c); and (e) depositing cobalt within the features according to the differential suppression arrangement, the method of processing the semiconductor substrate being performed at a temperature less than about 400 ℃.
Further, patent document 3 discloses a three-dimensional flash memory device including: a device forming substrate having a through hole penetrating through an upper surface and a lower surface; a conductor which is gap-filled in the through hole; a vertical channel formed on the through hole and formed in a shape extending long in an upper direction of the device forming substrate; and a common source line electrically connected to the conductor and formed of a conductive material.
Further, patent document 4 discloses a step of covering a high aspect ratio feature, including: a step of evaporating a film solution on the patterned features of the semiconductor substrate without a second drying step after wet cleaning the semiconductor substrate including the patterned features; firing at least one of a solvent and an unreacted solution of a film formed from the film solution by heating the substrate at a firing temperature; and a step of applying the film solution to the patterned features using a spin-on method, in which a spin-on dielectric for performing heating, thermal annealing, Ultraviolet (UV) curing, plasma curing, or chemical reactive curing is used.
Further, non-patent document 1 discloses that H is reacted at a low temperature of 400 to 500 ℃2Si that is difficult to oxidize by ordinary process under supercritical O conditions3N4Techniques for carrying out the oxidation.
Documents of the prior art
Patent document
Patent document 0001: korean laid-open patent publication No. 1999-0058163 (1999 publication No. 07/15)
Patent document 0002: korean laid-open patent publication No. 2016-0024351 (published 2016: 03/04/2016)
Patent document 0003: korean granted patent publication No. 10-1040154 (2011, registration on day 02 of 06 years)
Patent document 0004: korean laid-open patent publication No. 2016-
Non-patent document
Non-patent document 0001: Low-Temperature Oxidation of silicon nitride by water in supercritical conditioning, Journal of the European Ceramic Society, Vol.16, No.10,1996, p.1111.
Disclosure of Invention
Technical problem to be solved
However, in the related art as described above, in the case of filling a dielectric in a flash memory device based on a hollow (Macaroni) Si channel, there is a problem that voids (void) or seams (seam) are generated due to a high aspect ratio.
That is, in the conventional three-dimensional flash memory device, a structure having a very large aspect ratio is formed, and in the structure in which the central portion of the silicon channel having the hollow structure is filled with the dielectric filler, it is necessary to fill the silicon channel with an oxide having a sufficient composition ratio to ensure stable operation characteristics of the device.
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a three-dimensional flash memory device in which a dielectric filler of a three-dimensional flash memory device having a very large aspect ratio is subjected to a low-temperature high-pressure treatment so that voids and seams are not formed during charging of the dielectric filler.
Another object of the present invention is to provide a method for manufacturing a three-dimensional flash memory device, which can maximize device characteristics and reliability of the three-dimensional flash memory device.
Technical scheme for solving problems
In order to achieve the above object, the present invention provides a method for manufacturing a three-dimensional flash memory device for filling a gap having a high aspect ratio with a dielectric material that is void-free (void-free), wherein a dielectric filler for filling the dielectric material is filled by a low-temperature high-pressure heat treatment.
In the method for manufacturing a three-dimensional flash memory device according to the present invention, the dielectric filler is an oxide film.
In the method for manufacturing a three-dimensional flash memory device according to the present invention, the low-temperature high-pressure heat treatment is performed under a pressure of 1 to 20 atmospheres and at a temperature of 100 to 500 ℃.
Also, the present invention is characterized in that, in the method for manufacturing a three-dimensional flash memory device of the present invention, the low-temperature high-pressure heat treatment is performed by using water (H)2O) for a 30 minute period.
Further, according to the present invention, there is provided a method for manufacturing a three-dimensional flash memory device, comprising: a step (a) of forming a molded structure by laminating an interlayer insulating film for a control gate and a sacrificial layer in a multilayer manner on a substrate; a step (b) of forming a gap by etching the molded structure; a step (c) of forming a gate insulating film on the inner walls of the interlayer insulating film and the sacrificial layer; a step (d) of forming a channel in an inner wall of the gate insulating film; filling dielectric filler into the channel by a supercritical evaporation process or a high-pressure densification process; and (f) removing the sacrificial layer.
In the method for manufacturing a three-dimensional flash memory device according to the present invention, the step (e) includes: a step (e1) of coating a spin-on glass insulating film on the inside of the above-mentioned channel with a polysilazane solution; a step (e2) of performing pre-firing at a predetermined temperature to remove the solvent component of the insulating film; and a step (e3) of performing heat treatment as wet heat treatment in a high pressure state.
Also, the present invention is characterized in that, in the method for manufacturing a three-dimensional flash memory device of the present invention, the step (e2) is performed at a temperature ranging from 50 to 350 ℃ for 20 to 40 minutes.
Advantageous effects of the invention
As described above, according to the method of manufacturing the three-dimensional flash memory device of the present invention, there is an effect that device characteristics and reliability can be improved by minimizing voids in the three-dimensional flash memory device having a hollow structure and having a high aspect ratio.
In addition, the method for manufacturing a three-dimensional flash memory device according to the present invention has an effect that a dielectric filler of the three-dimensional flash memory device can be formed by a supercritical evaporation or high-pressure densification process by performing a low-temperature high-pressure heat treatment.
Further, according to the method of manufacturing a three-dimensional flash memory device of the present invention, when a shallow trench isolation process is applied to a new device such as Ge or III-V, an oxide film having good quality is densified at a very low temperature, thereby having an effect of heat dissipation cost (thermal budget).
Drawings
Fig. 1 is a perspective view illustrating a cell region of a nand-type flash memory device as a three-dimensional flash memory device applicable to the present invention.
Fig. 2 is a perspective view showing an example of a cell transistor constituting the cell region in fig. 1.
Fig. 3 is a perspective view showing still another example of a cell transistor constituting the cell region in fig. 1.
Fig. 4 to 8 are cross-sectional views for explaining a process of sequentially forming a gate insulating film, a channel, and an insulator in a control gate.
Fig. 9 is a Scanning Electron Microscope (SEM) image showing a cross-section of an insulator formed according to an embodiment of the present invention.
Description of reference numerals
15: control gate 16: channel
20: gate insulating film 21: insulator
Detailed Description
The above-described object and the novel features of the present invention will become more apparent from the technology in this specification and the accompanying drawings.
Hereinafter, the structure of the present invention will be described with reference to the drawings.
Fig. 1 is a perspective view showing a cell region of a nand-type flash memory device applied to a three-dimensional flash memory device of the present invention, fig. 2 is a perspective view showing an example of a cell transistor constituting the cell region in fig. 1, and fig. 3 is a perspective view showing another example of a cell transistor constituting the cell region in fig. 1.
As a three-dimensional flash memory device employed in the present invention, a vertical NAND-type (vertical NAND-type) flash memory apparatus 100 includes: a cell region including a plurality of memory cells; and a peripheral region including a peripheral circuit for operating the memory cell. That is, the vertical nand-type flash memory device 100 includes a row (row) control circuit, a page buffer circuit, a common source line control circuit, a memory cell array, and a column gate circuit. Such a vertical nand type flash memory device has a Gate-All-Around (GAA) structure of a fully depleted (fully depleted) channel, and thus, a program inhibition characteristic during a program inhibition operation (program inhibition) is very excellent.
In the following description, a memory cell array as a cell region is described, but the present invention is not limited thereto, and can be applied to the peripheral region as described above.
For example, the cell region includes: a plurality of control gates 15 formed in a plate shape, vertically stacked along a Z direction on the semiconductor substrate 10, and forming an X-Y plane; a lower select gate 13 disposed below the plurality of control gates 15; a plurality of upper select gates 14 disposed above the plurality of control gates 15; a plurality of bit lines 11 stacked on the upper side of the upper selection gate 14 and extending in the Y direction; and a plurality of channels extending vertically along the Z-direction on the semiconductor substrate 10.
The plurality of channels 16 extend from the semiconductor substrate 10 to the bit lines 11 and penetrate the upper selection gate 14, the lower selection gate 13, and the control gate 15. Further, the semiconductor substrate 10 is a P-type silicon substrate, but the present invention is not limited thereto, and the channel 16 is made of the same or similar material as the semiconductor substrate 10, and may have the same conductivity type. The semiconductor substrate 10 may include an N-type source.
As shown in fig. 1, in the three-dimensional flash memory device applicable to the present invention, the channel 16 and the control gate 15 constitute a memory transistor, the channel 16 and the lower select gate 13 may constitute a lower select transistor, and the channel 16 and the upper select gate 14 may constitute an upper select transistor.
As described above, the vertical nand-type flash memory device 100 applied to the present invention is configured as one cell string 12 by connecting a plurality of memory transistors formed in one channel 16 in series with an upper transistor and a lower transistor, as shown in fig. 1.
In the configuration shown in fig. 1, one cell string 12 is configured by 4 memory transistors, but the number of memory transistors in one cell string 12 is not limited to this, and any number may be selected depending on the memory capacity, for example, 8, 16, 32, and the like. Further, although the passage 16 is formed in a cylindrical shape in the structure shown in fig. 1, the present invention is not limited thereto, and a quadrangular pillar shape may be adopted.
The memory transistor, the upper selection transistor, and the lower selection transistor are formed as depletion transistors having no source and no drain in the channel 16, but the present invention is not limited thereto, and the memory transistor, the upper selection transistor, and the lower selection transistor may be formed as enhancement transistors having a source and a drain in the channel 16.
The plurality of channels 16 penetrate the plurality of control gates 15 along the Z direction, and thus, intersections between the plurality of control gates 15 and the plurality of channels 16 realize a three-dimensional distribution. The memory transistors of the present invention are formed at the plurality of intersections of the three-dimensional distribution as described above.
As shown in fig. 2, a memory transistor suitable for the vertical nand-type flash memory device 100 of the present invention may have a gate insulating film 20 provided with a charge storage film between a channel 16 and a control gate 15. The charge storage film may include an insulating film capable of floating charges. For example, in the case where the gate insulating film 20 is a so-called Oxide-Nitride-Oxide (ONO) film in which a silicon Oxide film, a silicon Nitride film (or a silicon oxynitride film), and a silicon Oxide film are stacked, electric charges can be floated and maintained by the silicon Nitride film (or the silicon oxynitride film). The charge storage film may include a floating gate formed of a conductive material.
In the vertical nand-type flash memory device 100 applied to the present invention, the memory transistor may be formed in a so-called hollow form having an insulator 21 as a dielectric filler inside the channel 16, as shown in fig. 3. The insulator 21 is formed in a pillar shape in a manner corresponding to the shape of the channel 16. Since the insulator 21 occupies the interior of the channel 16, the channel 16 can have a thinner thickness than the structure in fig. 2, which can reduce the floating gate of the carrier.
Also, in fig. 1, the upper selection transistor 14 and the lower selection transistor 13 may have the same or similar structures as those shown in fig. 2 or 3. The gate insulating films 20 of the upper selection transistor and the lower selection transistor may be formed of silicon oxide films or silicon nitride films.
Next, a method of filling a gap 300 provided in a channel 16 with a void-free dielectric in the process of forming an insulator 21 in the three-dimensional flash memory device having a high aspect ratio of the present invention will be described with reference to fig. 4 to 9.
Fig. 4 to 8 are sectional views for explaining a process of sequentially forming a gate insulating film, a channel, and an insulator in a control gate, and fig. 9 is a scanning electron microscope image showing a section of an insulator formed according to an embodiment of the present invention.
In the following description, a three-dimensional flash memory device having a hollow structure as shown in fig. 3 is taken as an example, but the present invention is not limited thereto, and can be applied to the structure shown in fig. 2. For convenience of explanation, a string structure in which control gates 15 are stacked on substrate 10 will be described, but the present invention is not limited to this, and may be applied to a structure in which lower select gates 13 and upper select gates 14 are provided on substrate 10 as shown in fig. 1.
First, as shown in fig. 4, interlayer insulating films for the control gate 15 and a sacrificial layer 200 are laminated in multiple layers on the substrate 10 to form a molded structure. The substrate 10 may be a Semiconductor substance, and may be, for example, a silicon single crystal substrate, a germanium single crystal substrate, or a silicon-germanium single crystal substrate or a Semiconductor On Insulator (SOI) substrate. For example, the substrate 10 may include a semiconductor layer (e.g., a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer for protecting a plurality of transistors on the semiconductor substrate
The sacrificial layer 200 preferably has a higher etching selectivity in a wet etching process using a chemical solution than in the interlayer insulating film, as a material having etching selectivity to the interlayer insulating film. For example, the interlayer insulating film may be a silicon oxide film or a silicon nitride film, and the sacrificial layer 200 may be selected from the group consisting of a silicon oxide film, a silicon nitride film, silicon carbide, silicon, and silicon germanium, and may have an etching selectivity with respect to the interlayer insulating film. For example, a metal nitride may be used as the interlayer insulating film, and silicon oxide may be used as the sacrificial layer 200. Such an interlayer insulating film and the sacrificial Layer 200 may be formed using Thermal chemical vapor Deposition (Thermal CVD), Plasma enhanced chemical vapor Deposition (Plasma enhanced CVD), or Atomic Layer Deposition (ALD) techniques.
For convenience of explanation, fig. 4 shows a configuration for 4 control gates 15, but the present invention is not limited to this, and may be applied to a string configuration including 8 or 12 control gates.
Next, as shown in fig. 5, the molded structure is etched to form a substantially cylindrical gap 300. The gap 300 is formed by forming a mask pattern on the molded structure and anisotropically etching the molded structure using the mask pattern as an etching mask. The gap 300 can increase the aspect ratio, for example, to 50 or more, according to the increase in capacity of the three-dimensional flash memory device.
Next, as shown in fig. 3 and 6, the gate insulating film 20 is formed inside the control gate 15 and the sacrificial layer 200, which are interlayer insulating films. Such a gate insulating film 20 may include a charge storage film that can float charges from the channel, for example, in the case where the flash memory is of the metal oxide nitride semiconductor type or the silicon nitride semiconductor type, charges can be floated and maintained by the silicon nitride film (or the silicon oxynitride film). The gate insulating film 20 may include a blocking insulating film, a charge storage film, and a tunnel insulating film. For example, a blocking insulating film, a charge storage film, and a tunnel insulating film are formed in this order from the control gate 15 and the inner wall of the sacrificial layer 200.
Next, as shown in fig. 7, a channel 16 is formed on the inner wall of the gate insulating film 20. The above-described channel 16 can be formed of Poly-Si which can easily achieve control of the sub-critical characteristics.
Next, as shown in fig. 8, a dielectric filler is filled into the inside of the channel 16 by a supercritical vapor deposition or high-pressure densification process, a trench (not shown) is formed in the molded structure, the exposed sacrificial layer 200 is removed from the trench, and an opening region is formed between the interlayer insulating films for the control gates 15, so that the plurality of control gates 15 are spaced apart from each other by the channel 16, thereby forming the structure shown in fig. 1. In the removal of the sacrificial layer 200, for example, when the sacrificial layer 200 is a silicon nitride film and the interlayer insulating film is a silicon oxide film, the sacrificial layer 200 is etched in a homogeneous manner using an etching solution containing phosphoric acid, thereby forming an opening region.
Next, a process of filling the passage 16 with the insulator 21 as a dielectric filler while preventing generation of voids or seams will be described.
The passage 16 is provided with a hole having an aspect ratio of 50 or more.
On the uppermost surface of the substrate 10A spin-on-glass (SOG) insulating film is coated with a polysilazane solution on the surface of the control gate electrode 15. That is, in order to form the insulator 21 by filling the hole having a high aspect ratio with the dielectric filler, for example, filling is performed by spin-coating a polysilazane solution at a speed of 1500rpm for 30 seconds in an air atmosphere. In the above description, the spin coating method was described as being performed at 1500rpm for 30 seconds, but the method is not limited to this, and may be changed according to the value of the aspect ratio. The polysilazane may be represented by the formula- (Si)xNyHz) The substance represented by (a) is a solution having a predetermined weight ratio using a solvent soluble in xylene, dibutyl ether or the like. Further, before coating polysilazane, Al can be formed by high-density plasma Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Liquid Phase Chemical Vapor Deposition (LPCVD), or the like, which are excellent in gap filling ability2O3A buffer layer.
Thereafter, pre-firing is performed at a temperature range of 50 to 350 ℃ in order to remove the solvent component of the insulator 21. The pre-firing is performed by heating the substrate from a normal temperature for a predetermined time (for example, 30 minutes) in a range of 50 to 350 ℃ in a stepwise manner by the same heating or by heating the substrate on a susceptor of a heating apparatus. By this process, most of the solvent component will be removed. The temperature and time described above may be adjusted according to the formation conditions of the three-dimensional flash memory device.
Thereafter, the insulator 21 is heat-treated. In the present invention, the heat treatment is performed in a wet heat treatment in a low-temperature high-pressure state.
That is, after the pre-baking, the low-pressure wet heat treatment is performed under a pressure condition of 1 to 20 atmospheres and a temperature condition of 100 to 500 ℃, and for example, the low-pressure wet heat treatment is performed for 30 minutes using water in an amount (for example, 20ml) sufficient to react with the spin-coated polysilazane.
The spin-coated polysilazane and H are subjected to the heat treatment as described above2O producing reaction to produce SiO2And an insulator 21.
Fig. 9 shows a state in which the insulator 21 as a dielectric filler is filled in the passage 16 as a result of the heat treatment as described above.
Fig. 9 is a scanning electron microscope image showing a cross section of the insulator 21 formed under 10 atmospheres as in the example of the present invention, and it can be seen that the insulator 21 is uniformly filled in such a manner that voids and seams are not generated in the upper and lower portions. This is because the high-pressure heat treatment can sufficiently react water and polysilazane even in the depth of the channel 16.
As described above, according to the present invention, the dielectric filler of the three-dimensional flash memory device having a very large aspect ratio is formed by a supercritical evaporation or high-pressure densification process using the high-pressure supercritical-based oxide composition ratio optimization technique, so that the voids and seams can be minimized.
The present invention made by the present inventors has been specifically described above with reference to the above embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention.
Industrial applicability
By using the method of manufacturing the three-dimensional flash memory device of the present invention, voids can be minimized in the three-dimensional flash memory device, thereby improving the characteristics and reliability of the device.
Claims (3)
1. A method of manufacturing a three-dimensional flash memory device for filling a gap having a high aspect ratio with a dielectric substance as a void-free dielectric, comprising:
a step (a) of forming a molded structure by laminating an interlayer insulating film for a control gate and a sacrificial layer in a multilayer manner on a substrate;
a step (b) of forming a gap by etching the molded structure;
a step (c) of forming a gate insulating film on the inner walls of the interlayer insulating film and the sacrificial layer;
a step (d) of forming a channel in an inner wall of the gate insulating film;
filling dielectric filler into the channel by a high-pressure densification process; and
step (f), removing the sacrificial layer,
the step (e) includes:
a step (e1) of coating a spin-on glass insulating film on the inside of the above-mentioned channel with a polysilazane solution;
a step (e2) of performing pre-firing at a predetermined temperature to remove the solvent component of the insulating film; and
a step (e3) of performing a heat treatment as a wet heat treatment in a high pressure state,
the dielectric filler for filling the above dielectric is filled by low-temperature high-pressure heat treatment,
the low-temperature high-pressure heat treatment is performed under a pressure of 1 to 20 atm and at a temperature of 100 to 500 ℃,
the above low-temperature high-pressure heat treatment is performed for a period of 30 minutes by using water.
2. The method of claim 1, wherein the dielectric filler is an oxide film.
3. The method of claim 1, wherein the step (e2) is performed at 50 to 350 ℃ for 20 to 40 minutes.
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| KR20090037165A (en) * | 2007-10-11 | 2009-04-15 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US8557712B1 (en) * | 2008-12-15 | 2013-10-15 | Novellus Systems, Inc. | PECVD flowable dielectric gap fill |
| CN104205302A (en) * | 2012-03-28 | 2014-12-10 | 应用材料公司 | Method of enabling seamless cobalt gap-fill |
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| KR100440418B1 (en) * | 1995-12-12 | 2004-10-20 | 텍사스 인스트루먼츠 인코포레이티드 | Low pressure, low temperature semiconductor gap filling treatment |
| KR100765682B1 (en) * | 1998-06-19 | 2007-10-11 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and production method thereof |
| JP2008010739A (en) * | 2006-06-30 | 2008-01-17 | Toshiba Corp | Semiconductor device, and its manufacturing method |
| JP2008283045A (en) * | 2007-05-11 | 2008-11-20 | Toshiba Corp | Method of manufacturing semiconductor device, and the semiconductor device |
| JP5376789B2 (en) * | 2007-10-03 | 2013-12-25 | 株式会社東芝 | Nonvolatile semiconductor memory device and control method of nonvolatile semiconductor memory device |
| KR101040154B1 (en) | 2009-11-04 | 2011-06-09 | 한양대학교 산학협력단 | 3-dimensional flash memory device |
| US8963156B2 (en) * | 2013-02-22 | 2015-02-24 | Micron Technology, Inc. | Semiconductor devices including WiSX |
| CN104779251B (en) * | 2014-01-13 | 2017-12-26 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacture method |
| KR101571715B1 (en) * | 2014-04-23 | 2015-11-25 | 주식회사 풍산 | Method of forming spin on glass type insulation layer using high pressure annealing |
| KR20160137091A (en) * | 2015-05-22 | 2016-11-30 | 삼성전자주식회사 | Methods of manufacturing vertical memory devices |
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| KR20090037165A (en) * | 2007-10-11 | 2009-04-15 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US8557712B1 (en) * | 2008-12-15 | 2013-10-15 | Novellus Systems, Inc. | PECVD flowable dielectric gap fill |
| CN104205302A (en) * | 2012-03-28 | 2014-12-10 | 应用材料公司 | Method of enabling seamless cobalt gap-fill |
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