CN108364870B - 改善栅极氧化层质量的屏蔽栅沟槽mosfet制造方法 - Google Patents

改善栅极氧化层质量的屏蔽栅沟槽mosfet制造方法 Download PDF

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CN108364870B
CN108364870B CN201810062556.1A CN201810062556A CN108364870B CN 108364870 B CN108364870 B CN 108364870B CN 201810062556 A CN201810062556 A CN 201810062556A CN 108364870 B CN108364870 B CN 108364870B
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周宏伟
杨乐
刘挺
岳玲
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Longteng Semiconductor Co.,Ltd.
Xi'an Longxiang Semiconductor Co.,Ltd.
Xusi semiconductor (Shanghai) Co.,Ltd.
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Abstract

本发明涉及一种改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法，通过在深槽内填充并回刻蚀多晶硅，使两个深槽互相电荷平衡完成超结功能，再在深槽上方采用氧化层淀积加厚栅极源极间氧化层，最后通过栅极热氧化和多晶硅淀积，共同构成屏蔽栅沟槽器件。本发明通过一次能氧化层各向异性淀积的特殊条件高密度等离子体化学气相淀积对栅极源极间氧化层厚度和形貌进行调整，可形成高质量栅极源极间氧化层，可以用传统的半导体制造工艺实现，在工艺难度不增加的情况下改善源极多晶硅与栅极多晶硅之间氧化层质量，优化产品的参数，提高成品率和可靠性，最终达到降低芯片成本。

Description

改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法。
背景技术
对于传统的功率MOSFET器件，器件导通电阻(Ron)与源漏击穿电压存在一定的折中关系（Ron∝BV2.5），长久以来限制了功率MOSFET器件的发展。屏蔽栅沟槽 MOSFET 利用电荷平衡原理，使得N型漂移区即使在较高掺杂浓度的情况下也能实现器件较高的击穿电压，从而获得低的导通电阻，打破了传统功率MOSFET的硅极限。如图21，普通工艺流程高掺杂多晶硅形成氧化层质量不高且栅源极性之间的氧化层厚度不均匀，对器件参数和可靠性带来了极大风险。
发明内容
本发明的目的是提供一种改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法,在工艺成本基本不变的前提下，可以用传统的半导体制造工艺实现，在不增加工艺难度的前提下生成厚度可调、质量较好的栅源极氧化层。
本发明所采用的技术方案为：
改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法，其特征在于：
通过在深槽内填充并回刻蚀多晶硅，使两个深槽互相电荷平衡完成超结功能，再在深槽上方采用氧化层淀积加厚栅极源极间氧化层，最后通过栅极热氧化和多晶硅淀积，共同构成屏蔽栅沟槽器件。
包括以下步骤：
步骤一：提供 n 型重掺杂的 n+ 衬底，并在n+衬底上形成n型外延层；
步骤二：在外延层表面形成厚氧化层，形成硬掩膜；
步骤三：通过光刻、干法腐蚀形成有源区的深沟槽与终端区的深沟槽，终端区深沟槽包围有源区深沟槽，最后去除厚氧化层；
步骤四：利用湿法热氧化工艺在所述深沟槽底部和侧壁生长场氧化层；
步骤五：利用多晶硅淀积工艺，进行第一次多晶硅淀积；
步骤六：通过干法腐蚀工艺进行多晶硅回刻，使有源区深沟槽上方得到一个浅沟槽，终端区深沟槽内的第一多晶硅及场氧化层在光刻胶的保护下不回刻；
步骤七：通过光刻、湿法腐蚀对场氧化层进行去除；
步骤八：利用刻蚀工艺继续回刻沟槽内的多晶硅；
步骤九：利用能氧化层各向异性淀积的特殊条件高密度等离子体化学气相淀积(HDP CVD)对栅极源极间氧化层厚度和形貌进行调整；
步骤十：利用湿法刻蚀工艺去除侧壁剩余场氧化层；
步骤十一：利用干法氧化形成栅极氧化层；
步骤十二：第二次多晶硅淀积，并对第二次多晶硅干法回刻，形成浅槽MOSFET器件栅极；
步骤十三：阱注入前对表面氧化层进行去除；
步骤十四：P-BODY注入，形成P阱；
步骤十五：通过注入，制作器件有源区；
步骤十六：淀积介质层，接触孔刻蚀；
步骤十七：接触孔刻蚀注入形成欧姆接触；
步骤十八：完成表面金属结构；
步骤十九：背面减薄并完成背面金属结构。
如所述的制造方法制得的改善栅极氧化层质量的屏蔽栅沟槽MOSFET结构。
本发明具有以下优点：
本发明通过一次能氧化层各向异性淀积的特殊条件高密度等离子体化学气相淀积(HDP CVD)对栅极源极间氧化层厚度和形貌进行调整，可形成高质量栅极源极间氧化层，可以用传统的半导体制造工艺实现，在工艺难度不增加的情况下改善源极多晶硅与栅极多晶硅之间氧化层质量，优化产品的参数，提高成品率和可靠性，最终达到降低芯片成本。
附图说明
图1为本发明步骤一的示意图；
图2为本发明步骤二的示意图；
图3为本发明步骤三的示意图；
图4为本发明步骤四的示意图；
图5为本发明步骤五的示意图；
图6为本发明步骤六的示意图；
图7为本发明步骤七的示意图；
图8为本发明步骤八的示意图；
图9为本发明步骤九的示意图；
图10为本发明步骤十的示意图；
图11为本发明步骤十一的示意图；
图12为本发明步骤十二的示意图；
图13为本发明步骤十三的示意图；
图14为本发明步骤十四的示意图；
图15为本发明步骤十五的示意图；
图16为本发明步骤十六的示意图；
图17为本发明步骤十七的示意图；
图18为本发明步骤十八的示意图；
图19为本发明步骤十九的示意图；
图20为本发明器件的截面图。
图21 为现有老工艺最终器件的截面图。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
本发明涉及改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法，通过在深槽内填充并回刻蚀多晶硅，使两个深槽互相电荷平衡完成超结功能，再在深槽上方采用氧化层淀积加厚栅极源极间氧化层，最后通过栅极热氧化和多晶硅淀积，共同构成屏蔽栅沟槽器件。
具体包括以下步骤：
步骤一：提供 n 型重掺杂的 n+ 衬底，并在n+衬底上形成n型外延层；
步骤二：在外延层表面形成厚氧化层，形成硬掩膜；
步骤三：通过光刻、干法腐蚀形成有源区的深沟槽与终端区的深沟槽，终端区深沟槽包围有源区深沟槽，最后去除厚氧化层；
步骤四：利用湿法热氧化工艺在所述深沟槽底部和侧壁生长场氧化层；
步骤五：利用多晶硅淀积工艺，进行第一次多晶硅淀积；
步骤六：通过干法腐蚀工艺进行多晶硅回刻，使有源区深沟槽上方得到一个浅沟槽，终端区深沟槽内的第一多晶硅及场氧化层在光刻胶的保护下不回刻；
步骤七：通过光刻、湿法腐蚀对场氧化层进行去除；
步骤八：利用刻蚀工艺继续回刻沟槽内的多晶硅；
步骤九：利用能氧化层各向异性淀积的特殊条件高密度等离子体化学气相淀积(HDP CVD)对栅极源极间氧化层厚度和形貌进行调整；
步骤十：利用湿法刻蚀工艺去除侧壁剩余场氧化层；
步骤十一：利用干法氧化形成栅极氧化层；
步骤十二：第二次多晶硅淀积，并对第二次多晶硅干法回刻，形成浅槽MOSFET器件栅极；
步骤十三：阱注入前对表面氧化层进行去除；
步骤十四：P-BODY注入，形成P阱；
步骤十五：通过注入，制作器件有源区；
步骤十六：淀积介质层，接触孔刻蚀；
步骤十七：接触孔刻蚀注入形成欧姆接触；
步骤十八：完成表面金属结构；
步骤十九：背面减薄并完成背面金属结构。
本发明通过一次特殊条件的高密度等离子体化学气相淀积(HDP CVD)对栅极源极间氧化层厚度和形貌进行调整，避免多晶硅氧化形成的低质量氧化层和图21中老式方案栅源间根部氧化层不均匀，造成栅源间耐压不够，器件失效。
方法具有以下特点：
一: 一次多晶硅的二次回刻蚀；
二：一次能氧化层各向异性淀积的特殊条件高密度等离子体化学气相淀积(HDPCVD)对栅极源极间氧化层厚度和形貌进行调整；
三:利用干法氧化层和淀积氧化层之间极大的腐蚀速率差，在阱注入前对器件表面的氧化层进行去除。
本发明的内容不限于实施例所列举，本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换，均为本发明的权利要求所涵盖。

Claims (2)

1.改善栅极氧化层质量的屏蔽栅沟槽MOSFET制造方法，其特征在于：
通过在深槽内填充并回刻蚀多晶硅，使两个深槽互相电荷平衡完成超结功能，再在深槽上方采用氧化层淀积加厚栅极源极间氧化层，最后通过栅极热氧化和多晶硅淀积，共同构成屏蔽栅沟槽器件；
包括以下步骤：
步骤一：提供 n 型重掺杂的 n+ 衬底，并在n+衬底上形成n型外延层；
步骤二：在外延层表面形成厚氧化层，形成硬掩膜；
步骤三：通过光刻、干法腐蚀形成有源区的深沟槽与终端区的深沟槽，终端区深沟槽包围有源区深沟槽，最后去除厚氧化层；
步骤四：利用湿法热氧化工艺在所述深沟槽底部和侧壁生长场氧化层；
步骤五：利用多晶硅淀积工艺，进行第一次多晶硅淀积；
步骤六：通过干法腐蚀工艺进行多晶硅回刻，使有源区深沟槽上方得到一个浅沟槽，终端区深沟槽内的第一多晶硅及场氧化层在光刻胶的保护下不回刻；
步骤七：通过光刻、湿法腐蚀对场氧化层进行去除，在多晶硅以上的侧壁区域不全部去除，保留一层薄层；
步骤八：利用刻蚀工艺继续回刻沟槽内的多晶硅，即二次回刻；
步骤九：采用能使氧化层各向异性淀积的条件进行高密度等离子体化学气相淀积，实现对栅极源极间氧化层厚度和形貌的调整；
步骤十：利用湿法刻蚀工艺去除侧壁剩余场氧化层；
步骤十一：利用干法氧化形成栅极氧化层；
步骤十二：第二次多晶硅淀积，并对第二次多晶硅干法回刻，形成浅槽MOSFET器件栅极；
步骤十三：阱注入前对表面氧化层进行去除；
步骤十四：P-BODY注入，形成P阱；
步骤十五：通过注入，制作器件有源区；
步骤十六：淀积介质层，接触孔刻蚀；
步骤十七：接触孔刻蚀注入形成欧姆接触；
步骤十八：完成表面金属结构；
步骤十九：背面减薄并完成背面金属结构。
2.利用权利要求1所述的制造方法制得的改善栅极氧化层质量的屏蔽栅沟槽MOSFET结构。
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CN111276394B (zh) * 2020-02-18 2022-09-23 捷捷微电(上海)科技有限公司 一种分离栅mosfet的制作方法
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CN112133637B (zh) * 2020-11-30 2021-02-12 中芯集成电路制造(绍兴)有限公司 具有屏蔽栅沟槽的半导体器件的制造方法
CN112908841B (zh) * 2021-03-24 2024-03-22 上海华虹宏力半导体制造有限公司 半导体器件的制备方法
CN113471078A (zh) * 2021-06-11 2021-10-01 上海格瑞宝电子有限公司 一种sgt-mosfet及其制造方法
CN113725078A (zh) * 2021-09-11 2021-11-30 捷捷微电(上海)科技有限公司 一种分离栅mosfet的制作方法
CN118073186A (zh) * 2022-11-22 2024-05-24 华润微电子（重庆）有限公司 一种屏蔽栅功率mosfet及其制作方法
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CN117457499A (zh) * 2023-11-01 2024-01-26 中晶新源(上海)半导体有限公司 一种改善屏蔽栅功率半导体器件hdp填充的工艺方法
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