CN108346587A - 芯片封装器件及封装方法 - Google Patents

芯片封装器件及封装方法 Download PDF

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Publication number
CN108346587A
CN108346587A CN201710061017.1A CN201710061017A CN108346587A CN 108346587 A CN108346587 A CN 108346587A CN 201710061017 A CN201710061017 A CN 201710061017A CN 108346587 A CN108346587 A CN 108346587A
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China
Prior art keywords
chip
layer
substrate
packaging method
plastic
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CN201710061017.1A
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English (en)
Inventor
张万宁
于德泽
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Singapore Co Ltd
Singapore Ltd
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Singapore Ltd
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Application filed by Singapore Ltd filed Critical Singapore Ltd
Priority to CN201710061017.1A priority Critical patent/CN108346587A/zh
Priority to PCT/CN2017/077439 priority patent/WO2018137280A1/zh
Priority to US16/480,622 priority patent/US10937767B2/en
Publication of CN108346587A publication Critical patent/CN108346587A/zh
Pending legal-status Critical Current

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Abstract

本发明提供了一种芯片封装器件及封装方法，所述芯片封装方法包括：提供一承载板，所述承载板上设置有第一粘接层；将多个芯片间隔放置于所述第一粘接层上；采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；移除所述承载板与第一粘接层；在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内形成金属导体层以及芯片之间的互连电路；对所述塑封芯片进行切割，形成多个模块；采用本发明所述的芯片封装方法，能够减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化。

Description

芯片封装器件及封装方法
技术领域
本发明涉及芯片封装的技术领域，特别涉及一种芯片封装器件及封装方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件，兼具MOS的高输入阻抗和GTR(巨型晶体管)的低导通压降两方面的优点。GTR饱和压降低，载流密度大，但驱动电流较大，MOS驱动功率很小，开关速度快，但导通压降大，载流密度小。IGBT综合了以上两种器件的优点，驱动功率小而饱和压降低，非常适合应用于直流电压为600v及以上的变流***如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
图1为现有技术中IGBT模块的封装结构示意图，如图1所示，所述封装结构包括：铝碳化硅散热板1，依次位于所述铝碳化硅散热板1之上的第一焊料层2、第一铜层3、陶瓷层4以及第二铜层5，位于所述第二铜层5上彼此隔开的第二焊料层6与第三铜层7，以及位于所述第二焊料层6上的彼此隔开的二极管芯片8与IGBT 9。所述二极管芯片8、IGBT 9以及第三铜层7通过导线10相连接。
所述导线10一般为金线、铝线或铜线，线连接的缺点是导线长，电阻大，电能转换成不必要的热能。功率器件的金属线为保证低电阻率，和加强散热，必须使用粗线，在0.1毫米以上，普通的只有0.25毫米。这样就使芯片与衬底的互联距离很大，芯片之间的互联也要比普通芯片大，使得终端产品面积比较大。
因此，提供一种缩小芯片之间距离的封装，减小终端产品面积是本领域技术人员亟需解决的一个技术问题。
发明内容
本发明的目的在于提供一种芯片封装器件及封装方法，减小芯片之间的距离，最终减小终端产品的面积。
本发明的技术方案是一种芯片封装方法，包括以下步骤：
步骤S01：提供一承载板，所述承载板上设置有第一粘接层；
步骤S02：将多个芯片间隔放置于所述第一粘接层上；
步骤S03：采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；
步骤S04：移除所述承载板与第一粘接层；
步骤S05：在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内形成金属导体层以及芯片之间的互连电路；
步骤S06：对所述塑封芯片进行切割，形成多个模块。
进一步的，还包括：
步骤S07：提供一基板，所述基板上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应；
步骤S08：在所述金属垫结构上形成第二粘接层；
步骤S09：将所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述第二粘接层的材料为焊锡；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过回流炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述第二粘接层的材料为烧结材料；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烧结炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述第二粘接层的材料为导电胶；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烘烤，使所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述基板的材质为金属，具备导电功能或散热功能。
进一步的，所述承载板为圆形、正方形或长方形。
进一步的，在所述第一粘接层上，相邻芯片之间的距离大于等于50um。
进一步的，步骤S03中，所述塑封工艺为压力塑封工艺或注塑工艺，所述塑封层的材质为环氧树脂。
进一步的，所述塑封层的厚度等于所述芯片的厚度。
进一步的，所述塑封层的厚度小于所述芯片的厚度，在靠近所述基板的一侧所述塑封层的表面比所述芯片的表面低2um～10um。
进一步的，所述芯片的正面设置有电路，在所述芯片的背面设置有电极，所述芯片的背面放置于所述第一粘接层上。
进一步的，在步骤S05中，形成金属导体层以及芯片之间的互连电路的步骤包括：
采用溅射法在所述绝缘层上沉积金属种子层；
对所述开孔内的金属种子层进行电镀；
去除未被电镀的金属种子层。
相应的，本发明还提供一种芯片封装器件，采用上述的芯片封装方法进行封装，所述芯片封装器件包括：
基板，形成于所述基板上的多个间隔排列的第二粘接层；
多个芯片，分别位于所述第二粘结层上，所述芯片与所述第二粘结层一一对应；
位于所述基板上且包围所述芯片四周的塑封层；
位于所述塑封层以及所述芯片上的绝缘层；
位于所述绝缘层内的开孔，所述开孔延伸至所述芯片；
在所述开孔内形成的金属导体层以及芯片之间的互连电路。
与现有技术相比，本发明提供的芯片封装器件及封装方法具有以下有益效果：
1、通过将多个芯片间隔放置于设置有第一粘结层的承载板上，然后采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片，由此减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化；
2、本发明通过在绝缘层的开孔内溅射沉积金属种子层，并通过对金属种子层进行电镀形成金属导体层以及芯片之间的互联电路，金属间互联电阻比现有技术中的线连接的电阻小，从而降低了能量的损耗，提高了半导体器件的效率。
附图说明
图1为现有技术中IGBT模块的封装结构示意图。
图2为本发明一实施例所提供的芯片封装方法的流程图。
图3为本发明一实施例所提供的芯片的结构示意图。
图4～图12为本发明一实施例所提供的芯片封装方法的各步骤结构示意图。
具体实施方式
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例，本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应对此作为本发明的限定。
本发明本发明提供一种芯片封装方法及由该封装方法形成的芯片封装器件，所述芯片封装方法包括以下步骤：提供一承载板，所述承载板上设置有第一粘接层；将多个芯片间隔放置于所述第一粘接层上；采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；移除所述承载板与第一粘接层；在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内沉积金属形成金属导体层以及芯片之间的互连电路；对所述封装芯片进行切割，形成多个模块。
本发明通过将多个芯片间隔放置于设置有第一粘结层的承载板上，然后采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片，由此减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化。
图2为本发明一实施例所提供的芯片封装方法的流程图，如图2所示，本发明提出一种芯片封装方法，包括以下步骤：
步骤S01：提供一承载板，所述承载板上设置有第一粘接层；
步骤S02：将多个芯片间隔放置于所述第一粘接层上；
步骤S03：采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；
步骤S04：移除所述承载板与第一粘接层；
步骤S05：在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内沉积金属形成金属导体层以及芯片之间的互连电路；
步骤S06：对所述封装芯片进行切割，形成多个模块；
步骤S07：提供一基板，所述基板上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应；
步骤S08：在所述金属垫结构上形成第二粘接层；
步骤S09：将所述模块远离所述绝缘层的一侧粘接至所述基板。
图4～图12为本发明一实施例所提供的芯片封装方法的各步骤结构示意图，请参考图2所示，并结合图4～图12，详细说明本发明提出的芯片封装方法：
在步骤S01中，提供一承载板201，所述承载板201上设置有第一粘接层202，如图4所示。
在本实施例中，所述承载板201为圆形、正方形或长方形。所述第一粘结层202具有在高温或光照条件下其粘结性降低的性能。
在步骤S02中，将多个芯片100间隔放置于所述第一粘接层202上，如图5所示。相邻所述芯片100之间的距离大于等于50um，例如相邻所述芯片100之间的距离为50um、60um或70um。
所述芯片的正面设置有电路，所述芯片的背面设置有电极，所述芯片的背面放置于所述第一粘接层上，具体的，图3为本发明一实施例所提供的芯片的结构示意图，如图3所示，所述芯片100包括半导体沉底150，在所述半导体衬底150正面设置有绝缘层140，在所述绝缘层140内形成有凹槽，在所述凹槽内填充有金属，形成所述芯片100的栅极120与发射极130，作为芯片的输入端与输出端，在所述半导体衬底150的背面设置有集电极110。所述半导体衬底150的背面放置于所述第一粘接层上。可以理解的是，所述半导体衬底150的正面与背面是相对而言的，在本实施例中，以图5为例，以远离所述第一粘接层201的一面为半导体衬底150的正面，以靠近所述第一粘接层201的一面为半导体衬底150的背面。
在步骤S03中，采用塑封工艺在所述承载板201上形成塑封层203，所述塑封层203填满多个所述芯片100之间的间隙，形成塑封芯片200，如图6所示。
所述塑封工艺为压力塑封工艺或注塑工艺，所述塑封层203的材质为环氧树脂。使用环氧树脂，利用压力塑封工艺或注塑工艺将环氧树脂与芯片铸成一体，形成塑封芯片。所述环氧树脂形成塑封层203，所述塑封层203填满多个所述芯片之间的间隙，即所述塑封层203包围所述芯片100的四周，所述塑封层203与所述芯片100的上表面平齐。塑封芯片可以根据承载板101的形状，设计成圆形、正方形或长方形。所述塑封层203的厚度等于所述芯片100的厚度，或者，所述塑封层203的厚度也可以小于所述芯片100的厚度，例如，所述塑封层203的厚度比所述芯片100的厚度小2um～10um，使得所述芯片100背面的集电极110比所述塑封层203高出2um～10um。所述环氧树脂包含低热膨胀系数高分子材料，所述低热膨胀系数高分子材料的体积浓度为7ppm～9ppm，例如所述低热膨胀系数高分子材料的体积浓度为7ppm、8ppm或9ppm。所述低热膨胀系数高分子材料是指热膨胀系数小于4×10/℃的高分子材料。
在步骤S04中，移除所述承载板201与第一粘接层202，形成塑封芯片300，如图7所示。
对所述塑封芯片200进行加热，使所述第一粘结层202的粘结性降低，然后使用真空吸盘将所述塑封芯片200中的所述承载板201以及第一粘结层202移除，形成塑封芯片300。
在步骤S05中，在所述塑封芯片300上形成绝缘层301，在所述绝缘层301上形成开孔，在所述开孔内沉积金属形成金属导体层302以及芯片之间的互连电路303，如图8所示。
具体的，首先，在所述塑封芯片300上涂布第一层绝缘层301，绝缘层301中的绝缘材料为集成电路封装常用的紫外光照相制版材料。经过曝光，显影工艺，在对应于所述芯片100的栅极与发射极的位置处形成开孔，所述开孔延伸至所述芯片100的上表面。
然后，使用溅射法，在所述第一层绝缘层301上沉积金属种子层，厚度为0.2um～0.5um，目的是电镀金属，形成导线。
然后，在所述金属种子层上涂布光刻胶，进行曝光与显影，暴露出开孔的位置，对暴露出的所述金属种子层进行电镀，然后去除光刻胶，用酸刻蚀去除未被电镀的金属种子层，形成金属导体层302以及芯片之间的互连电路303。
还包括，在上述形成的器件表面涂布第二层绝缘层304，在特定位置开孔，形成绝缘层开孔305，作为与外部电路的接口。
在步骤S06中，对所述塑封芯片进行切割，形成多个模块400，如图9所示。所述模块400可以为单一芯片，也可以是多芯片的集成。在本实施例以两个芯片为例进行说明。
在步骤S07中，提供一基板500，所述基板500上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应，如图10所示。所述基板500的材质为金属，具备导电功能或散热功能。所述金属垫结构(图中未示出)在所述基板500上的位置与所述模块内的芯片一一对应。也就是说，如果模块内包含两个芯片，则所述基板上也设置有两个金属垫结构，所述金属垫结构之间的距离与所述芯片之间的距离相等。
在步骤S08中，在所述金属垫结构上形成第二粘接层501，如图11所示。所述第二粘接层501的材料为焊锡，或者低温烧结材料，或者导电胶，或本领域技术人员已知的其他材料。
在步骤S09中，将所述模块400远离所述绝缘层的一侧粘接至所述基板500，形成如图12所示的结构。首先，将所述模块400用贴片机放置于所述基板500上，所述模块400上远离所述绝缘层的一侧放置于所述基板500上设置有第二粘结层501的一侧上。然后，通过回流炉(所述第二粘接层501的材料为焊锡)或者烧结炉(所述第二粘接层501的材料为烧结材料)或者烘烤(所述第二粘接层501的材料为导电胶)，使所述模块400粘结于所述基板500上，形成芯片封装器件。
本发明通过将多个芯片100间隔放置于设置有第一粘结层202的承载板201上，然后采用塑封工艺在所述承载板201上形成塑封层203，所述塑封层203填满多个所述芯片100之间的间隙，形成塑封芯片200，从而能够减小芯片100之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化。并且，本发明通过在绝缘层的开孔内溅射沉积金属种子层，并通过对金属种子层进行电镀形成金属导体层302以及芯片之间的互联电路303，金属间互联电阻比现有技术中的线连接的电阻小，从而降低了能量的损耗，提高了半导体器件的效率。
相应的，本发明还提供一种芯片封装器件，采用上述的芯片封装方法进行封装。请参考图12所示，所述芯片封装器件包括：基板500，形成于所述基板500上的多个间隔排列的第二粘接层501；多个芯片100，分别位于所述第二粘结层501上，所述芯片100与所述第二粘结层501一一对应；位于所述基板500及所述第二粘接层501上且包围所述芯片100四周的塑封层203；位于所述塑封层203以及所述芯片100上的绝缘层301；位于所述绝缘层301内的开孔，所述开孔延伸至所述芯片100；在所述开孔内形成的金属导体层302以及芯片之间的互连电路303。还包括：位于所述绝缘层301及互联电路303之上的第二层绝缘层304，以及绝缘层开孔305。
本发明提供的芯片封装器件，芯片100之间的距离最小可以达到50um，与现有技术中的500um相比，大大减小了芯片之间的距离，从而最终减小了终端产品的面积，有利于实现终端产品的小型化。并且，在本发明提供的芯片封装器件中，采用金属互联代替了现有技术中的线连接，在很大程度上降低的连线的电阻，金属间互联电阻只有线连接电阻的30％～50％，从而降低了能量的损耗，提高了半导体器件的效率。
综上所述，本发明提供的芯片封装器件及封装方法，通过将多个芯片间隔放置于设置有第一粘结层的承载板上，然后采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片，由此减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化；本发明通过在绝缘层的开孔内溅射沉积金属种子层，并通过对金属种子层进行电镀形成金属导体层以及芯片之间的互联电路，金属间互联电阻比现有技术中的线连接的电阻小，从而降低了能量的损耗，提高了半导体器件的效率。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (14)

1.一种芯片封装方法，其特征在于，包括以下步骤：
步骤S01：提供一承载板，所述承载板上设置有第一粘接层；
步骤S02：将多个芯片间隔放置于所述第一粘接层上；
步骤S03：采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；
步骤S04：移除所述承载板与第一粘接层；
步骤S05：在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内形成金属导体层以及芯片之间的互连电路；
步骤S06：对所述塑封芯片进行切割，形成多个模块。
2.如权利要求1所述的芯片封装方法，其特征在于，还包括：
步骤S07：提供一基板，所述基板上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应；
步骤S08：在所述金属垫结构上形成第二粘接层；
步骤S09：将所述模块远离所述绝缘层的一侧粘接至所述基板。
3.如权利要求2所述的芯片封装方法，其特征在于，所述第二粘接层的材料为焊锡；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过回流炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
4.如权利要求2所述的芯片封装方法，其特征在于，所述第二粘接层的材料为烧结材料；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烧结炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
5.如权利要求2所述的芯片封装方法，其特征在于，所述第二粘接层的材料为导电胶；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烘烤，使所述模块远离所述绝缘层的一侧粘接至所述基板。
6.如权利要求2所述的芯片封装方法，其特征在于，所述基板的材质为金属，具备导电功能或散热功能。
7.如权利要求1所述的芯片封装方法，其特征在于，所述承载板为圆形、正方形或长方形。
8.如权利要求1所述的芯片封装方法，其特征在于，在所述第一粘接层上，相邻芯片之间的距离大于等于50um。
9.如权利要求1所述的芯片封装方法，其特征在于，步骤S03中，所述塑封工艺为压力塑封工艺或注塑工艺，所述塑封层的材质为环氧树脂。
10.如权利要求8所述的芯片封装方法，其特征在于，所述塑封层的厚度等于所述芯片的厚度。
11.如权利要求8所述的芯片封装方法，其特征在于，所述塑封层的厚度小于所述芯片的厚度，在靠近所述基板的一侧所述塑封层表面比所述芯片的表面低2um～10um。
12.如权利要求1所述的芯片封装方法，其特征在于，所述芯片的正面设置有电路，在所述芯片的背面设置有电极，所述芯片的背面放置于所述第一粘接层上。
13.如权利要求12所述的芯片封装方法，其特征在于，在步骤S05中，形成金属导体层以及芯片之间的互连电路的步骤包括：
采用溅射法在所述绝缘层上沉积金属种子层；
对所述开孔内的金属种子层进行电镀；
去除未被电镀的金属种子层。
14.一种芯片封装器件，其特征在于，采用如权利要求1～13中任一项所述的芯片封装方法进行封装，所述芯片封装器件包括：
基板，形成于所述基板上的多个间隔排列的第二粘接层；
多个芯片，分别位于所述第二粘结层上，所述芯片与所述第二粘结层一一对应；
位于所述基板上且包围所述芯片四周的塑封层；
位于所述塑封层以及所述芯片上的绝缘层；
位于所述绝缘层内的开孔，所述开孔延伸至所述芯片；
在所述开孔内形成的金属导体层以及芯片之间的互连电路。
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CN113036425B (zh) * 2021-03-01 2023-05-30 青岛歌尔智能传感器有限公司 集成封装及移动终端
CN113611616A (zh) * 2021-07-29 2021-11-05 矽磐微电子(重庆)有限公司 半导体封装方法
CN113611616B (zh) * 2021-07-29 2023-12-26 矽磐微电子(重庆)有限公司 半导体封装方法

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