CN108330518B - Method and apparatus for filling an interconnect structure - Google Patents

Abstract

The application relates to a method and apparatus for filling an interconnect structure. The present invention provides methods, apparatus and systems for depositing copper and other metals. In some embodiments, a wafer substrate is provided to the apparatus. The wafer substrate has a surface with field regions and a feature. Plating a copper layer onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the features. Implementations of the disclosed method, apparatus and system allow for void-free bottom-up filling of features in a wafer substrate.

Description

Method and apparatus for filling an interconnect structure

Related information of divisional application

The scheme is a divisional application. The parent application of this division is the invention patent application with application date of 2012, 04/13, application number of 201210109495.2 entitled "method and apparatus for filling interconnect structures".

Cross reference to related applications

This application claims priority to the following applications: united states patent application No. 13/108,894 filed on 16/5/2011, united states patent application No. 13/108,881 filed on 16/5/2011, and united states provisional patent application No. 61/476,091 filed on 15/4/2011; all three applications are incorporated herein by reference.

Technical Field

The present invention relates to semiconductor processing technology, and in particular, to a method and apparatus for filling an interconnect structure.

Background

Interconnects may be formed on integrated circuits using damascene processing (semiconductor processing techniques). Damascene processing involves forming embedded metal lines in trenches and vias formed in a dielectric layer. In a typical damascene process, a pattern of trenches and vias is etched in a dielectric layer of a semiconductor wafer substrate. A barrier layer, such as tantalum (Ta), tantalum nitride (TaN), or a TaN/Ta bilayer, is then deposited onto the wafer surface by, for example, a Physical Vapor Deposition (PVD) process. The trenches and vias are then filled with copper, typically using an electroplating process. Since electroplating typically needs to occur over a conductive layer, a copper seed layer may first be deposited over the barrier layer by means of a Chemical Vapor Deposition (CVD) or PVD process. Copper may then be electroplated onto the copper seed layer.

Disclosure of Invention

The present invention provides methods, apparatus and systems for plating copper and other metals. According to various embodiments, the method involves plating a copper layer onto a wafer substrate. The copper layer may be annealed, which may redistribute copper from several regions of the wafer substrate to several features in the wafer substrate. In some cases, plating and subsequent annealing serve as one cycle of a multi-cycle deposition process. Thus, the deposition process may involve two or more plating/annealing cycles performed in series.

In some implementations, a method includes providing a wafer substrate to an apparatus. The wafer substrate includes a surface having field regions and a feature. Plating a copper layer onto the surface of the wafer substrate. The copper layer is then annealed, wherein the annealing redistributes copper from several regions of the wafer substrate to the features.

In some implementations, the surface of the wafer further includes a liner layer over the field region and the feature. In some embodiments, the liner layer may be annealed in a reducing atmosphere prior to plating the copper layer. The liner layer may be selected from the group consisting of ruthenium (Ru), cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), gold (Au), and rhodium (Rh).

In some implementations, a method includes providing a wafer substrate to an apparatus. The wafer substrate includes a surface covered with a liner layer, the surface including field areas and a feature. Plating a copper layer onto the surface of the wafer substrate with an electroplating process. The copper layer is then annealed, wherein the annealing redistributes copper from several regions of the wafer substrate to the features. The annealing may be performed in a reducing atmosphere at a temperature of about 150 ℃ to 400 ℃ for a duration of about 30 seconds to 180 seconds.

In some implementations, an apparatus includes a plating chamber, a wafer substrate holder, a component, and a controller. The plating chamber is configured to hold an electrolyte. The wafer substrate holder is configured to hold a wafer substrate in the plating chamber. The wafer substrate includes a surface having edge regions, field regions, and a feature.

The element includes an ionically resistive body having perforations therein such that the perforations do not form communicating channels within the body. The perforations allow the electrolyte to be transported through the element. The element is positioned to have a surface facing the surface of the wafer substrate, wherein the surface of the element is within about 10 millimeters of the surface of the wafer substrate when the wafer substrate is held by the wafer substrate holder. Openings of substantially all of the perforations in the ionically resistive body on the surface of the element facing the surface of the wafer substrate have a major dimension of no greater than about 5 millimeters. The element has a porosity of about 1% to 3%.

The controller includes instructions for performing a process. The process comprises the following steps: plating a copper layer onto the surface of the wafer substrate using the plating chamber; and annealing the copper layer. Annealing the copper layer redistributes copper from regions of the wafer substrate to the features.

In some implementations, a non-transitory computer machine readable medium includes program instructions for controlling an apparatus. The program instructions include code for operations comprising: transporting the wafer substrate to a module associated with the apparatus; plating a copper layer onto the surface of the wafer substrate; and annealing the copper layer. The wafer substrate includes a surface having field regions and a feature. Annealing the copper layer redistributes copper from regions of the wafer substrate to the features.

These and other aspects of implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

Drawings

Fig. 1 shows an example of a flow chart illustrating a process for plating copper.

Fig. 2A and 2B show examples schematically illustrated in cross-section of stages in a method of plating copper.

Figure 3 shows an example of a flow chart illustrating a process for plating copper.

Fig. 4A-4G show examples of schematic diagrams of an electrical fill system.

Fig. 5 shows an example of a cross-sectional schematic of an electroplating apparatus.

Fig. 6A and 6B show examples of views of one-dimensional resistive elements.

Detailed Description

Introduction to the design reside in

In the following detailed description, numerous specific embodiments are set forth in order to provide a thorough understanding of the present invention. However, as will be apparent to one skilled in the art, the present invention may be practiced without these specific details or by using alternate elements or processes. In other instances, well-known processes, procedures, and components have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

In this application, the terms "semiconductor wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of a number of stages on which the integrated circuit is fabricated. The workpieces on which the disclosed operations may be performed may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the present invention include various articles such as printed circuit boards.

Current techniques for metalizing integrated circuits include depositing barrier and liner layers via a Physical Vapor Deposition (PVD) process, seeding the liner layers with copper (Cu) deposited via the PVD process, and then electroplating copper using a process that provides void-free bottom-up fill. However, electroplating techniques do not readily scale to feature sizes below about 18 nanometers. At these dimensions, the opening of small features may be reduced to about 2-4 nanometers, for example, prior to the electroplating process due to the coating of the barrier layer and the liner layer. This makes the features very high aspect ratio features that may not allow void-free bottom-up filling with some electroplating processes.

Implementations disclosed herein can overcome the difficulty of filling very small features by sequentially plating copper layers and redistributing the copper to fill the features. Such features may be below about 100 nanometers in size and have high aspect ratios. Implementations of methods and apparatus to fill small integrated circuit features that may be coated with barrier/liner layers are disclosed herein. In some embodiments, the process operation may completely fill the features with copper. Furthermore, some disclosed implementations do not use a copper seed layer deposited by means of a Physical Vapor Deposition (PVD) process.

In some embodiments, the copper layer is plated directly onto the liner layer of the wafer substrate. For example, the liner layer can be a ruthenium layer or other suitable conductive barrier metal layer. The plated copper layer may then be annealed. In some embodiments, the annealing may be performed in a reducing atmosphere (e.g., forming gas) at about 150 ℃ to 400 ℃ for about 30 seconds to 180 seconds. The annealing may redistribute copper in the copper layer into small features. The annealing can also maintain any subsequently exposed regions of the copper layer and liner layer in a reduced state. The copper plating and annealing process may be repeated from about 2 to 8 times in order to gradually and void-free fill small features, such as features having a width or diameter from about 8 to 100 nanometers. In some implementations, the thickness of each plated copper layer can be about 2 to 20 nanometers, depending on feature size and aspect ratio. The wafer substrate may then be plated using a conventional electroplating process to fill the larger features prior to Chemical Mechanical Planarization (CMP).

In some embodiments, resistive elements are used in electroplating apparatus to help mitigate or eliminate "end effects" when plating copper layers. End effects can increase the plating thickness near the edge of the wafer with a wafer surface having a sheet resistance greater than about 1 ohm/square, which is undesirable. In some implementations, the resistive element includes a number of isolated and unconnected vias in close proximity to the wafer, thereby governing the overall resistance of the electroplating apparatus.

Method of producing a composite material

Fig. 1 shows an example of a flow chart illustrating a process for plating copper. At block 102 of the method 100, a wafer substrate is provided. The wafer substrate may include a feature and field regions. The features may have varying widths or diameters and aspect ratios. The aspect ratio of a feature is the ratio of the height of the vertical sidewalls of the feature to the width of the feature.

For example, the width or diameter of a feature may be about 100 nanometers, about 90 nanometers, about 60 nanometers, about 30 nanometers, about 18 nanometers, about 15 nanometers, about 12 nanometers, about 8 nanometers, less than about 100 nanometers, or less than about 18 nanometers. Other processes for depositing copper may be faster and more efficient for features having larger widths than embodiments of the method 100. However, the method 100 may be used to fill a portion or a feature of such larger width feature with copper.

In some implementations, the wafer substrate may be a wafer substrate that has been subjected to a damascene process, and the features in the wafer substrate may be line features or via features etched in a dielectric layer. For example, the aspect ratio of features etched in the dielectric layer may be about 10:1 or greater. In some implementations, the dielectric layer can be covered with a barrier layer, and the barrier layer can be covered with a liner layer. In other implementations, the barrier and liner may be a single layer of one material. That is, the liner layer may exhibit barrier layer properties such that separate barrier layers and liner layers are not required. For example, the aspect ratio of features etched in the dielectric layer covered with the barrier/liner layer may be about 12:1, about 15:1, or greater than about 12: 1. In other embodiments, the feature may be a contact via having an aspect ratio of about 15:1, about 20:1, or greater than about 15: 1.

For example, the dielectric layer may be covered with a tantalum nitride (TaN) barrier layer. The TaN barrier layer may be about 2 nanometers thick. The TaN barrier layer may be deposited by means of a Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process. In other implementations, the barrier layer may be tantalum (Ta), tungsten (W), tungsten nitride (WN), titanium (Ti), or titanium nitride (TiN), for example. The barrier layer may be covered with a ruthenium (Ru) liner layer. The Ru liner layer can have a thickness of about 2 nm. The Ru liner layer can be deposited by means of a CVD process. In other implementations, the liner layer can be cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), gold (Au), or rhodium (Rh), for example.

In some embodiments, the liner layer is selected such that copper wets the liner layer. Wetting is the ability of a liquid to maintain contact with a solid surface. Liquid wetting a solid surface spreads across the surface. Liquids that do not wet a solid surface form droplets or spheres on the surface to minimize contact with the surface. The degree of wetting of a liquid in contact with a solid surface is determined by the adhesive forces (i.e., the forces between the liquid and the solid) and cohesive forces (i.e., the forces within the liquid). For example, copper-wetting metals include Ru, Pt, Pd, Au, and Rh based on the oxidation behavior of the metal.

At block 104, the liner layer on the surface of the substrate is annealed. In some embodiments, the liner layer may be annealed in a reducing atmosphere to remove contaminants or reduce any native oxides of the metal. For example, the contaminants may include carbon that adsorbs to the surface of the backing layer. Removal of contaminants or reduction of native oxides may assist in the formation of a continuous copper layer in the plating process described below.

In some embodiments, the reducing atmosphere comprises a forming gas, atomic hydrogen, or other chemical reducing agent. The forming gas is a mixture of hydrogen (hydrogen mole fraction is variable) and nitrogen. In some embodiments, the liner layer may be annealed at about 150 ℃ to 400 ℃ for about 30 seconds to 180 seconds. For example, the liner layer may be annealed at about 225 ℃ for about 90 seconds in a forming gas. In other embodiments, the liner layer may be treated under other reducing conditions (e.g., hydrogen plasma or atomic hydrogen).

At block 106, a copper layer is plated on the liner layer. In some embodiments, the copper layer is plated by means of an electroplating process, and in other embodiments, the copper layer is plated by means of an electroless plating process. In some embodiments, the plating process in block 106 may be performed at about room temperature (i.e., about 20 ℃ to 29 ℃ or about 25 ℃).

In some implementations, the thickness of the plated copper layer can be about 20% to 80% of the width or diameter of the features on the wafer substrate. For example, the copper layer may have a thickness of about 2 to 20 nanometers or about 2 to 10 nanometers. In some implementations, the copper layer has a thickness such that there is sufficient copper to fill about 10% to 50% of the feature with each annealing operation at block 110 described below. In some embodiments, the copper layer can form a substantially conformal layer on both the liner layer in the feature of the wafer substrate and on the liner layer over the field area.

In some embodiments, the plated copper layer may be a continuous copper layer. That is, the copper layer may form a continuous layer over the liner layer. In other embodiments, the copper may be discontinuous. That is, several areas of the liner layer may not be covered with the copper layer. For example, a copper layer may cover the liner layer except for an area over a portion of the field area of the wafer substrate.

In some embodiments, the copper layer may exhibit some preferential growth within the feature, and in other embodiments, the copper layer may exhibit a somewhat slower growth within the feature.

In some embodiments, the copper layer may comprise an alloying element; that is, the liner layer may be plated with a copper alloy layer. The alloying element may have an atomic mass of about 50 to 210. For example, the alloying element can be chromium, iron, cobalt, nickel, zinc, ruthenium, rhodium, palladium, silver, indium, tin, tellurium, platinum, gold, or lead. The copper layer may include one or more of these alloying elements. In some embodiments, the copper layer comprises about 0.1 wt% to 5 wt% of one or several alloying elements. As explained below, the alloying elements may provide some protection against damage resulting from electromigration.

As described above, in some embodiments, the copper layer may be plated by means of an electroplating process. In some implementations, the electroplating solution and hardware can allow for uniform across-wafer deposition of copper. For example, the plating solution may be a dilute, highly complex copper plating solution. With such electroplating solutions, copper nucleation on the resistive wafer substrate can be uniform and continuous. A dilute highly complex copper electroplating solution is further described in U.S. patent No. 7,799,684, which is incorporated herein by reference. The electroplating solution may also include additives, such as polymers, that can enhance the plating rate in smaller features to aid in filling these features.

Other methods of depositing copper by means of an electroplating process are described in the following applications: U.S. patent application No. 12/075,023 entitled "TWO-step COPPER ELECTROPLATING PROCESS with anneal FOR UNIFORM cross-WAFER DEPOSITION AND VOID-free filling ON RUTHENIUM-COATED WAFERs" (TWO stepp aper ELECTROPLATING PROCESS WITH ANNEAL FOR UNIFORM cross-WAFER DEPOSITION AND VOID-free filling FREE FILLING ON RUTHENIUM COATED WAFER) "AND filed ON 6.3.2008, AND U.S. patent application No. 12/785,205 entitled" COPPER ELECTROPLATING PROCESS FOR UNIFORM cross-WAFER DEPOSITION AND VOID-free filling ON SEMI-NOBLE METAL COATED WAFERs "(COPPER ELECTROPLATING PROCESS FOR UNIFORM cross-WAFER DEPOSITION AND VOID-free filling FREE FILLING ON SEMI-METAL COATED WAFER coating WAFER)" AND filed ON 21.5.2010, both of which are incorporated herein by reference. The apparatus for electroplating copper is described further below.

As described above, in some embodiments, copper may be plated by means of an electroless plating process. In some cases, electroless plating (also known as chemical or autocatalytic plating) may be performed without the use of external power. With electroless plating processes, the end effects sometimes present in electroplating processes are absent due to the absence of current delivery to the wafer substrate from an external source. In some embodiments, copper layer uniformity is more easily achieved by means of an electroless plating process. Electroless plating processes and apparatus are further described in U.S. patent nos. 6,664,122, 6,815,349, 7,456,102, 7,897,198, all of which are incorporated herein by reference.

At block 108, the wafer substrate is rinsed and dried. In some embodiments, the wafer substrate may be rinsed and dried in a Spin Rinse Dryer (SRD). The process and apparatus for rinsing and drying wafer substrates is further described in U.S. patent No. 7,033,465, which is incorporated herein by reference.

At block 110, the copper layer is annealed such that copper is redistributed from several regions of the wafer substrate to the features. The region of the wafer substrate may include a number of field regions. In some implementations, copper is redistributed from the field area of the wafer substrate to the features. In some implementations, copper is redistributed from several areas of the wafer substrate to the bottom of the features. In some embodiments, the copper layer is annealed at about 150 ℃ to 400 ℃ for about 30 seconds to 180 seconds. In some embodiments, the annealing may be performed under a reducing atmosphere. The reducing atmosphere can be any reducing atmosphere that maintains the liner layer in an oxide-free state and prevents oxidation of the copper. For example, in some embodiments, the reducing atmosphere comprises a forming gas, atomic hydrogen, or other chemical reducing agent.

Heating the copper layer to anneal it can be accomplished by a number of different techniques. For example, a copper layer may be heated by passing an electric current through the copper layer (i.e., resistive heating). The copper layer may also be heated by means of Ultraviolet (UV) light or Infrared (IR) light. In some implementations, the wafer substrate may be heated continuously or periodically during a process cycle.

In some embodiments, annealing the copper layer causes copper plated in the feature to redistribute to the base of the feature. For example, copper plated onto the sides of a feature may be redistributed to the bottom of the feature. In some cases, the plated copper is drawn from the field areas of the wafer substrate into the features.

While not wishing to be bound by any theory, it is believed that the redistribution of copper to the features and to the base of the features is a result of capillary effects. For example, if the features are sufficiently small, the surface tension of the copper (which results from cohesion within the copper) and adhesion between the copper and the liner layer in the features can act to draw the copper into the base of the features.

At block 112, it is determined whether the aspect ratio of the feature is sufficient. If the aspect ratio of the feature is sufficient, the method 100 ends. If the aspect ratio of the feature is insufficient, operations 106 through 110 are repeated until the aspect ratio is sufficient. In some embodiments, operations 106 to 110 are repeated from about 2 to 8 times. In some implementations, the thickness of the plated copper layer and the annealing temperature and duration may vary for the process sequence of operations 106-110, but in general the thickness of the plated copper layer is about 2-20 nanometers and the annealing temperature is about 150-400 ℃ for about 30-180 seconds.

A sufficient aspect ratio of a feature may be the following aspect ratio: for the aspect ratio, the bulk layer plating process may be performed without forming any voids in the features. For example, a sufficient aspect ratio of a feature may be about 2:1 or less, about 2:1, or about 1: 1. If the bulk layer plating process is performed with a wafer substrate having high aspect ratio features prior to performing an implementation of method 100, copper metal may be plated onto the wafer substrate such that the openings of the features are plugged with copper with voids beneath the plugs.

After the features in the wafer substrate are filled to a sufficient aspect ratio with copper, the wafer substrate may be plated with a copper bulk layer using a bulk electroplating process. In some embodiments, the copper bulk layer may have a thickness of about 0.2 to 0.5 nanometers. Plating a copper bulk layer onto a wafer substrate by means of a bulk electroplating process can improve the plated film topography prior to Chemical Mechanical Planarization (CMP). Subsequent processing of the wafer substrate after CMP follows a standard damascene process flow known to those skilled in the art.

Thus, embodiments of the method 100 are used to fill features with copper, thereby ensuring bottom-up filling of the features so that voids are not formed. In some embodiments, operations 106 through 110 of method 100 may be repeated until the features are filled. Alternatively, operations 106 through 110 of method 100 may be repeated until the features are filled with copper to a level such that a bulk plating process may be performed without forming voids.

In some implementations, the number of times the process operations in blocks 106-110 are repeated to achieve a desired copper level in the feature is minimized. For example, a desired copper level in the feature may be reached with 2 or 3 iterations of the process operations in blocks 106-110. For example, the number of iterations of the process operation may be minimized by plating a copper layer with an optimal thickness in block 106. The copper layer should not be too thick because if the copper layer is too thick, the feature openings can become plugged with copper during the plating process. However, the thicker the plated copper layer, the more copper will be redistributed to the features over several areas of the wafer substrate (including the field areas) during the anneal in block 110. Thus, plating a thick copper layer is useful in providing copper that is capable of being redistributed to the feature, but the copper layer should not be so thick that it plugs the feature.

For example, the wafer substrate may include 20 nanometer features. In block 106, a copper layer about 5 nanometers thick may be plated, followed by rinsing and drying in block 108 and annealing in block 110. The features may be filled with copper to the appropriate level with 2 or 3 iterations of operations 106 through 110.

In some implementations, the plating process in block 106 can be performed at a high temperature. For example, the electroplating process may be performed using an electroplating solution employing a higher boiling point solvent at a temperature exceeding the boiling point of water. As another example, the electroless plating process may be performed at a temperature of about 50 ℃ to 90 ℃. In some implementations, performing the plating process at an elevated temperature can redistribute, at least in part, copper to the features during the plating process.

Fig. 2A and 2B show examples schematically illustrated in cross-section of stages in a method of plating copper. In fig. 2A, 200 illustrates a wafer substrate having features 204 and field regions 206. A copper layer 202 has been plated onto the wafer substrate as in block 106 in fig. 1. 220 illustrate the wafer substrate after the annealing process, as in block 110 of fig. 1. As shown in 220, the copper layer 202 is redistributed to the bottom of the feature 204, with no copper remaining in the field regions 206.

In fig. 2B, which is similar to fig. 2A, 200 illustrates a wafer substrate having features 204 and field regions 206. A copper layer 202 has been plated onto the wafer substrate as in block 106 in fig. 1. 240 illustrate the wafer substrate after the annealing process, as in block 110 of fig. 1. As shown in 240, the copper layer 202 is redistributed to the bottom of the feature 204, with some copper remaining in the field regions 206 and on the sidewalls of the feature 204. The differences in the amount of copper redistribution, including whether copper remains in the field areas, may be due to, for example, annealing time, annealing temperature, or different wafer substrate materials to which the copper is deposited.

Figure 3 shows an example of a flow chart illustrating a process for plating copper. The method 250 shown in fig. 3 is similar to the method 100 shown in fig. 1, with a plating cap layer added in the method 250.

At block 260 of the method 250, a capping layer is plated onto the copper layer after determining whether the aspect ratio of the feature is sufficient. For example, the capping layer may comprise a copper layer (i.e., a copper alloy layer) having an alloying element. The copper alloying element can comprise any of the alloying elements described above. The copper alloying elements may help to reduce electromigration of the copper, which increases the electromigration lifetime of the semiconductor device. The capping layer may also comprise a metal other than copper that assists in reducing electromigration of the copper.

In some implementations, the composition of the copper layer can be varied with each plating operation in block 106. For example, in a first plating operation, a substantially pure copper layer may be plated. In the second plating operation, a copper layer containing about 2.5 wt% of an alloying element may be plated. In the third plating operation, a copper layer containing about 5 wt% of an alloying element may be plated. Thus, the composition of the copper layer can be gradually increased to the composition of the cap layer.

In an embodiment of the method 100 where a copper layer having an alloying element is plated on a wafer substrate throughout the method 100, after the copper bulk layer is plated onto the wafer substrate using a bulk electroplating process, the wafer substrate may be treated to cause at least some of the alloying element to diffuse into the bulk layer. In some embodiments, the treatment may be a thermal treatment. The copper alloying element diffused into the bulk layer may also assist in reducing electromigration of the copper, thereby increasing the electromigration lifetime of the semiconductor device.

Although the above method is described with respect to copper plating and redistribution, the method may also be applicable to the plating and redistribution of other metals, including, for example, tin (Sn), silver (Ag), and gold (Au).

Device

Implementations of suitable apparatus configured to implement the methods described herein include hardware for implementing process operations and a system controller having instructions for controlling the process operations. An apparatus configured to allow efficient cycling of a wafer substrate through sequential plating, rinsing, drying, and annealing process operations is suitable for implementations used in a manufacturing environment. The apparatus may include a tool and/or chamber configured to perform more than one process operation. For example, the apparatus may include a plating chamber and an annealing chamber that are also configured to rinse and dry the wafer substrate. As another example, the apparatus can include a plating chamber and a chamber configured to rinse, dry, and anneal a wafer substrate. A particular implementation of a tool configured to rinse, dry and anneal wafer substrates may be a Spin Rinse Dryer (SRD) in combination with an annealing station.

Fig. 4A-4G show examples of schematic diagrams of an electrical fill system. Fig. 4A shows an example of a schematic diagram of an electrical fill system 300. The electro-fill system 300 includes three separate electro- fill modules 302, 304, and 306. The electro-fill system 300 also includes three separate modules 312, 314, and 316 configured for various process operations. For example, in some implementations, modules 312 and 316 may be SRDs and module 314 may be an annealing station. In other implementations, modules 312, 314, and 316 may be post-electro-fill modules (PEMs) that are each configured to perform functions such as edge bevel removal, backside etching, and acid cleaning of a wafer after the wafer has been processed by one of the electro- fill modules 302, 304, and 306.

The electro-fill system 300 includes a central electro-fill chamber 324. The central electrofill chamber 324 is a chamber that holds a chemical solution that is used as a plating solution in the electrofill module. The electro-fill system 300 also includes a dosing system 326 that can store and deliver chemical additives for the electroplating solution. The chemical dilution module 322 may store and mix chemicals to be used as, for example, an etchant in the PEM. The filtration and pumping unit 328 may filter and pump the electroplating solution for the central electro-fill chamber 324 to the electro-fill module.

The anneal station 332 may be used to anneal the wafer as a pre-treatment. The anneal station 332 may also be used to anneal the wafer to achieve copper redistribution, as described above. The annealing station 332 may include several stacked annealers, such as five stacked annealers. The annealing devices may be arranged in the annealing station 332 on top of each other, in separate stacks, or in other multi-device configurations.

The system controller 330 provides the electronic and interface controls needed to operate the electro-fill system 300. The system controller typically includes one or more memory devices and one or more processors configured to execute instructions such that the apparatus may perform a method in accordance with implementations described herein. A machine-readable medium containing instructions for controlling the operation of a process according to implementations described herein may be coupled to a system controller. The system controller 330 may also include a power supply for the electrical fill system 300.

The handoff tool 340 may select a wafer from a wafer cassette (e.g., cassette 342 or cassette 344). The cassettes 342 or 344 may be Front Opening Unified Pods (FOUPs). A FOUP is a housing designed to securely and safely hold wafers in a controlled environment and allow the wafers to be removed for processing or measurement by tools equipped with appropriate load ports and robotic handling systems. The handoff tool 340 may use a vacuum attachment or some other attachment mechanism to hold the wafer.

The delivery tool 340 may interface with the annealing station 332, cassettes 342 or 344, transfer station 350, or aligner 348. The handoff tool 346 may access the wafer from the transfer station 350. The transfer station may be a slot or location where the handoff tools 340 and 346 may pass the wafer back and forth without passing through the aligner 348. However, in some embodiments, to ensure that the wafer is properly aligned on the handoff tool 346 for accurate delivery to the electro-fill module, the handoff tool 346 may align the wafer with the aligner 348. The handoff tool 346 may also deliver the wafer to one of the electro- fill modules 302, 304, or 306 or one of the three separate modules 312, 314, and 316 configured for various process operations.

An example of process operation according to the method described above may proceed as follows: (1) plating a copper layer onto the wafer in an electro-fill module 304; (2) rinsing and drying the wafer in the SRD in block 312; and (3) annealing the wafer to effect copper redistribution in block 314. The process operations may be repeated if further copper electroplating for copper redistribution is required. After the copper layer and anneal process is completed, a cap layer may be plated onto the wafer in the electrofill module 302. A copper body layer may be plated onto the wafer in the electro-fill module 306. The electro- fill modules 302, 304, and 306 may also be used interchangeably by providing the electro-fill modules with an electroplating solution appropriate for the process to be performed. For example, the electro-fill module 302 may be used for copper electroplating with one electroplating solution. The plating solution may be drained from the electro-fill module 302 and replaced with a plating solution for use in bulk copper plating in subsequent process operations.

In some embodiments, module 314 may anneal the wafer by means of hot plate resistive electrical heating of the copper layer itself. In some implementations, the module 314 can include an Ultraviolet (UV) light source or an Infrared (IR) light source to anneal the wafer. In some implementations, the electrical fill system 300 can include a means to constantly heat the wafer during the plating operation. This may be done through the backside of the wafer.

As noted above, an apparatus configured to allow a wafer substrate to be efficiently cycled through sequential plating, rinsing, drying, and annealing process operations is suitable for implementations used in a manufacturing environment. To accomplish this, the module 312 may be configured as a rotary rinse dryer and annealing chamber. With this module 312, the wafer would only need to be transported between the electro-fill module 304 and the module 312 for copper plating and annealing operations. Further, in some embodiments, the electrical fill system 300 can maintain the wafer substrate in a vacuum environment or an inert gas atmosphere to assist in avoiding contamination of the wafer.

Fig. 4B-4G show examples of simplified schematic diagrams of alternative electrical fill systems. Note that some or all of the features included in the electrical fill system 300 shown in fig. 4A may be included in the electrical fill system shown in fig. 4B-4G. For example, the electro-fill system shown in fig. 4B-4G may include a post-electro-fill module (PEM) for edge bevel removal or other operations. Fig. 4B-4G show primarily examples of some of the different possible module configurations.

The electro-fill system 400 shown in fig. 4B includes four plating/rinsing modules 402 and four drying/annealing modules 404. The electro-fill system 400 also includes a handoff tool 406, which may be similar to the handoff tools 340 and 346 described above. The four plating/rinse modules may each include equipment configured to plate a wafer and rinse the wafer. The four drying/annealing modules may each include an apparatus configured to dry and anneal a wafer. In some implementations, the electrical fill system 400 can include fewer modules (e.g., four modules or six modules) or more modules (e.g., ten modules or twelve modules). Further, in some implementations, each of the eight modules shown in the system 400 can include two, three, or more modules stacked on top of each other. For example, the plating/rinsing module 408 may include three plating/rinsing modules stacked on top of each other, and the drying/annealing module 410 may include three drying/annealing modules stacked on top of each other.

The modules in the electrical fill system 400 can include equipment for different operations, as described herein. For example, four plating/rinsing modules 402 may instead be plating modules, and four drying/annealing modules may instead be rinsing/drying/annealing modules. As another example, some modules may be rinse/dry modules. In some implementations, the rinse/dry module may include components configured to rapidly rotate the wafer.

The electro-fill system 430 shown in fig. 4C includes four plating/rinsing modules 402 and four drying/annealing modules 404. The electrical fill system 430 also includes a handoff tool 406. The electrical fill system 430 is similar to the electrical fill system 400, with one difference being that all plating/rinsing modules 402 are on one side of the electrical fill system 430 and four drying/annealing modules 404 are on the other side. Different configurations of modules may be more efficient in quickly processing wafers. For example, minimizing the transfer distance and/or time between two modules may assist in quickly processing wafers.

Similar to the modules in the electro-fill system 400, the modules in the electro-fill system 430 may include equipment for different operations. For example, four plating/rinsing modules 402 may instead be plating modules, and four drying/annealing modules may instead be rinsing/drying/annealing modules.

The electro-fill system 460 shown in fig. 4D includes eight plating/rinsing/drying modules 462 and eight annealing modules 464. The electrical fill system 460 also includes a handoff tool 406. The eight plating/rinse/dry modules may each include an apparatus configured to plate a wafer, rinse the wafer, and dry the wafer. The eight annealing modules may each include an apparatus configured to anneal wafers. As shown, the annealing modules 464 are in two sets of annealing modules, where each set of annealing modules includes four annealing modules stacked on top of each other.

The electro-fill system 470 shown in fig. 4E includes four plating modules 472 and four rinse/dry/anneal modules 474. The electro-fill system 470 also includes a handoff tool 406. The four plating modules may each include an apparatus configured to plate a wafer. The four rinse/dry/anneal modules may each include an apparatus configured to rinse the wafer, dry the wafer, and anneal the wafer.

The electro-fill system 480 shown in fig. 4F includes four plating modules 472, four annealing modules 464, four rinse/dry modules 482, and four overburden plating modules 484. The electro-fill system 480 also includes a handoff tool 406. As shown, the plating module 472, rinse/dry module 482, and annealing module 464 are stacked on top of one another, forming four sets of these modules. As described herein, the plating module 472 can be used to plate copper that will be redistributed by annealing in the annealing module 464. As also described herein, the overplate plating module 484 may be used to plate a copper layer.

The electro-fill system 490 shown in fig. 4G includes eight plating modules 472, eight annealing modules 464, eight rinse/dry modules 482, and two overburden plating modules 484. The electro-fill system 480 also includes a handoff tool 406. As shown, two plating modules 472 are stacked on top of each other, forming four groups of these modules. As described herein, the plating module 472 can be used to plate copper that will be redistributed by annealing in the annealing module 464. Two rinse/dry modules 482 are also stacked on top of each other to form four groups of these modules. Eight annealing modules 464 are all stacked on top of each other to form a stack of these modules. Two overloaded plating modules 484 are also stacked on top of each other, forming a stack of these modules. As also described herein, the overplate plating module 484 may be used to plate a copper layer.

In some implementations of the methods described above, copper is plated onto the liner layer having a high sheet resistance. For example, a thin ruthenium layer can have a sheet resistance of about 100-200 ohms/square. The sheet resistance of a layer increases as its thickness decreases. When the sheet resistance of a layer is high, there is a voltage drop (called end effect) between the edge of the wafer (where electrical contact is made in the electroplating apparatus) and the center of the wafer. This resistance drop continues during the electroplating process until sufficient plating increases the conductance across the wafer and reduces the voltage drop. The resistance drop results in a larger voltage driving the plating reaction near the wafer edge and thus a faster plating rate at the wafer edge. Thus, the plated layer may have a concave profile with an increased thickness near the edge of the wafer relative to the center of the wafer. This end effect may substantially increase the plated layer thickness near the wafer edge of a wafer having a seed layer or liner layer with a sheet resistance greater than about 1 ohm/square and may cause the edge thickness to grow progressively larger as the sheet resistance further increases. In general, the effect of the end effect in producing thickness variation is mainly concentrated at the outer 15mm to 30mm of the wafer diameter.

When plating is performed on a surface having a high sheet resistance, a plating solution having low conductivity may be used. As the conductivity of the plating solution decreases, the relative voltage drop between the center of the wafer and the edge of the wafer becomes smaller compared to the overall voltage drop across the plating vessel. The thickness profile of the plated metal is improved because the voltage driving the reaction at the edge of the wafer is not much greater relative to the voltage at the center of the wafer. In some embodiments, the low conductivity (high resistivity) plating solution has a resistivity greater than about 200 Ω -cm or greater than about 1000 Ω -cm, which is significantly higher than conventional plating solutions having a resistivity of about 2 Ω -cm to 20 Ω -cm. However, the electroplating solution may only have a resistivity up to a certain level and still contain enough copper so that copper can be plated with the electroplating solution.

Other ways to reduce the end effect include adding auxiliary cathodes, shields, and resistive elements to the electroplating apparatus. All of these devices and techniques are discussed further below.

Fig. 5 shows an example of a cross-sectional schematic of an electroplating apparatus. The plating apparatus 101 may be included in any of the above-described electrofill modules or plating modules. The electroplating apparatus 101 includes a plating vessel 103 containing an electroplating solution shown at a level 105. The wafer 107 may be immersed in the electroplating solution and held by a "clamshell" holding fixture 109 mounted on a rotatable spindle 111. The rotatable spindle allows the clamshell 109 to rotate with the wafer 107. Clamshell plating apparatus is further described in U.S. patent No. 6,156,167 and U.S. patent No. 6,800,187, both of which are incorporated herein by reference. Of course, wafer holders other than clamshell-type clamps may be employed.

An anode 113 is disposed within the electroplating vessel 103 beneath the wafer 107 and separated from the wafer area by an anode membrane 115 (which in some embodiments is an ion selective membrane). The area under the anodic membrane is commonly referred to as the "anode chamber" and the electrolyte in this chamber is referred to as the "anolyte". The anode membrane 115 allows ionic communication between the anode and cathode regions of the plating vessel while preventing any particles generated at the anode from entering the vicinity of and contaminating the wafer. The anode film can also be useful for redistributing current during the electroplating process and thereby improving plating uniformity. Anode films are further described in U.S. patent No. 6,126,798 and U.S. patent No. 6,569,299, both of which are incorporated herein by reference.

The plating solution may be continuously supplied to the plating vessel 103 by a pump 117. Generally, the electroplating solution flows up through the anode film 115 and resistive element 119 to the center of the wafer 107 and then radially outward and across the wafer. In some embodiments, the plating solution may be provided into the anode region of the plating vessel 103 from the side of the plating vessel. In some implementations, the electroplating solution can be supplied into the anode and cathode regions of the plating vessel via separate inlets.

The resistive element 119 is located in close proximity to the wafer (within about 10 millimeters or about 3 millimeters to 8 millimeters in various embodiments) and acts as a constant current source for the wafer. That is, the resistive element 119 shapes the electrolyte current near the wafer to provide a relatively uniform current distribution across the wafer face. The element contains a plurality of one-dimensional vias, as described further below. Further details regarding the resistive element may be found in U.S. patent application No. 12/291,356, entitled "METHOD and apparatus FOR ELECTROPLATING" (and filed on 7.11.2008), which is incorporated herein by reference.

The plating solution then overflows from plating vessel 103 to overflow reservoir 121 as indicated by arrow 123. The plating solution can be filtered (not shown) and returned to the pump 117 as indicated by arrow 125, thereby completing the recirculation of the plating solution.

A second cathode chamber 127 containing a second cathode (i.e., a thief cathode) 129 may be located on the outside of plating vessel 103 and at the wafer periphery. Generally, the second cathode may be positioned at several locations within or outside of the plating vessel.

In some embodiments, the plating solution overflows from the weir wall of plating vessel 103 into second cathode chamber 127. In some embodiments, the second cathode chamber 127 is separated from the plating vessel 103 by a wall having a plurality of openings covered by an ion permeable membrane. The membrane allows ionic communication between the plating vessel 103 and the second cathode chamber 127, thereby allowing the current to be diverted to the second cathode. The porosity of the film may be such that it does not allow particulate material to cross from the second cathode chamber 127 to the plating vessel 103 and cause wafer contamination. The openings in the wall may take the form of circular holes, slots, or other shapes of various sizes. In one embodiment, the opening is a slot having dimensions of, for example, about 12 millimeters by 90 millimeters. There may be other mechanisms for allowing fluid and/or ionic communication between the second cathode chamber and the plating vessel. Examples include designs in which a thin film, rather than an impermeable wall, provides the majority of the potential barrier between the plating solution in the second cathode chamber and the plating solution in the plating vessel. In such implementations, a rigid frame may provide support for the membrane.

Two DC power supplies 135 and 137 may be used to control the current to the wafer 107 and to the second cathode 129, respectively. The power supply 135 has a negative output lead 139 that is electrically connected to the wafer 107 via one or more slip rings, brushes, or contacts (not shown). The positive output lead 141 of the power supply 135 is electrically connected to the anode 113 located in the electroplating vessel 103. For example, the power supply may have an output voltage of up to about 250 volts. Similarly, the power supply 137 has a negative output lead 143 electrically connected to the second cathode 129 and a positive output lead 145 electrically connected to the anode 113. Alternatively, different levels of current may be provided to the wafer and the second cathode using one power supply having multiple independently controllable electrical sockets.

The power supplies 135 and 137 may be connected to a controller 147, the controller 147 allowing modulation of the current and potential provided to the elements of the electroplating apparatus 300. For example, the controller may allow electroplating in a current controlled or potential controlled state. The system controller 330 may include program instructions that specify the current and voltage levels that need to be applied to the various elements of the electroplating apparatus, as well as the times at which these levels need to be changed. For example, it may include program instructions for transitioning from potential control to current control upon immersion of the wafer into the electroplating solution.

During use, the power supplies 135 and 137 bias both the wafer 107 and the second cathode 129 to have negative potentials with respect to the anode 113. This causes the current flowing from the anode 113 to the wafer 107 to be partially or substantially diverted to the second cathode 129. The circuit described above may also include one or several diodes that will prevent current reversal when such reversal is not desired. Undesirable current feedback can occur during the electroplating process because the anode 113, set to ground potential, is a common element of both the wafer circuit and the second cathode circuit.

The level of current applied to the second cathode 129 is typically set to a lower value than the level of current applied to the wafer 107, where the second cathode current is present as a percentage of the wafer current. For example, a 10% second cathode current corresponds to a current at the second cathode that is 10% of the current to the wafer. The direction of current flow as used herein is the direction of net positive ion flux. During electroplating, electrochemical reduction occurs on both the wafer surface and the second cathode surface (e.g., Cu)²⁺+2e^-＝Cu⁰) This results in deposition of copper on the surface of both the wafer and the second cathode. The thickness of the deposited copper layer at the edge of the wafer can be reduced as the current is diverted from the wafer to the second cathode. This effect is typically 20 mm outside the waferOccurs in meters and is particularly prominent at 10 millimeters outside thereof, particularly when electroplating is performed on liner or thin seed layers. The use of the second cathode 129 may substantially improve the center-edge non-uniformity created by the end and field effects. The second cathode may be used alone or in combination with other auxiliary cathodes or in combination with a plurality of fixed or dynamic shields.

Further details regarding auxiliary cathodes, including secondary AND tertiary cathodes, may be found in U.S. patent application No. 12/481,503, entitled "METHOD AND APPARATUS FOR ELECTROPLATING" (AND filed FOR ELECTROPLATING), filed on 6.9.2009, which is incorporated herein by reference. It should be understood that the auxiliary cathode and its associated power supply are optional features.

One or more shields (e.g., 149) may be positioned within the electroplating vessel between the resistive element 119 and the anode 113 (e.g., under the resistive element in a wafer-down system). The shield is typically a ring-shaped dielectric insert that is used to shape the current distribution profile and improve the uniformity of plating, such as those described in U.S. patent No. 6,027,631, which is incorporated herein by reference. Other shield designs and shapes known to those skilled in the art may be employed.

In general, the shield may take any shape, including wedge, bar, circular, oval shapes, and other geometric designs. The ring-shaped insert may also have several patterns at its inside diameter that may improve the ability of the shield to shape the current flux in a desired manner. The function of the shield may vary depending on its location in the plating vessel. The apparatus may include either of a static shield and a variable field shaping element, such as those described in U.S. patent No. 6,402,923 and U.S. patent No. 7,070,686, both of which are incorporated herein by reference. The apparatus may also include any of segmented anodes such as described in U.S. patent No. 6,497,801 or concentric anodes such as described in U.S. patent nos. 6,755,954 and 6,773,571, all of which are incorporated herein by reference. Although shield inserts may be suitable for improving plating uniformity, in some embodiments, the shield inserts may not be used or alternative shield configurations may be employed.

A shield (e.g., shield 151) may be positioned within the plating vessel between the resistive element 119 and the wafer 107. In some implementations, a shield can reside around the perimeter of the resistive element to further improve edge-to-center plating uniformity. In some implementations, the shield may reside directly above the resistive element. In some implementations, a shield can be positioned between the resistive element and the wafer to block a path between at least some of the perforations at the peripheral region of the element and the wafer.

Resistance element

In some embodiments, the resistive element 119 may be a multi-porous plate or disk (e.g., a plate made of sintered particles of ceramic or glass) having a continuous three-dimensional pore network. A porous plate having a three-dimensional network of pores includes entangled pores through which ionic current can travel both vertically upward through the plate to the wafer and laterally (e.g., from the center to the edge of the plate) in the general direction of the anode. Examples of suitable designs for such panels are described in U.S. patent No. 7,622,024, which is incorporated herein by reference.

In some implementations, the resistive element 119 can include pores or channels that provide pathways through the resistive element that are not substantially in communication with each other within the body of the element. Such pores or channels may be linear or non-linear. Such pores or channels may also be parallel or non-parallel to the direction of ion current flow.

In some implementations, the resistive element 119 may include linear pores or channels (i.e., one-dimensional vias in the resistive element) that are generally parallel to the direction of ionic current and that do not substantially communicate with each other within the body of the element. This aperture or channel configuration minimizes lateral movement of the ion current in the element. The ion current flows in a one-dimensional manner, i.e., generally in a vector direction perpendicular to the nearest plated surface (e.g., wafer 107) in the vicinity of the resistive element. This resistance element is referred to as a one-dimensional resistance element.

The resistive element comprising one-dimensional through-holes (also known as a one-dimensional porous high resistance virtual anode or HRVA) is typically a disk made of an ionically resistive material with a plurality of holes drilled (or otherwise fabricated) through it (other shapes may also be used). The holes do not form communication channels within the body of the disk and extend through the disk generally in a direction generally perpendicular to the surface of the wafer. A variety of ionic resistance materials may be used for the disk body, including polycarbonate, polyethylene, polypropylene, polyvinylidene fluoride (PVDF), polytetrafluoroethylene, polysulfone, and the like. In some embodiments, the disk material is resistant to degradation in an acid electrolyte environment, relatively hard, and easily handled by machining.

In some implementations, the resistive element may be in close proximity to the workpiece and dominate the overall resistance of the electroplating apparatus. The resistive element may approximately evenly distribute the current source when the resistive element has sufficient resistance relative to the sheet resistance of the workpiece. In general, the higher the sheet resistance of the layer being plated, the higher the resistance of the resistive element needed to assist in mitigating the end effect, or the higher the resistivity of the electroplating solution. With a high resistance resistive element, in some embodiments, a lower resistivity electrolyte may be used and vice versa.

By holding the workpiece close to the resistive element, the ionic resistance from the top of the element to the surface of the workpiece is much less than the ionic path resistance from the center-top of the element to the edge of the workpiece, thereby substantially compensating for the sheet resistance in the seed layer of the liner layer and directing a significant amount of current over the center of the workpiece. Details associated with using resistive elements in close proximity to the wafer are further discussed in U.S. patent application No. 11/040,359.

Whether the resistive element permits current flow in one or more dimensions, it may be coextensive with the workpiece in some implementations. Thus, when the workpiece is a wafer, the resistive element has a diameter that is generally close to the diameter of the wafer being plated. For example, the resistive element diameter may be about 150 mm to 450 mm in diameter, with about 200 mm resistive element for a 200 mm wafer, about 300 mm resistive element for a 300 mm wafer, and about 450 mm resistive element for a 450 mm wafer, and so on. In examples where the wafer has a generally circular shape but has irregular asperities at the edges (such as notches or flat areas where the wafer is chordally cut), a disk-shaped resistive element may still be used, although other compensating adjustments may be made to the electroplating apparatus, as described in U.S. patent application No. 12/291,356.

In some embodiments, the resistive element has a diameter greater than the diameter of the wafer to be plated (e.g., greater than 200 millimeters or 300 millimeters) and has an outer edge portion that is non-porous (in the case of a one-dimensional resistive element). This edge portion can be used to create a small gap around the periphery of the wafer (the peripheral gap between the resistive element edge portion and the wafer edge or bottom of the wafer retaining cup) and to assist in mounting the resistive element within the plating vessel. In some embodiments, the non-porous resistive element edge (from the outer edge of the resistive element to the edge of the portion of the resistive element having the holes) is about 5mm to 50 mm in size.

In some implementations of one-dimensional resistive elements, the number of vias in the element can be large, with the diameter of each hole being small. In general, the diameter of each hole may be less than about one-quarter of the gap between the resistive element and the workpiece. In some embodiments, the number of pores may be about 5,000 to 12,000. In some embodiments, each pore (at least 95% of the pores) may have a diameter (or other major dimension) of less than about 5 millimeters, or less than about 1.25 millimeters.

Fig. 6A and 6B show examples of views of one-dimensional resistive elements. Fig. 6A shows an example of a top view of a resistive element 602, illustrating a top surface of the resistive element. The resistive element 602 includes a large number of small diameter openings (shown as black dots). Fig. 6B shows an example of a cross-sectional view of the resistive element 602. As shown in fig. 6B, the vias are substantially perpendicular to the top and bottom surfaces of the resistive element.

In some embodiments, the resistive element has a thickness of about 5mm to 50 mm, for example, about 10 mm to 25 mm or about 10 mm to 20 mm. In some embodiments, the resistive element has a thickness of less than about 15% of the wafer diameter.

The resistance of a resistive element in an electroplating apparatus for a given electroplating solution depends on several parameters, including the thickness of the resistive element and the porosity of the resistive element. The porosity of the resistive element may be defined by an area occupied by an opening of the hole on the surface of the resistive element divided by an area occupied by the surface of the resistive element. Note that this region occupied by the surface of the resistance element is an active region (i.e., a region in contact with the electrolyte) and does not contain a region of the resistance element for mounting or holding the resistance element in the electroplating apparatus. In some embodiments, the porosity of the resistive element may be about 1% to 5% or about 1% to 3%.

In some examples, high resistance resistive elements may be used in applications where end effects are greater. For example, a high resistance resistive element may be particularly useful when the sheet resistance of the surface being plated is about 100 to 200 ohms/square. In the embodiments of the method described above, the end effect can be large when plating copper directly onto the liner layer. For example, one such liner layer may be ruthenium.

The resistance of the resistive element may be determined by determining the resistance of the electroplating solution in the volume to be occupied by the resistive element. For example, a resistive element for electroplating a 300 mm wafer may include an active area (652 cm) of 288 mm in diameter²And its thickness is 1.27 cm. Thus, the electroplating solution having a resistivity of 1250 ohm-centimeters (Ω -cm) has an electrical resistance of (1250 Ω -cm) × (1.27cm)/(652 cm) within the volume to be occupied by the resistive element²) Or 2.43 omega. In the case of a resistance element in the electroplating apparatus having a porosity of 2.43%, only 2.43% of the volume is available for conduction without the resistance element in place. Therefore, the resistance of the resistance element is (2.43 Ω)/(2.43%) or 100.1 Ω.

Table 1 contains the resistance of some exemplary one-dimensional resistive elements having an active area of 288 millimeters in diameter for a 1250 ohm-cm plating solution.

TABLE 1 resistance of exemplary one-dimensional resistive element

In some embodiments, the resistance of the resistive element (assuming a resistive element for electroplating a 300 mm wafer substrate, which is used at a distance of about 3 mm to 8 mm from the wafer substrate surface) is about 25 ohms to 250 ohms (Ω), about 25 Ω to 75 Ω, about 75 Ω to 150 Ω, or about 150 Ω to 250 Ω.

A resistive element may also be characterized by its resistance divided by the active area of the face of the resistive element. Thus, the resistive element may have about 0.04 Ω/cm²To 0.4. omega./cm²About 0.04. omega./cm²To 0.1. omega./cm²About 0.1. omega./cm²To 0.2. omega./cm²Or about 0.2. omega./cm²To 0.4. omega./cm²Per area resistance of (a).

Electroplating devices incorporating high resistance resistive elements may require a power supply having a relatively high output voltage to plate at typical desired current levels. For example, a power supply capable of providing an output voltage of about 50 volts or greater may be used with a high resistance resistive element (e.g., the 2 resistive element in table 1). More specifically, the power supply may be capable of providing an output voltage of about 100 volts to 175 volts (with 150 volts being a typical example). Power supplies capable of providing even higher output voltages (e.g., about 150 to 250 volts) may be used with resistive elements having higher resistance (e.g., 4X resistive elements in table 1).

When copper is plated onto ruthenium, the potential applied between the wafer and the cathode depends on the thickness of the ruthenium layer and the wafer diameter. For example, for a 300 mm wafer, when copper is plated onto a 3 nanometer thick layer of ruthenium, a potential of about 75 volts can be used with the 2 resistive element in table 1, which results in a plating current of about 0.75 amps. For wafers having different ruthenium thicknesses on the surface of a 300 mm wafer, a potential of about 70 to 120 volts can be used with the 2 resistive element in table 1 when plating copper onto ruthenium, resulting in a plating current of about 0.75 to 1.2 amps.

The resistance of the resistive element results from a porosity that is low throughout the thickness of the resistive element but is continuously connected. In an electroplating solution, this can form a very high resistance compact region, which can be positioned in close proximity to the wafer surface. In contrast, a thick resistive element with lower and non-one-dimensional porosity may have the same resistance as the resistive element disclosed herein, but the current steering characteristics of such a thick resistive element may not be the same. The current within such a thick resistive element may tend to enter the central region of the element and flow radially outward as it flows upward.

Another important parameter of a one-dimensional resistive element is the ratio of the via diameter (or other major dimension) to the distance of the element from the wafer. Experimentally and subsequently verified by computer modeling, this ratio should be approximately 1 or less (e.g., less than about 0.8 or less than about 0.25). In some embodiments, this ratio is about 0.1 to provide good plating uniformity performance. In other words, the diameter of the hole may be equal to or less than the distance from the resistive element to the workpiece. If the hole diameter is greater than the wafer-to-resistive element distance, the holes may leave their individual current images or "imprints" on the plated layer above them, thereby resulting in small-scale non-uniformities in the plated layer. The hole diameter value described above refers to the diameter of the hole opening measured on the resistive element side near the wafer. In some implementations, the hole diameters are the same on both the proximal and distal faces of the resistive element, but the holes can also be tapered.

Although the resistive element shown in fig. 6A has a uniform distribution of holes, in other implementations, the resistive element may have areas with a non-uniform distribution of holes or with holes blocked to form a non-uniform distribution of holes. This hole distribution can direct more current to the center of the workpiece so that a high sheet resistance layer can be plated more uniformly. However, very thick films with low sheet resistance may tend to plate less uniformly if a non-uniform pore distribution is used. Blocked or missing holes may be non-uniform in the radial direction, azimuthal direction, or both.

In some implementations, the resistive element is positioned substantially parallel to the workpiece surface and the anode surface, and the one-dimensional aperture is oriented parallel to a direction between the wafer surface and the anode surface. In other implementations, at least some of the holes have their relative angles modified to change the hole length relative to the element thickness and thereby modify the local contribution of the holes to the resistance.

It should be noted that the one-dimensional porous resistive element is different from a so-called diffusion plate. The primary function of the diffuser plate is to distribute the flow of electrolyte rather than providing significant resistance. The diffuser plate typically has openings that constitute a much larger net porosity (in the range from 25% to 80%) sufficient to achieve substantially uniform electrolyte flow via significant viscous flow resistance, and generally has a small (typically insignificant) overall contribution to the electrical resistance of the electroplating apparatus. In contrast, a one-dimensional resistive element can significantly increase the resistance of the electroplating apparatus, which may be desirable for improving the uniformity of electroplating.

Experiment of

In one process, 10 nm of copper was plated on the Ru liner layer. The copper layer is plated by a method similar to that described in U.S. patent No. 7,799,684. The copper layer is then rinsed and dried. The copper layer is annealed at about 300 c in a forming gas. Repeating the process three more times; i.e. four cycles of process operation are performed.

Scanning Electron Microscopy (SEM) micrographs of the cross section of the wafer show that the process operation completely fills features having widths of about 30 to 60 nanometers. Little or no copper remains on the field area of the wafer near the features due to the redistribution of copper into the features. In areas of the wafer that do not contain any features, copper remains in the field regions.

In another process, 10 nm of copper was plated on the Ru barrier layer. The copper layer is plated by a method similar to that described in U.S. patent No. 7,799,684. The copper layer is then rinsed and dried. The copper layer is annealed at about 200 c in a forming gas. Repeating the process three more times; i.e. four cycles of process operation are performed.

SEM micrographs of the cross section of the wafer show that the process operation partially fills features having a width of about 60 nanometers. Some copper remains on the field areas of the wafer. In areas of the wafer that do not contain any features, copper remains in the field regions.

Future embodiments

The apparatus and methods described herein may also be used in conjunction with lithographic patterning tools or processes, for example, to fabricate or manufacture semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, although not necessarily, such tools/processes will be used or performed together in a common fabrication facility. Lithographic patterning of films typically involves some or all of the following steps, each being achieved by several possible tools: (1) applying photoresist on a workpiece (i.e., substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate, an oven, or a UV curing tool; (3) exposing the photoresist to visible, UV or x-ray light with a tool (e.g., a wafer stepper); (4) developing the resist so as to selectively remove the resist using a tool (e.g., a wet etch bath) and thereby pattern it; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma assisted etch tool; and (6) removing the resist using a tool (e.g., RF or microwave plasma resist stripper).

Claims (21)

1. An apparatus, comprising:

a plating chamber configured to hold an electrolyte;

a wafer substrate holder configured to hold a wafer substrate in the plating chamber, the wafer substrate including a surface having an edge region, a field region, and a feature, wherein a width or diameter of the feature is less than 100 nanometers; and

a controller containing program instructions, the program instructions comprising:

(a) instructions for conformally electroplating a copper layer onto the surface of the wafer substrate using the plating chamber;

(b) instructions for annealing the copper layer at a temperature of 150 ℃ to 400 ℃, wherein the annealing reflows copper in the copper layer and redistributes the copper from the field regions of the wafer substrate to bottoms of the features without voids; and

(c) instructions for repeating instructions (a) and (b) until the aspect ratio of the feature is 2:1 or less.

2. The apparatus of claim 1, further comprising:

an element comprising an ionically resistive body having a perforation therein such that the perforation does not form a communicating channel within the body, wherein the perforation allows for transport of the electrolyte through the element, wherein the element is positioned to have a surface facing the surface of the wafer substrate.

3. The apparatus of claim 2, wherein:

the surface of the element having the ion-resistive body is located within 10 millimeters of the surface of the wafer substrate when the wafer substrate is held by the wafer substrate holder, and

substantially all of the perforations in the ionically resistive body have openings on the surface of the element facing the surface of the wafer substrate that have a major dimension of no greater than 5 millimeters, and wherein the element has a porosity of 1% to 3%.

4. The apparatus of claim 1, wherein the copper layer is annealed for 30 seconds to 180 seconds.

5. The apparatus of claim 1, wherein annealing the copper layer is performed in a reducing atmosphere.

6. The apparatus of claim 5, wherein the reducing atmosphere is selected from the group consisting of: forming gases, atomic hydrogen, and other chemical reducing agents, wherein the forming gases are a mixture of hydrogen and nitrogen.

7. The apparatus of claim 1, wherein the surface of the wafer substrate includes a liner layer over the field region and the feature.

8. The apparatus of claim 7, wherein the program instructions of the controller further comprise:

instructions for annealing the liner layer in a reducing atmosphere prior to electroplating the copper layer.

9. The apparatus of claim 7, wherein the backing layer is selected from the group consisting of: ruthenium (Ru), cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), gold (Au), and rhodium (Rh).

10. The apparatus of claim 1, wherein the copper layer comprises a copper alloying element.

11. The apparatus of claim 1, wherein the copper layer has a thickness of 2 to 20 nanometers.

12. The apparatus of claim 1, wherein the program instructions of the controller further comprise:

instructions for electroplating copper onto the copper layer to fill the features after the annealing redistributes the copper from the field regions of the wafer substrate to the features such that the aspect ratio of the features is 2:1 or less.

13. The apparatus of claim 1, wherein the program instructions of the controller further comprise:

instructions for repeating operations (a) and (b)2 to 8 times.

14. The apparatus of claim 1, wherein the program instructions of the controller further comprise:

instructions for electroplating a copper alloy onto the copper layer after annealing the copper layer.

15. The apparatus of claim 1, wherein the copper layer is continuous.

16. The apparatus of claim 1, wherein the electroplating is performed at a temperature of room temperature.

17. The apparatus of claim 1, wherein the electroplating is performed at a temperature of 50 ℃ to 90 ℃.

18. The apparatus of claim 1, wherein the electroplating is performed in an electroplating solution having a resistivity above 200 Ω -cm.

19. The apparatus of claim 18, wherein the electroplating is performed in an electroplating solution having a resistivity above 1000 Ω -cm.

20. A system comprising the apparatus of claim 3 and a stepper.

21. A non-transitory computer machine readable medium having program instructions for controlling a device, the program instructions comprising:

(a) instructions for transporting a wafer substrate to a module associated with the apparatus, the wafer substrate including a surface having an edge region, a field region, and a feature, wherein a width or diameter of the feature is less than 100 nanometers;

(b) instructions for conformally plating a copper layer onto the surface of the wafer substrate;

(c) instructions for annealing the copper layer at a temperature of 150 ℃ to 400 ℃, wherein the annealing reflows copper in the copper layer and redistributes the copper from the field regions of the wafer substrate to bottoms of the features without voids; and

(d) instructions for repeating instructions (b) and (c) until the aspect ratio of the feature is 2:1 or less.

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