CN102732925A

CN102732925A - Method and device for filling interconnection structure

Info

Publication number: CN102732925A
Application number: CN2012101081007A
Authority: CN
Inventors: 乔纳森·D·里德; 朱焕丰
Original assignee: ASM Nutool Inc
Current assignee: Novellus Systems Inc; ASM Nutool Inc
Priority date: 2011-04-15
Filing date: 2012-04-13
Publication date: 2012-10-17
Also published as: CN108330518B; CN108330518A; CN102738071B; CN102738071A

Abstract

The invention relates to a method and device for filling an interconnection structure. The invention provides a method, device and system for deposited copper and other metals. In some embodiments, a wafer substrate is provided to the device, and has a plurality of areas and a surface of characteristic,a copper layer is plated to the surface of the wafer substrate,the copper layer is annealed so as to redistribute the plurality of areas of the wafer substrate to the characteristic,and the disclosed method, device and system allow the characteristic of the wafer substrate to be filled upwards without clearance.

Description

Be used to fill the method and apparatus of interconnection structure

The related application cross reference

The application's case is advocated the right of priority of following application case: filed an application on May 16th, 2011 the 13/108th; File an application in No. 894 patent application, on May 16th, 2011 the 13/108th; The 61/476th, No. 091 U.S. Provisional Patent Application case that No. 881 patent application and on April 15th, 2011 file an application; All three application cases all are incorporated herein by reference.

Technical field

The present invention relates to semiconductor processing techniques.In particular, the present invention relates to a kind of method and apparatus that is used to fill interconnection structure.

Background technology

Can use damascene (semiconductor processing techniques) on unicircuit, to form interconnection.Damascene relates to forming in groove and the via in being formed at dielectric layer and embeds metal wire.In typical inlay, the pattern of etched trench and via in the dielectric layer of semiconductor wafer substrate.Then, through (for instance) physical vapor deposition (PVD) technology the for example double-deck barrier layer of tantalum (Ta), tantalum nitride (TaN) or TaN/Ta is deposited on the wafer surface.Then, use electroplating technology to fill said groove and via usually with copper.Usually need on conductive layer, take place owing to electroplate, therefore can be at first by chemical vapor deposition (CVD) or PVD technology copper seed crystal layer on barrier layer.Then, can copper be electroplated onto on the said copper seed layer.

Summary of the invention

The present invention is provided for method, equipment and the system of plating coating copper and other metal.According to various embodiments, said method relates to the copper layer is plated on the wafer substrates.Can be with said copper layer annealing, this can make copper redistribute the certain characteristics the wafer substrates from the several regions of wafer substrates.In some cases, plating and subsequent anneal are served as a circulation of many cyclical deposition process.Therefore, said depositing operation can relate to two or more plating/anneal cycles of continuous execution.

In some embodiments, a kind of equipment comprises plating chamber, workpiece retainer and element.Said plating chamber is through being configured to keep electrolytic solution.Said workpiece retainer remains in workpiece in the said plating chamber through being configured to.Said workpiece comprises the surface with some fringe regions.Said element comprises the ion resistance main body, has some perforation in the said main body and makes said perforation in said main body, not form communication passage.Said perforation allows to carry said electrolytic solution via said element.Said element is through locating to have towards the surface on the said surface of said workpiece.Said equipment makes during the plating said surface of said element be positioned at apart from the said surface of said workpiece about 10 millimeters through disposing.Roughly all said perforation have at the said lip-deep opening towards the said surface of said workpiece of said element and are not more than about 5 millimeters major dimension.The porosity of said element is about 1% to 3%.

In some embodiments, a kind of equipment comprises plating chamber, workpiece retainer, element and negative electrode.Said plating chamber is through being configured to keep electrolytic solution.Said workpiece retainer remains in workpiece in the said plating chamber through being configured to.Said workpiece comprises the surface with some fringe regions.Said element comprises the ion resistance main body, has some perforation in the said main body and makes said perforation in said main body, not form communication passage.Said perforation allows to carry said electrolytic solution via said element.Said element is through locating to have towards the surface on the said surface of said workpiece.Said equipment makes during the plating said surface of said element be positioned at apart from the said surface of said workpiece about 10 millimeters through disposing.Roughly all said perforation have at the said lip-deep opening towards the said surface of said workpiece of said element and are not more than about 5 millimeters major dimension.The porosity of said element is about 1% to 3%.Said negative electrode through configuration so that the part of ion(ic)current turn to from the said fringe region of said workpiece.

In some embodiments, a kind of equipment comprises plating chamber, workpiece retainer, element and screen.Said plating chamber is through being configured to keep electrolytic solution.Said workpiece retainer remains in workpiece in the said plating chamber through being configured to.Said workpiece comprises the surface with some fringe regions.Said element comprises the ion resistance main body, has some perforation in the said main body and makes said perforation in said main body, not form communication passage.Said perforation allows to carry said electrolytic solution via said element.Said element is through locating to have towards the surface on the said surface of said workpiece.Said equipment makes during the plating said surface of said element be positioned at apart from the said surface of said workpiece about 10 millimeters through disposing.Roughly all said perforation have at the said lip-deep opening towards the said surface of said workpiece of said element and are not more than about 5 millimeters major dimension.The porosity of said element is about 1% to 3%.Said screen is positioned between said element and the said workpiece with at least some perforation in the said perforation in the outer peripheral areas that stops said element and the path between the said workpiece.

Aspect these and other of the embodiment of the subject matter in accompanying drawing and hereinafter description described in this specification sheets of elaboration.

Description of drawings

Fig. 1 shows that graphic extension is used for the instance of schema of the technology of plating coating copper.

The instance of the xsect schematic illustration in the stage in the method for Fig. 2 A and 2B displaying plating coating copper.

Fig. 3 shows that graphic extension is used for the instance of schema of the technology of plating coating copper.

Fig. 4 A shows the instance of the synoptic diagram of electric fill system to 4G.

Fig. 5 shows the instance of the cross sectional representation of electroplating device.

Fig. 6 A and 6B show the instance of the view of one dimension resistance unit.

Embodiment

Foreword

In following detailed description, set forth numerous particular so that provide to thorough of the present invention.Yet, as it will be apparent to those skilled in the art that, can be under the situation of not having these specific detail or through using alternative elements or technology to put into practice the present invention.In other instance, do not describe well-known technology, program and assembly in detail so that can make aspect of the present invention fuzzy necessarily.

In the application's case, term " semiconductor wafer ", " wafer ", " substrate ", " wafer substrates " reach " through the unicircuit of part making " and use interchangeably.Those skilled in the art will appreciate that term " through the unicircuit that part is made " can refer to the silicon wafer during any one in many stages of making unicircuit above that.Can have different shape, size and material to its workpiece of carrying out the operation that is disclosed.Except that semiconductor wafer, other workpiece of the present invention capable of using also comprises for example various items such as printed substrate.

The current techniques that is used for metallized integrated circuit comprises via physical vapor deposition (PVD) process deposits barrier layer and backing layer, uses via the copper (Cu) of PVD process deposits and give said backing layer sowing and then use the technology electro-coppering that the bottom-up filling of tight is provided.Yet electroplating technology is not easy to expand to the feature sizes that is lower than about 18 nanometers.Under these sizes, the opening of little characteristic can (for instance) be reduced to about 2 nanometers to 4 nanometers before electroplating technology owing to the coating of barrier layer and backing layer.This makes said characteristic become the very characteristic of high aspect ratio, and it possibly not allow to carry out void-free bottom-up filling by some electroplating technologies.

Embodiment disclosed herein can and make the copper redistribution overcome the difficulty of filling said characteristic to fill very little characteristic through plating coating copper layer in regular turn.The big I of these a little characteristics is lower than about 100 nanometers and it has high aspect ratio.Disclose embodiment among this paper in order to the method and apparatus of filling the little unicircuit characteristic that can be coated with potential barrier/backing layer.In some embodiments, the said characteristic of technological operation available copper completely filled.In addition, the embodiment that some disclosed is not used the copper seed layer by the physical vapor deposition (PVD) process deposits.

In some embodiments, the copper layer directly is plated on the backing layer of wafer substrates.For instance, said backing layer can be ruthenium layer or other suitable conduction barrier metal layer.So can be then with annealing through the plating coating copper layer.In some embodiments, said annealing can be carried out under about 150 ℃ to 400 ℃ in reducing atmosphere (for example forming gas) about 30 seconds to 180 seconds.Said annealing can make the copper in the copper layer redistribute in the little characteristic.Said annealing also can make any area exposed subsequently of said copper layer and backing layer be maintained in the reduced state.Can repeat copper plating and annealing process about 2 times to 8 times, so as gradually and tight ground fill little characteristic, for example width or diameter are the characteristic from about 8 nanometers to 100 nanometers.In some embodiments, each thickness through the plating coating copper layer can be about 2 nanometers to 20 nanometers, and this depends on feature sizes and aspect ratio.Can then use conventional electroplating technology plating wafer substrates to fill big characteristic before at chemical-mechanical planarization (CMP).

In some embodiments, in electroplating device, use resistance unit to assist to alleviate or eliminate " end effect " when the plating coating copper layer.End effect can increase near the plating thickness that has greater than the Waffer edge of the wafer surface of the sheet resistance of about 1 ohm-sq, and this is unacceptable.In some embodiments, resistance unit comprises closely near several of wafer through isolating and connecting through hole not the overall resistance of arranging electroplating device whereby.

Method

Fig. 1 shows that graphic extension is used for the instance of schema of the technology of plating coating copper.Frame 102 places in method 100 provide wafer substrates.Said wafer substrates can comprise a characteristic and some field.Said characteristic can have width or the diameter and the aspect ratio of variation.The aspect ratio of characteristic is the ratio of width of height and said characteristic of the vertical side wall of said characteristic.

For instance, the width of characteristic or diameter can be about 100 nanometers, about 90 nanometers, about 60 nanometers, about 30 nanometers, about 18 nanometers, about 15 nanometers, about 12 nanometers, about 8 nanometers, less than about 100 nanometers or less than about 18 nanometers.For characteristic, be used for embodiment that other technology of deposited copper maybe ratio method 100 more fast and more efficient with big width.Yet method 100 can be used for filling with copper a part or parts of this big width characteristics.

In some embodiments, said wafer substrates can be the wafer substrates that experiences damascene, and the characteristic in the said wafer substrates can be etched line characteristic or via characteristic in dielectric layer.For instance, the aspect ratio of etched characteristic can be about 10: 1 or bigger in dielectric layer.In some embodiments, said dielectric layer can be coated with barrier layer, and said barrier layer can be coated with backing layer.In other embodiments, potential barrier and lining can be a kind of single layer of material.That is to say that backing layer can represent barrier layer character, making does not need independent barrier layer and backing layer.For instance, in being coated with the dielectric layer of potential barrier/backing layer the aspect ratio of etched characteristic can be about 12: 1, about 15: 1 or greater than about 12: 1.In other embodiments, said characteristic can be have about 15: 1, about 20: 1 or greater than the contact via of about 15: 1 aspect ratio.

For instance, said dielectric layer can be coated with tantalum nitride (TaN) barrier layer.The thickness of TaN barrier layer can be about 2 nanometers.Can deposit the TaN barrier layer by physical vapor deposition (PVD) technology or chemical vapor deposition (CVD) technology.In other embodiments, for instance, said barrier layer can be tantalum (Ta), tungsten (W), tungsten nitride (WN), titanium (Ti) or titanium nitride (TiN).Said barrier layer can be coated with ruthenium (Ru) backing layer.The thickness of Ru backing layer can be about 2 nanometers.Can deposit the Ru backing layer by CVD technology.In other embodiments, for instance, said backing layer can be cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), gold (Au) or rhodium (Rh).

In some embodiments, said backing layer is through selecting to make the wetting said backing layer of copper.Wetting is liquid-retentive and the ability that contacts of solid surface.The liquid of wetting solid surface is crossed over said surface and is scattered.The liquid of nonwetting solid surface forms droplet or spheroid so that minimize with contacting of said surface on said surface.The wetness degree of the liquid that contacts with solid surface is confirmed by adhesive power (that is the power between liquid and the solid) and force of cohesion (that is the intravital power of liquid).For instance, based on the oxidation behavior of metal, the wetting metal of copper comprises Ru, Pt, Pd, Au and Rh.

At frame 104 places, with the lip-deep backing layer annealing of substrate.In some embodiments, can in reducing atmosphere, backing layer be annealed to remove any natural oxide of pollutent or minimizing metal.For instance, pollutent can comprise the carbon on the surface that is adsorbed onto backing layer.Remove pollutent or minimizing natural oxide and can assist formation Continuous Copper layer in the described hereinafter shikishima plating process.

In some embodiments, reducing atmosphere comprises formation gas, atomic hydrogen or other chemical reducing agent.Formation gas is the mixture of hydrogen (hydrogen mole fraction is variable) and nitrogen.In some embodiments, can be under about 150 ℃ to 400 ℃ with about 30 seconds to 180 seconds of backing layer annealed.For instance, can be in forming gas under about 225 ℃ with about 90 seconds of backing layer annealed.In other embodiments, can handle backing layer down at other reductive condition (for example hydrogen plasma or atomic hydrogen).

At frame 106 places, plating coating copper layer on backing layer.In some embodiments, by electroplating technology plating coating copper layer, and in other embodiments, by electroless plating plating coating copper layer.In some embodiments, can carry out the plating process in the frame 106 down in about room temperature (that is, about 20 ℃ to 29 ℃ or about 25 ℃).

In some embodiments, through the thickness of plating coating copper layer can be the characteristic on the wafer substrates width or diameter about 20% to 80%.For instance, the thickness of said copper layer can be about 2 nanometers to 20 nanometers or about 2 nanometers to 10 nanometers.In some embodiments, said copper layer has a thickness and makes and to exist enough copper to fill about 10% to 50% of characteristic by each annealing operation at the described frame of hereinafter 110 places.In some embodiments, said copper layer is not only on the backing layer in the characteristic of wafer substrates but also on the backing layer on the field, form approximate conformal layer.

In some embodiments, the copper layer through plating can be the Continuous Copper layer.That is to say that said copper layer can form successive layers above backing layer.In other embodiments, copper can be discontinuous.That is to say that the several regions of backing layer possibly not be coated with the copper layer.For instance, the copper layer can cover backing layer except the backing layer the zone above the part of the field of wafer substrates.

In some embodiments, the copper layer can represent a certain preferred growth in the characteristic, and in other embodiments, the copper layer can represent the growth slightly slowly in the characteristic.

In some embodiments, the copper layer can comprise alloying element; That is, can be on backing layer the plating coating copper alloy layer.Alloying element can have about atomic mass of 50 to 210.For instance, alloying element can be chromium, iron, cobalt, nickel, zinc, ruthenium, rhodium, palladium, silver, indium, tin, tellurium, platinum, gold or plumbous.Can comprise one or more in these alloying elements in the copper layer.In some embodiments, the copper layer comprises about 0.1 weight % a kind of or some kinds of alloying elements to 5 weight %.Such as hereinafter explanation, alloying element can provide a certain protection of resisting the damage that is produced by electromigration.

As indicated above, in some embodiments, can be by electroplating technology plating coating copper layer.In some embodiments, electroplating solution and hardware can allow copper evenly to extend across the wafer deposition.For instance, electroplating solution can be the height compound copper electroplating solution of dilution.By these a little electroplating solutions, the copper nucleation can be on the resistance wafer substrates evenly and successive.The height compound copper electroplating solution of dilution is further described in the 7th, 799, No. 684 USPs that are incorporated herein by reference.Electroplating solution also can comprise the plating speed that can strengthen in the less characteristic with auxiliary additive of filling these characteristics, for example polymkeric substance.

Other method by the electroplating technology deposited copper is described in the following application case: title for " be used for be coated with stride evenly on the wafer of ruthenium that wafer deposition and tight fill have annealed two step copper electroplating technologies (TWO STEP COPPER ELECTROPLATING PROCESS WITH ANNEAL FOR UNIFORM ACROSS WAFER DEPOSITION AND VOID FREE FILLING ON RUTHENIUM COATED WAFERS) " and on March 6th, 2008 file an application the 12/075th; No. 023 patent application; And title for " be used for be coated with evenly stride the copper electroplating technology (COPPER ELECTROPLATING PROCESS FOR UNIFORM ACROSS WAFER DEPOSITION AND VOID FREE FILLING ON SEMI-NOBLE METAL COATED WAFERS) that wafer deposition and tight are filled on the wafer of semi-precious metal " and on May 21st, 2010 file an application the 12/785th; No. 205 patent application, both all are incorporated herein by reference said application case.Hereinafter further describes the equipment that is used for electro-coppering.

As indicated above, in some embodiments, can be by the electroless plating plating coating copper.In some cases, can under the situation of not using external power, carry out electroless plating (being also referred to as chemistry or autocatalytically plating).By electroless plating, be present in the end effect in the electroplating technology sometimes owing to current delivery is not existed to wafer substrates from external source.In some embodiments, more easily realize copper layer homogeneity by electroless plating.Electroless plating and equipment are further described in the 6th, 664, and No. 122, the 6th, 815, No. 349, the 7th, 456, No. 102, the 7th, 897, in No. 198 USPs, all these patents all are incorporated herein by reference.

At frame 108 places, flushing and drying crystal wafer substrate.In some embodiments, can in spin rinse moisture eliminator (SRD), wash also drying crystal wafer substrate.Being used to wash also, the Processes and apparatus of drying crystal wafer substrate is further described in the 7th, 033, No. 465 USPs that are incorporated herein by reference.

At frame 110 places,, make copper redistribute said characteristic from the several regions of wafer substrates with the annealing of copper layer.The said zone of wafer substrates can comprise some field.In some embodiments, copper redistributes said characteristic from the field of wafer substrates.In some embodiments, copper redistributes the bottom of characteristic from the several regions of wafer substrates.In some embodiments, under about 150 ℃ to 400 ℃ with about 30 seconds to 180 seconds of copper layer annealed.In some embodiments, can under reducing atmosphere, carry out annealing.Said reducing atmosphere can be any reducing atmosphere that makes backing layer be maintained in the oxide-free state and prevent the oxidation of copper.For instance, in some embodiments, reducing atmosphere comprises formation gas, atomic hydrogen or other chemical reducing agent.

Can realize heating the copper layer with its annealing by many different technologies.For instance, can heat said copper layer (that is resistive heating) through the copper layer through making electric current.Also can heat the copper layer by ultraviolet (UV) light or infrared (IR) light.In some embodiments, can be during technological cycle heated chip substrate constantly or periodically.

In some embodiments, cause the copper of plating in characteristic to redistribute the substrate of said characteristic the annealing of copper layer.For instance, be plated to the bottom that copper on the side of characteristic can redistribute said characteristic.In some cases, will be drawn into the characteristic through the field of plating coating copper from wafer substrates.

Although do not expect to be subject to any theory, believe that copper is the result of capillary effect to the redistribution that characteristic reaches the substrate of characteristic.For instance, if characteristic is fully little, the adhesive power between the backing layer in the surface tension of copper (it is caused by the force of cohesion in the copper) and copper and the characteristic can be done in order to copper is drawn in the substrate of characteristic so.

At frame 112 places, confirm whether the aspect ratio of characteristic is competent.If the aspect ratio of characteristic is competent, method 100 finishes so.If the aspect ratio of characteristic is inadequate, repetitive operation 106 to 110 is till the aspect ratio abundance so.In some embodiments, repetitive operation is 106 to 110 about 2 times to 8 times.In some embodiments; Can and change to the process sequence of operation 106 to 110 through the thickness of plating coating copper layer and annealing temperature and time length; But in general the thickness through the plating coating copper layer is that about 2 nanometers are about 150 ℃ to 400 ℃ to 20 nanometers and annealing temperature, continues about 30 seconds to 180 seconds.

The sufficient aspect ratio of characteristic can be following aspect ratio: to said aspect ratio, can be not form in the characteristic under the situation in any space and carry out body layer electroplating technology.For instance, the sufficient aspect ratio of characteristic can be about 2: 1 or littler, about 2: 1 or about 1: 1.If before the embodiment of manner of execution 100, under wafer substrates has the situation of high aspect ratio features, carry out body layer electroplating technology; So may be on wafer substrates with the copper metal-plated; Make the opening obstruction of characteristic that copper arranged, and the tamper below have the space.

After the characteristic in the wafer substrates being filled into sufficient aspect ratio, can use the body electroplating technology with copper body layer plating wafer substrates with copper.In some embodiments, copper body layer can have the thickness of about 0.2 nanometer to 0.5 nanometer.By the body electroplating technology copper body layer is plated on the wafer substrates and can improves before through the electroplated film pattern at chemical-mechanical planarization (CMP).The subsequent disposal of wafer substrates after CMP followed the known standard inlay of those skilled in the art flow process.

Therefore, the embodiment of method 100 is used for filling characteristic with copper, thereby guarantees the bottom-up filling of said characteristic, makes not form the space.In some embodiments, but the operation 106 to 110 of repetition methods 100, till characteristic is filled.Perhaps, but the operation 106 to 110 of repetition methods 100, up to characteristic being filled into the level that can under not interstitial situation, carry out the body electroplating technology that makes with copper.

In some embodiments, the number of times of the technological operation in the copper level repeat block 106 to 110 of wanting for reaching in the characteristic is minimized.The copper level of wanting that for instance, can repeat to reach in the characteristic by 2 times or 3 times of the technological operation in the frame 106 to 110.For instance, can the multiplicity of technological operation be minimized through the copper layer that plating in frame 106 has an optimal thickness.The copper layer should be too not thick, if because the copper layer is too thick, characterized openings can be stopped up by copper in the plating process so.Yet, thick more through the plating coating copper layer, during just having the annealing of more copper in frame 110 on the several regions (comprising field) of wafer substrates, redistribute said characteristic.Therefore, the plating thick copper layer is useful providing aspect the copper that can redistribute characteristic, but the copper layer should be not thick in making it stop up said characteristic.

For instance, wafer substrates can comprise 20 nanofeature.In frame 106, but the copper layer of about 5 nanometer thickness of plating carries out flushing and the annealing in drying and the frame 110 in the frame 108 afterwards.Can repeat characteristic to be filled into proper level by 2 times or 3 times of operation 106 to 110 with copper.

In some embodiments, can at high temperature carry out the shikishima plating process in the frame 106.For instance, can use the electroplating solution that adopts the higher solvent under the temperature of the boiling point that surpasses water, to carry out electroplating technology.As another instance, can under about 50 ℃ to 90 ℃ temperature, carry out electroless plating.In some embodiments, at high temperature carrying out shikishima plating process can make copper redistribute characteristic at least in part during shikishima plating process.

The instance of the xsect schematic illustration in the stage in the method for Fig. 2 A and 2B displaying plating coating copper.In Fig. 2 A, 200 graphic extensions have the wafer substrates of characteristic 204 and field 206.Copper layer 202 is plated on the said wafer substrates, in the frame in Fig. 1 106.220 are illustrated in the wafer substrates after the annealing process, as in the frame 110 of Fig. 1.Such as in 220 displaying, make copper layer 202 redistribute the bottom of characteristic 204, wherein residual copper not in field 206.

In being similar to Fig. 2 B of Fig. 2 A, 200 graphic extensions have the wafer substrates of characteristic 204 and field 206.Copper layer 202 is plated on the said wafer substrates, in the frame in Fig. 1 106.Wafer substrates after the 240 graphic extension annealing processs is as in the frame 110 of Fig. 1.Such as in 240 displaying, make copper layer 202 redistribute the bottom of characteristic 204, wherein some copper of residue in field 206 and on the sidewall of characteristic 204.The difference of the amount of copper redistribution (be included in the field whether residual copper) is attributable to the different chips substrate material that (for instance) annealing time, annealing temperature or copper deposit to.

Fig. 3 shows that graphic extension is used for the instance of schema of the technology of plating coating copper.The method 100 that the method 250 of being showed among Fig. 3 is similar among Fig. 1 to be showed wherein adds the plating cap layer in method 250.

At frame 260 places of method 250, whether after the abundance, cap layer is plated on the copper layer in the aspect ratio of confirming characteristic.For instance, said cap layer can comprise the copper layer (that is copper alloy layer) with alloying element.Said copper alloy element can comprise any one in the alloying element mentioned above.The copper alloy element can be assisted the electromigration that reduces copper, and this increases the electromigration lifetime of semiconductor device.Said cap layer also can comprise the auxiliary electromigratory copper removal metal in addition that reduces copper.

In some embodiments, can the composition of copper layer be changed by each the plating operation in the frame 106.For instance, in first plating operation, but plating pure copper layer roughly.In the operation of second plating, but plating comprises the copper layer of the alloying element of about 2.5 weight %.In the operation of the 3rd plating, but plating comprises the copper layer of the alloying element of about 5 weight %.Therefore, can gradually the composition of copper layer be increased to the composition of cap layer.

In the embodiment (the copper layer plating that wherein in entire method 100, will have alloying element is on wafer substrates) of method 100; After use body electroplating technology is plated to copper body layer on the wafer substrates, can handles said wafer substrates and be diffused in the body layer to cause at least some alloying elements in the alloying element.In some embodiments, said processing can be thermal treatment.The copper alloy element that is diffused in the body layer also can be assisted the electromigration that reduces copper, thereby increases the electromigration lifetime of semiconductor device.

Although above method is described about copper plating and redistribution, said method also applicable to the plating and the redistribution of other metal, for instance, comprises tin (Sn), silver (Ag) and gold (Au).

Equipment

Embodiment through the suitable equipment that is configured to realize method described herein comprises the central controller that is used to realize the hardware of technological operation and has the instruction that is used for the CONTROL PROCESS operation.Be applicable to the embodiment of in manufacturing environment, using through being configured to allow wafer substrates to cycle through order plating, flushing, drying and annealing process apparatus operating efficiently.Said equipment can comprise through being configured to carry out the instrument and/or the chamber of more than one technological operations.For instance, said equipment can comprise also through being configured to wash the also plating chamber and the annealing chamber of drying crystal wafer substrate.As another instance, said equipment can comprise plating chamber and through be configured to wafer substrates wash, drying and annealed chamber.Through be configured to wafer substrates wash, the particular of drying and annealed instrument can be and the spin rinse moisture eliminator (SRD) of annealing station combination.

Fig. 4 A shows the instance of the synoptic diagram of electric fill system to 4G.Fig. 4 A shows the instance of the synoptic diagram of electric fill system 300.Electricity fill system 300 comprises three independent electric packing modules 302,304 and 306.Electricity fill system 300 also comprises three the independent modules 312,314 and 316 that are configured for use in various technological operations.For instance, in some embodiments,

module

312 and 316 can be SRD, and module 314 can be annealing station.In other embodiments; Module 312,314 and 316 can be electricity and fills back module (PEM), and it is respectively hung oneself and is configured to after wafer is handled by one in electric packing module 302,304 and 306, to carry out that for example the bevel angle of said wafer removes, the function of back side etch and acid cleaning.

Electrocardio filled chamber 324 during electricity fill system 300 comprises.Middle electrocardio filled chamber 324 is for keeping the chamber as the chemical solution of the electroplating solution in the electric packing module.Electricity fill system 300 also comprises dosing system 326, and it can store and send the chemicaladditives that is used for electroplating solution.Chemical dilution module 322 can store and mix the chemical of treating as the etching reagent among (for instance) PEM.Filter with pump unit 328 and can filter the electroplating solution that is used for electrocardio filled chamber 324 and it is drawn into said electric packing module.

Annealing station 332 can be used for wafer annealing with as pre-treatment.Annealing station 332 also can be used for wafer annealing realizing the copper redistribution, such as preceding text description.Annealing station 332 can comprise several annealing devices that piles up, for example five annealing devices that pile up.But self ground of said annealing device, with pile up separately or with other many device deployment arrangements in annealing station 332.

Central controller 330 provides the electric fill system of operation 300 required electronics and interface control piece.Said central controller comprise one or more storage arrangements usually and through being configured to execute instruction the equipment that makes can carry out one or more treaters according to the method for embodiment described herein.Contain and be useful on control and can be coupled to central controller according to the machine-readable medium of the instruction of the technological operation of embodiment described herein.Central controller 330 also can comprise the power supply that is used for electric fill system 300.

Instrument 340 is passed in friendship can select wafer from wafer cassettes (for example, card casket 342 or card casket 344).

Card casket

342 or 344 can be the opened front formula and unifies container (FOUP).FOUP designs to remain in wafer in the controlled environment securely and safely and to allow to remove the housing of said wafer to be used for being handled or being measured by the instrument that is equipped with suitable load port and robot transport system for warp.Friendship is passed instrument 340 and can be used vacuum accessory or a certain other attachment means to keep wafer.

Friendship is passed instrument 340 and can be connect with annealing station 332,

card casket

342 or 344, transfer station 350 or aligner 348 Jie.Instrument 346 is passed in friendship can be from transfer station 350 near wafer.Transfer station can be to hand over passs slit or the position that

instrument

340 and 346 can wafer be passed in passback under not through the situation of aligner 348.Yet in some embodiments, suitably alignment wafer is accurately to be delivered to electric packing module on the instrument 346 in order to ensure passing in friendship, and instrument 346 is passed in friendship can be by aligner 348 alignment wafer.Friendship is passed instrument 346 and also can wafer is delivered to one in electric packing module 302,304 or 306 or be configured for use in one in three separate modular 312,314 and 316 of various technological operations.

Instance according to the technological operation of the described method of preceding text can be proceeded as follows: (1) is plated to the copper layer on the wafer in electric packing module 304; (2) flushing and drying crystal wafer among the SRD in module 312; And (3) redistribute wafer annealing in module 314 to realize copper.The further copper that is used for the copper redistribution is if desired electroplated, and can repeat said technological operation so.After accomplishing copper layer and annealing process, can in electric packing module 302, cap layer be plated on the wafer.Can in electric packing module 306, copper body layer be plated on the wafer.Also can the electroplating solution that be suitable for technology to be carried out be provided and use said electric packing module interchangeably through giving electric packing module 302,304 and 306.For instance, electric packing module 302 can be used for carrying out the copper plating with a kind of electroplating solution.Can discharge said electroplating solution and be used in from electric packing module 302 and be used for the galvanized electroplating solution replacement of body layer copper the subsequent technique operation.

In some embodiments, module 314 can be annealed wafer by the hot plate resistance electrically heated to copper layer self.In some embodiments, module 314 can comprise in order to wafer annealed ultraviolet (UV) light source or infrared (IR) light source.In some embodiments, electric fill system 300 can comprise in order at plating operating period device of heated chip constantly.This can carry out via wafer backside.

As indicated above, be applicable to the embodiment of in manufacturing environment, using through being configured to allow wafer substrates to cycle through order plating, flushing, drying and annealing process apparatus operating efficiently.In order to realize this, module 312 can be configured to spin rinse moisture eliminator and annealing chamber.By this module 312, wafer will only need be carried to be used for copper plating and annealing operation between electric packing module 304 and module 312.In addition, in some embodiments, electric fill system 300 can make wafer substrates remain in vacuum environment or the inert gas atmosphere with the auxiliary pollution of avoiding wafer.

Fig. 4 B shows the instance of the rough schematic view that substitutes electric fill system to 4G.Note, can comprise the some or all of characteristics in the characteristic that is comprised in the electric fill system of being showed among Fig. 4 A 300 in the electric fill system that Fig. 4 B is showed in the 4G.For instance, the electric fill system showed in the 4G of Fig. 4 B can comprise and be used for that the bevel angle removes or the electricity of other operation is filled back module (PEM).Fig. 4 B mainly shows the instance of some configurations in the possible disparate modules configuration to 4G.

The electric fill system of being showed among Fig. 4 B 400 comprises four plating/wash module 402 and four drying/annealing modules 404.Electricity fill system 400 also comprises and can be similar to the described friendship of preceding text and pass the friendship of

instrument

340 and 346 and pass instrument 406.But each self-contained equipment of said four plating/wash module through being configured to the plating wafer and washing wafer.But each is self-contained through being configured to drying crystal wafer and with said wafer annealed equipment for said four dryings/annealing module.In some embodiments, electric fill system 400 can comprise less module (for example, four modules or six modules) or than multimode (for example, ten modules or 12 modules).In addition, in some embodiments, each in eight modules of being showed in the electric fill system 400 can comprise two, three of self piling up or three with upper module.For instance, plating/wash module 408 can comprise three plating/wash module of self piling up, and drying/annealing module 410 can comprise three dryings/annealing module of self piling up.

Module in the electricity fill system 400 can comprise the equipment that is used for different operating, as described herein.For instance, four plating/wash module 402 can instead be the plating module, and four drying/annealing modules can instead be flushing/drying/annealing module.As another instance, some modules can be flushing/irradiation modules.In some embodiments, flushing/irradiation modules can comprise through configuration so that the atwirl assembly of wafer.

The electric fill system of being showed among Fig. 4 C 430 comprises four plating/wash module 402 and four drying/annealing modules 404.Electricity fill system 430 also comprises the instrument 406 of passing of handing over.The electricity fill system 430 be similar to electric fill system 400, one of them difference be all plating/wash module 402 on a side of electric fill system 430 and four drying/annealing modules 404 on opposite side.The difference of module is configured in fast processing wafer aspect and can be more efficient.For instance, make two transfer distance and/or time minimizations between the module can assist processing wafers apace.

Be similar to the module in the electric fill system 400, the module in the electric fill system 430 can comprise the equipment that is used for different operating.For instance, four plating/wash module 402 can instead be the plating module, and four drying/annealing modules can instead be flushing/drying/annealing module.

The electric fill system of being showed among Fig. 4 D 460 comprises eight platings/flushing/irradiation modules 462 and eight annealing modules 464.Electricity fill system 460 also comprises the instrument 406 of passing of handing over.But each is self-contained through being configured to the equipment of plating wafer, flushing wafer and drying crystal wafer for eight plating/flushing/irradiation modules.But each is self-contained through being configured to wafer annealed equipment for eight modules of annealing.Such as displaying, annealing module 464 is in two groups of annealing modules, wherein each group annealing module comprises four annealing modules of self piling up.

The electric fill system of being showed among Fig. 4 E 470 comprises four plating modules 472 and four flushing/drying/annealing modules 474.Electricity fill system 470 also comprises the instrument 406 of passing of handing over.But each is self-contained through being configured to the equipment of plating wafer for four plating modules.But each is self-contained through being configured to wash wafer, drying crystal wafer and with wafer annealed equipment for four flushing/drying/annealing modules.

The electric fill system of being showed among Fig. 4 F 480 comprises four plating modules 472, four annealing modules 464, four flushing/irradiation modules 482 and four plating modules 484 that overload.Electricity fill system 480 also comprises the instrument 406 of passing of handing over.Such as displaying, plating module 472, flushing/irradiation modules 482 and annealing module 464 self are piled up, thereby form four groups of these modules.As described herein, plating module 472 can be used for plating will be by the copper of the annealing redistribution in the annealing module 464.Also as described herein, overload plating module 484 can be used for plating coating copper body layer.

The electric fill system of being showed among Fig. 4 G 490 comprises eight plating modules 472, eight annealing modules 464, eight flushing/irradiation modules 482 and two plating modules 484 that overload.Electricity fill system 480 also comprises the instrument 406 of passing of handing over.Such as displaying, two plating modules 472 self are piled up, thereby form four groups of these modules.As described herein, plating module 472 can be used for plating will be by the copper of the annealing redistribution in the annealing module 464.Two flushing/irradiation modules 482 also self are piled up, thereby form four groups of these modules.Eight annealing module 464 whole self piling up are piled up thereby form of these modules.Two overload plating modules 484 also self are piled up, and pile up thereby form of these modules.Also as described herein, overload plating module 484 can be used for plating coating copper body layer.

In some embodiments of the described method of preceding text, copper is plated on the backing layer with high sheet resistance.For instance, thin ruthenium layer can have the sheet resistance of about 100 ohm-sq to 200 ohm-sq.The sheet resistance of one deck reduces with its thickness and increases.When the sheet resistance of one deck when being high, there is volts lost (being called end effect) between the center of the edge of wafer (in electroplating device, electrically contacting) and wafer in said edge.This resistance drop is existing during the electroplating technology till the electricity that wafer is crossed in sufficient plating increase is led and reduced volts lost.Resistance drop causes driving near the big voltage of the electroplating reaction of Waffer edge and therefore causes the faster plating speed at Waffer edge place.Therefore, near the recessed profile that increases with respect to the center of wafer of the thickness plating layer can have the edge of wafer.This end effect can roughly increase have sheet resistance greater than near the Waffer edge of the wafer of the inculating crystal layer of about 1 ohm-sq or backing layer through plating layer thickness and can cause edge thickness further to increase and become big gradually with sheet resistance.In general, end effect mainly concentrate on wafer diameter in the influence that produces aspect the variation in thickness outside 15mm to the 30mm place.

When having the surperficial enterprising electroplating of high sheet resistance, can use electroplating solution with low electrical conductivity.When the electroplating solution electric conductivity reduces, to compare with running through the overall voltage drop of electroplating vessel, the relative voltage drop between center wafer and the Waffer edge diminishes.Thickness distribution through coating metal is improved, and with respect to the voltage at center wafer place, is not much bigger because drive the voltage of the reaction at Waffer edge place.In some embodiments, low electrical conductivity (high resistivity) electroplating solution has the resistivity that is higher than about 200 Ω-cm or is higher than about 1000 Ω-cm, and it is significantly higher than the conventional electroplating solution resistivity to 20 Ω-cm into about 2 Ω-cm.Yet electroplating solution can only have up to the resistivity of certain level and still contain enough copper so that available said electroplating solution plating coating copper.

Comprise to electroplating device interpolation auxiliary cathode, screen and resistance unit in order to the alternate manner that reduces end effect.Hereinafter is further discussed all these devices and technology.

Fig. 5 shows the instance of the cross sectional representation of electroplating device.Can be in described electric packing module of preceding text or plating module any one in comprise electroplating device 101.Electroplating device 101 comprises and contains the plating vessel 103 that are shown as the electroplating solution that is in liquid level 105.Wafer 107 can be immersed in the said electroplating solution and by " clam shell " that be installed on the rotatable spindle 111 and keep anchor clamps 109 to keep.Said rotatable spindle allows clam shell 109 with wafer 107 rotations.The clam shell electroplating device is further described in the 6th, 156, and in No. 167 USPs and the 6th, 800, No. 187 USPs, both are incorporated herein by reference said patent.Certainly, can adopt wafer retainer except that the clam shell anchor clamps.

Anode 113 is placed in to electroplate in the vessel 103 and separates with wafer area below the wafer 107 and through anode film 115 (in some embodiments, it is the ion-selective membrane).Zone below the anode film is commonly referred to " anolyte compartment ", and this indoor electrolytic solution is called " anolyte ".Anode film 115 allows to electroplate the anode of vessel and the ionic communication between the cathode zone, prevent simultaneously any particle that the anode place produces get into wafer near and pollute said wafer.Anode film also applicable to redistribution during the electroplating technology electric current and improve the plating homogeneity whereby.Anode film is further described in the 6th, 126, and in No. 798 USPs and the 6th, 569, No. 299 USPs, both are incorporated herein by reference said patent.

Through pump 117 electroplating solution is provided to plating vessel 103 continuously.In general, electroplating solution is upward through anode film 115 and resistance unit 119 flow to the center of wafer 107 and then radially outward reach the leap wafer mobile.In some embodiments, can electroplating solution be provided to the anode region of said plating vessel from the side of electroplating vessel 103.In some embodiments, can electroplating solution be fed in the anode and cathode zone of plating vessel via independent inlet.

Resistance unit 119 is arranged in closely near wafer place (in various embodiments, in about 10 millimeters or about 3 millimeters to 8 millimeters) and serves as the constant current source of wafer.That is to say that near the electrolytic solution electric current 119 pairs of wafers of resistance unit carries out moulding so that distribution of current relatively uniformly to be provided on wafer face.Said element contains a plurality of one dimension through holes, further describes like hereinafter.About the further details of resistance unit can title for " being used for electric plating method and equipment (METHOD AND APPARATUS FOR ELECTROPLATING) " and on November 7th, 2008 file an application the 12/291st; Find in No. 356 patent application, said application case is incorporated herein by reference.

Electroplating solution then overflows to overflow tank 121 from electroplating vessel 103, and is indicated like arrow 123.Can filter (show) electroplating solution and as arrow 125 is indicated makes it turn back to pump 117, thereby the recycling of completion electroplating solution.

Second cathode compartment 127 that contains second negative electrode (that is, surreptitiously flowing negative electrode) 129 can be positioned on the outside of electroplating vessel 103 and the wafer periphery.In general, second negative electrode can be positioned to electroplate in the vessel or several positions in the plating vessel outside.

In some embodiments, electroplating solution overflows to second cathode compartment 127 from the weir wall of electroplating vessel 103.In some embodiments, second cathode compartment 127 separates with plating vessel 103 through the wall with a plurality of openings that covered by the ion-permeable film.Said film allows to electroplate the ionic communication between the vessel 103 and second cathode compartment 127, allows to make electric current to redirect to second negative electrode whereby.The porosity of film can make it not allow particulate material to cross from second cathode compartment 127 and electroplate vessel 103 and cause wafer contamination.Opening in the wall can be taked the form of other shape of circular port, slit or all size.In one embodiment, the slit of said opening for having (for example) about 12 millimeters * 90 millimeters size.May be useful in the fluid that allows between second cathode compartment and the plating vessel and/or other mechanism of ionic communication.Instance comprises film wherein but not impermeable wall provides the electroplating solution in second cathode compartment and electroplates the design of the most of potential barrier between the electroplating solution in the vessel.In these a little embodiments, rigid frame can provide the support to film.

Can use two

DC EPS devices

135 and 137 to control to the electric current that wafer 107 reaches second negative electrode 129 respectively.EPS device 135 has the negative output lead-in wire 139 that is electrically connected to wafer 107 via one or more slip rings, brush or contact (not showing).The positive output lead-in wire 141 of EPS device 135 is electrically connected to and is arranged in the anode 113 of electroplating vessel 103.For instance, said EPS device can have up to about 250 volts output voltage.Similarly, EPS device 137 has negative output lead-in wire 143 that is electrically connected to second negative electrode 129 and the positive output lead-in wire 145 that is electrically connected to anode 113.Perhaps, can use and have a plurality of EPS devices can independently controlling electrical outlet the electric current of varying level is provided to the wafer and second negative electrode.

EPS device

135 and 137 can be connected to unit 147, and unit 147 allows the electric current of the element that is provided to electroplating device 300 and the modulation of current potential.For instance, said unit can allow to electroplate with current controlled or current potential slave mode.Central controller 330 can comprise electric current and voltage level and the programmed instruction that needs change the time of these level that regulation need be applied to the various elements of electroplating device.For instance, it can comprise the programmed instruction that is used for after wafer is immersed into electroplating solution, being converted to from control of Electric potentials at once current control.

During use, both are biased to respect to anode 113 and have negative

potential EPS device

135 and 137 with wafer 107 and second negative electrode 129.This causes the electric current that flow to wafer 107 from anode 113 partly or roughly to be redirect to second negative electrode 129.The described circuit of preceding text also can comprise anti-one or several diodes of counter-rotating here when not expecting current reversal.During electroplating technology unacceptable current feedback possibly take place, be wafer circuit and both common elements of second cathode circuit because be set at the anode 113 of earthing potential.

The level that is applied to the electric current of second negative electrode 129 is set at than is applied to the low value of level of the electric current of wafer 107 usually, and wherein second cathodic current is rendered as a per-cent of wafer current.For instance, 10% the second cathodic currents are corresponding to 10% the electric current to the electric current of wafer that is at the second negative electrode place.Like sense of current used herein is the direction of clean positive ion flux.During electroplating, at wafer surface and second cathode surface electrochemical reduction (Cu for example can take place on both ²⁺+ 2e ^-=Cu ⁰), this causes deposited copper on wafer and both surfaces of second negative electrode.Because electric current is redirect to second negative electrode from wafer, therefore can dwindle the thickness of institute's copper layer of the edge of wafer.This effect is located for 20 millimeters to take place in the outside of wafer usually and is especially outstanding at its outside 10 millimeters places, particularly to backing layer or thin inculating crystal layer execution plating the time.The use of second negative electrode 129 can roughly improve the center-edge ununiformity that is produced by end and field-effect.Can individually or combine other auxiliary cathode or combine a plurality of fixing or dynamic screens to use second negative electrode.

About the further details of auxiliary cathode (comprising secondary and three grades of negative electrodes) can title for " being used for electric plating method and equipment (METHOD AND APPARATUS FOR ELECTROPLATING) " and on June 9th, 2009 file an application the 12/481st; Find in No. 503 patent application, said application case is incorporated herein by reference.Should be understood that auxiliary cathode and associated power supply thereof are optional feature.

One or more screens (for example 149) can be positioned to electroplate (for example, below the resistance unit in the wafer face-down systems) between vessel internal resistance element 119 and the anode 113.Said screen is generally annular dielectric insert, and it is used for the distribution of current curve is carried out moulding and improves galvanized homogeneity, for example those described in the 6th, 027, No. 631 USPs that are incorporated herein by reference.Can adopt those skilled in the art known other screen design and shape.

In general, said screen can be taked Any shape, comprises wedge shape, bar shaped, circle, oval in shape and other geometry designs.Annular insert also within it side diameter place have plurality of patterns, said pattern can improve screen and with desired mode current flux carried out moulding ability.The function of said screen can be different, and this depends on its position in electroplating vessel.Said equipment can comprise any one in static screen and the moulding element of variable field, for example the 6th, 402, and those described in No. 923 USPs and the 7th, 070, No. 686 USPs, both are incorporated herein by reference said patent.Equipment for example also can comprise the segmented anodes or for example the 6th described in the USP the 6th, 497, No. 801; 755, No. 954 and the 6th, 773; In the concentric anode described in No. 571 USPs any one, all said patents all are incorporated herein by reference.Although the shielding insert applicable to improving electroplating evenness, in some embodiments, can not use said shielding insert or can adopt alternative shield configuration.

Screen (for example screen 151) can be positioned to electroplate between vessel internal resistance element 119 and the wafer 107.In some embodiments, screen can be stayed the circumference that exists around resistance unit and sentenced further improvement edge-center plating homogeneity.In some embodiments, screen can stay exist resistance unit just above.In some embodiments, screen can be positioned between resistance unit and the wafer with at least some perforation in the perforation at the outer peripheral areas place of barrier element and the path between the wafer.

Resistance unit

In some embodiments, resistance unit 119 can be many microwell plates or the disk (plate of for example, being processed by the sintering particle of pottery or glass) with continuous three-dimensional pore space network.Porous plate with three-dimensional pore space network comprises the entanglement hole, not only can pass plate vertically upward along the anodic general direction via said entanglement hole ion(ic)current and advance to wafer but also can laterally advance (for example, the center of slave plate is to the edge).The case description of suitable design that is used for these a little plates is in the 7th, 622, No. 024 USP that is incorporated herein by reference.

In some embodiments, resistance unit 119 can comprise hole that in the main body of element, does not roughly communicate with each other or the passage that the path of passing said resistance unit is provided.These a little holes or passage can be linear or nonlinear.These a little holes or passage also can be parallel or be not parallel to the direction of ion(ic)current.

In some embodiments, resistance unit 119 can comprise the direction that is in substantially parallel relationship to ion(ic)current and the linear hole that in the main body of element, does not roughly communicate with each other or passage (that is the one dimension through hole in the resistance unit).This hole or channel arrangement minimize laterally the moving of ion(ic)current in the element.Ion(ic)current with the unidimensional mode (that is, roughly along perpendicular near the resistance unit recently through the vector of plating surface (for example, wafer 107)) flow.This resistance unit is called the one dimension resistance unit.

The resistance unit (being also referred to as one dimension porous high resistance virtual anodes or HRVA) that comprises the one dimension through hole is generally the disk of being processed by the ion resistance material with a plurality of holes of passing its boring (or otherwise making) (also can use other shape).Said hole does not form communication passage and extends through said disk along the direction that is approximately perpendicular to the surface of wafer usually in the main body of disk.The different kinds of ions resistive material can be used for disc body, comprises polycarbonate, Vilaterm, Vestolen PP 7052, PVDF (PVDF), tetrafluoroethylene, polysulfones etc.In some embodiments, disc material in the acid electrolyte environment degradation resistant, handle through machining relatively firmly and easily.

In some embodiments, said resistance unit can be closely near the overall resistance of workpiece and domination electroplating device.When said resistance unit had sufficient resistance with respect to workpiece thin layer resistance, said resistance unit can be similar to the evenly distributing electric current source.In general, just high more by the sheet resistance of the layer of plating, assist the resistance that alleviates the needed resistance unit of end effect just high more, or the resistivity of electroplating solution is just high more.By high-resistance resistance unit, in some embodiments, can use the electrolytic solution of low resistivity and vice versa.

Through workpiece is remained close in resistance unit; Much littler than center-top from the top of element to the Ion paths resistance of the edge of work from element to the ion resistance on the surface of workpiece, thus roughly compensate in the inculating crystal layer of backing layer sheet resistance and above the center of workpiece the electric current of guiding significant quantity.The details that is associated with the resistance unit that uses closely near wafer is discussed further in the 11/040th, No. 359 patent application.

No matter resistance unit is to permit one dimension or the above electric current of one dimension, and in some embodiments, it all can be stretched with workpiece is coextensive.Therefore, when workpiece was wafer, resistance unit had usually approaching just by the diameter of the diameter of the wafer of plating.For instance; The resistance unit diameter can be about 150 millimeters to 450 millimeters on diameter, and wherein about 200 millimeters resistance units are used for 200 millimeters wafers, and about 300 millimeters resistance units are used for 300 millimeters wafers; And about 450 millimeters resistance units are used for 450 millimeters wafers, or the like.Wafer has round-shaped substantially but locates to have in the instance of irregular concavo-convex (the for example flat site of the recess or the cut crystal of wherein stopping) on the edge of therein; Still can use the resistance unit of disc-shape; But can make other compensation adjustment to electroplating device; Described in the 12/291st, No. 356 patent application.

In some embodiments, resistance unit has the diameter (for example, greater than 200 millimeters or 300 millimeters) greater than the diameter of the wafer of treating plating and has the outer edge portion (under the situation of one dimension resistance unit) of atresia.This edge section can be used for periphery around wafer and forms little gap (resistance unit edge section and Waffer edge or wafer keep the peripheral clearance between the bottom of cup) and assist resistance unit is installed in the plating vessel.In some embodiments, the size at atresia resistance unit edge (edge of the tool foraminous part from the external margin of resistance unit to resistance unit) is about 5 millimeters to 50 millimeters.

In some embodiments of one dimension resistance unit, the number of the through hole in the element can be big, and wherein the diameter in each hole is little.In general, the diameter in each hole can be less than about 1/4th of the gap between resistance unit and the workpiece.In some embodiments, the number in hole can be about 5,000 to 12,000.In some embodiments, each hole (at least 95% hole) can have less than about 5 millimeters or less than about 1.25 millimeters diameter (or other major dimension).

Fig. 6 A and 6B show the instance of the view of one dimension resistance unit.Fig. 6 A shows the instance of the vertical view of resistance unit 602, the top surface of its graphic extension resistance unit.Resistance unit 602 comprises a large amount of small dia openings (being shown as stain).Fig. 6 B shows the instance of the cross-sectional view of resistance unit 602.Such as among Fig. 6 B displaying, through hole is approximately perpendicular to the top and the lower surface of resistance unit.

In some embodiments, the thickness of resistance unit is about 5 millimeters to 50 millimeters, for example, and about 10 millimeters to 25 millimeters or about 10 millimeters to 20 millimeters.In some embodiments, the thickness of resistance unit is less than about 15% of wafer diameter.

The resistance of resistance unit that is used for the electroplating device of given electroplating solution depends on several parameters, comprises the porosity of the thickness and the resistance unit of resistance unit.The porosity of resistance unit can be defined at the surperficial occupied area of the occupied area of the lip-deep opening of resistance unit divided by resistance unit by the hole.Notice that this surperficial occupied district of resistance unit is zone of action (that is the district that, contacts with electrolytic solution) and the zone that is used for resistance unit is installed or remained in electroplating device that does not comprise resistance unit.In some embodiments, the porosity of resistance unit can be about 1% to 5% or about 1% to 3%.

In some instances, use high-resistance resistance unit in the application that end effect is bigger therein.For instance, high-resistance resistance unit possibly is being that about 100 ohm-sq are particularly useful during to 200 ohm-sq by the sheet resistance on the surface of plating just.In the embodiment of the described method of preceding text, end effect maybe be for big when directly being plated to copper on the backing layer.For instance, this kind backing layer can be ruthenium.

Can confirm the resistance of said resistance unit through the resistance of the electroplating solution in the volume of confirming to treat to occupy by resistance unit.For instance, it is 288 millimeters the zone of action (652cm that the resistance unit that is used to electroplate 300 millimeters wafers can comprise diameter ²The zone of action) and its thickness be 1.27cm.Therefore, (resistance of electroplating solution in treating the volume that is occupied by resistance unit of the resistivity of Ω-cm) is (* (1.27cm)/(652cm of 1250 Ω-cm) to have 1250 ohm-cms ²) or 2.43 Ω.Resistance unit in electroplating device has under the situation of 2.43% porosity, and said volume only 2.43% can be used for conduction under resistance unit situation not in place.Therefore, the resistance of resistance unit is (2.43 Ω)/(2.43%) or 100.1 Ω.

Table 1 comprises to 1250 Ω-cm electroplating solution and has the resistance of some exemplary one dimension resistance units that diameter is 288 millimeters the zone of action.

The resistance of the exemplary one dimension resistance unit of table 1.

In some embodiments; The resistance of resistance unit (suppose to be used to electroplate the resistance unit of 300 millimeters wafer substrates, its apart from wafer substrates surface about 3 millimeters use to 8 mm distance places) be about 25 ohm to 250 ohm (Ω), about 25 Ω to 75 Ω, about 75 Ω to 150 Ω or about 150 Ω to 250 Ω.

Resistance unit also can be characterized by the active area of its resistance divided by the face of said resistance unit.Therefore, resistance unit can have about 0.04 Ω/cm ²To 0.4 Ω/cm ², about 0.04 Ω/cm ²To 0.1 Ω/cm ², about 0.1 Ω/cm ²To 0.2 Ω/cm ²Or about 0.2 Ω/cm ²To 0.4 Ω/cm ²Every area resistance.

Incorporate the electroplating device that high-resistance resistance unit is arranged into and can have relative high output voltage under typical desired current level, to carry out the EPS device of plating.For instance, can provide the EPS device of about 50 volts or bigger output voltage to use with high-resistance resistance unit (the for example 2X resistance unit in the table 1).More particularly, the EPS device can provide about 100 volts to 175 volts output voltage (wherein 150 volts are representative instance).Can provide in addition more high output voltage (for example, about 150 volts to 250 volts) the EPS device can with have more high-resistance resistance unit (for example, the 4X resistance unit in the table 1) and use together.

When being plated to copper on the ruthenium, the current potential that between wafer and negative electrode, applies depends on the thickness and the wafer diameter of ruthenium layer.For instance, for 300 millimeters wafers, when on the ruthenium layer that copper is plated to 3 nanometer thickness, about 75 volts current potential can use with the 2X resistance unit in the table 1, and this produces the plating electric current of about 0.75 peace.For the said wafer that on the surface of 300 millimeters wafers, has different ruthenium thickness, when being plated to copper on the ruthenium, about 70 volts to 120 volts current potential can use with the 2X resistance unit in the table 1, pacifies to the plating electric current of 1.2 peaces thereby produce about 0.75.

The resistance of resistance unit is that porosity low but that connect continuously produces by the thickness that runs through said resistance unit.In electroplating solution, this can form very high-resistance compact area, and this can be positioned closely near the wafer surface place.By contrast, have thick resistance unit low and non-one dimension porosity and can have the resistance identical, but the electric current steering characteristic of this thick resistance unit maybe be inequality with resistance unit disclosed herein.Electric current in this thick resistance unit can trend towards getting into the central zone of element and along with it upwards flows and flows radially outward.

Another important parameter of one dimension resistance unit is through-hole diameter (or other major dimension) and the ratio of element apart from the distance of wafer.With experiment method and find through microcomputer modelling check subsequently, this ratio should be approximately 1 or littler (for example, less than about 0.8 or less than about 0.25).In some embodiments, this ratio is about 0.1, so that good electroplating evenness performance to be provided.In other words, the diameter in hole can be equal to or less than the distance from the resistance unit to the workpiece.If to the resistance unit distance, the hole can stay its indivedual map of current pictures or " trace " to bore dia in the above on plating layer so, causes the small-scale ununiformity in plating layer whereby greater than wafer.Bore dia value mentioned above is meant the diameter of the hole opening of on the resistance unit face near wafer, measuring.In some embodiments, the nearly face of resistance unit and face far away bore dia on both is identical, but that the hole also can be is gradually thin.

Although the resistance unit of being showed among Fig. 6 A has uniform pore distribution, in other embodiments, resistance unit can have and has on-uniform porosity and distribute or have through stopping to form the zone in the hole that on-uniform porosity distributes.This pore distribution can be with the center that is directed to workpiece than multiple current, so that the high sheet resistance layer of plating more equably.Yet if use on-uniform porosity to distribute, the very thick film that has low sheet resistance so can trend towards plating more unevenly.Through the hole that stops or lack can radially, on position angle or the both direction for uneven.

In some embodiments, resistance unit is roughly parallel to workpiece surface and anode surface location, and the direction that the one dimension hole is parallel between wafer surface and the anode surface is directed.In other embodiments, at least some holes in the said hole are revised to change bore length and to revise the localized contributions of hole to resistance whereby with respect to component thickness its relative angle.

It should be noted that one dimension porous resistance unit is different from so-called diffuser plate.The major function of diffuser plate is the distribution electrolyte flow but not remarkable resistance is provided.Diffuser plate has to constitute usually to be enough to realize roughly the evenly much bigger clean porosity (in from 25% to 80% scope) of electrolyte flow and the opening that in general resistance of electroplating device is had less (inappreciable usually) overall contribution via remarkable viscosity flow resistance.By contrast, the one dimension resistance unit can significantly increase the resistance of electroplating device, and this maybe be for needed for improving electroplating evenness.

Experiment

In a kind of technology, the copper of plating 10 nanometers on the Ru backing layer.By being similar to the 7th, 799, the method for the method described in No. 684 USPs is come the plating coating copper layer.Then wash and dry copper layer.In forming gas, under about 300 ℃, the copper layer is annealed.Repeat said process three times again; That is, carry out four circulations of technological operation.

The SEM of the xsect of wafer (SEM) Photomicrograph is showed the said technological operation filling agent characteristic of 30 nanometers to the width of 60 nanometers of having an appointment fully.The residue near the field the characteristic of wafer is residual copper very less or not, and this redistributes in the said characteristic owing to copper.In the zone that does not comprise any characteristic of wafer, residual copper in the field.

In another technology, the copper of plating 10 nanometers on the Ru barrier layer.By being similar to the 7th, 799, the method for the method described in No. 684 USPs is come the plating coating copper layer.Then wash and dry copper layer.In forming gas, under about 200 ℃, the copper layer is annealed.Repeat said process three times again; That is, carry out four circulations of technological operation.

The SEM Photomicrograph of the xsect of wafer is showed partly the have an appointment characteristic of width of 60 nanometers of filling agent of said technological operation.Some copper of residue on the field of wafer.In the zone that does not comprise any characteristic of wafer, residual copper in the field.

Following embodiment

Apparatus and method for described herein also can combine lithographic patterning instrument or technology to use, and (for instance) is to make or to make semiconductor device, indicating meter, LED, photovoltaic panel etc.Usually, (although needn't) these a little instrument/technologies will be used in common making facility or carry out together.Lithographic patterning to film generally includes the some or all of steps in the following steps, and each step realizes by several possible instruments: (1) uses spin coating or Spray painting tool on workpiece (that is substrate), to apply photo-resist; (2) use hot plate, stove or UV tools of solidifying that photo-resist is solidified; (3) by instrument (for example, wafer stepper) said photo-resist is exposed to visible, UV or x ray light; (4) said resist is developed so that tool using (for example, wet corrosion cutting) comes optionally to remove resist and patterned whereby; (5) through use dry type or plasma assisted etch instrument with the resist design transfer in underlie film or workpiece; And (6) tool using (for example, RF or microwave plasma corrosion inhibitor stripper) removes said resist.

Claims

1. equipment, it comprises:

Plating chamber, it is through being configured to keep electrolytic solution;

The workpiece retainer, it remains in workpiece in the said plating chamber through being configured to, and said workpiece comprises the surface with some fringe regions; And

Element; It comprises the ion resistance main body; Having some perforation in the said main body makes said perforation in said main body, not form communication passage; Wherein said perforation allows to carry said electrolytic solution via said element; Wherein said element is through locating to have towards the surface on the said surface of said workpiece; Wherein said equipment makes during the plating said surface of said element be positioned at apart from the said surface of said workpiece about 10 millimeters through disposing, and wherein roughly all said perforation have at the said lip-deep opening towards the said surface of said workpiece of said element and are not more than about 5 millimeters major dimension, and the porosity of wherein said element is about 1% to 3%.

2. equipment according to claim 1, the said porosity of wherein said element corresponding to said perforation at the occupied area of the said lip-deep said opening of said element divided by the occupied area in the said surface of said element.

3. equipment according to claim 1, wherein said element along when said workpiece during by said workpiece retainer maintenance the direction perpendicular to the said surface of said workpiece have a thickness, and the said thickness of wherein said element is about 5 millimeters to 50 millimeters.

4. equipment according to claim 1, the resistance in the occupied volume of wherein said element is about 25 ohm to 250 ohm.

5. equipment according to claim 1, the resistance of wherein said element are every square centimeter about 0.04 ohm to 0.4 ohm of said surface of said element.

6. equipment according to claim 1, wherein said element surface and said workpiece surface are roughly coextensive to be stretched.

7. equipment according to claim 1, wherein said element has about 150 millimeters to 450 millimeters diameter.

8. equipment according to claim 1, wherein said element comprise having about 5,000 disks to 12,000 perforation.

9. equipment according to claim 1, wherein said element comprise uneven perforation distributions in the central zone of said element, and wherein said element comprises uniform perforation distributions in the outer peripheral areas of said element.

10. equipment according to claim 1, it further comprises:

One or more electrical contacts, it is electrically connected to said surface through one or more positions that are configured on the fringe region on the said surface of said workpiece; And

EPS device, but itself and said electrical contact, anode and unit operable communication.

11. equipment according to claim 1, it further comprises:

Screen, it is positioned between said element and the said workpiece with at least some perforation in the said perforation in the outer peripheral areas that stops said element and the path between the said workpiece.

12. equipment according to claim 1, it further comprises and is configured for use in second negative electrode that the part that makes ion(ic)current turns to from the said fringe region of said workpiece.

13. equipment according to claim 12, wherein said second negative electrode are housed in second Room on the outside of said plating chamber, and wherein said second Room and said plating chamber ionic communication.

14. equipment according to claim 1, it further comprises:

Unit, it is operated metal-plated through being configured to control to the plating on the said workpiece.

15. equipment according to claim 1, it further comprises:

The spin rinse moisture eliminator, it is through being configured to wash said electrolytic solution and dry said workpiece from said workpiece.

16. equipment according to claim 1, wherein said spin rinse moisture eliminator are further through being configured to said workpiece annealing.

17. equipment according to claim 1, it further comprises:

Annealing chamber, it is through being configured to said workpiece annealing.

18. system that comprises an equipment according to claim 1 and a step unit.

19. an equipment, it comprises:

Plating chamber, it is through being configured to keep electrolytic solution;

The workpiece retainer, it remains in workpiece in the said plating chamber through being configured to, and said workpiece comprises the surface with some fringe regions;

Element; It comprises the ion resistance main body; Having some perforation in the said main body makes said perforation in said main body, not form communication passage; Wherein said perforation allows to carry said electrolytic solution via said element; Wherein said element is through locating to have towards the surface on the said surface of said workpiece; Wherein said equipment makes during the plating said surface of said element be positioned at apart from the said surface of said workpiece about 10 millimeters through disposing, and wherein roughly all said perforation have at the said lip-deep opening towards the said surface of said workpiece of said element and are not more than about 5 millimeters major dimension, and the porosity of wherein said element is about 1% to 3%; And

Negative electrode, its through configuration so that the part of ion(ic)current turn to from the said fringe region of said workpiece.

20. an equipment, it comprises:

Plating chamber, it is through being configured to keep electrolytic solution;