CN108322048A - BUCK converters and its input/output control circuit - Google Patents
BUCK converters and its input/output control circuit Download PDFInfo
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- CN108322048A CN108322048A CN201810072927.4A CN201810072927A CN108322048A CN 108322048 A CN108322048 A CN 108322048A CN 201810072927 A CN201810072927 A CN 201810072927A CN 108322048 A CN108322048 A CN 108322048A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
Abstract
A kind of BUCK converters of present invention offer and its input/output control circuit, input/output control circuit include：Duty ratio logic control circuit and inductance peak-to-valley value logic control circuit；Duty ratio logic control circuit includes：First input end is connected with pulse width modulated comparator；Second input terminal is connected with inductance peak-to-valley value logic control circuit；Third input terminal is connected with turn-on time comparator；Logic gates, including the first NOT gate, the output of first NOT gate is carried out to first and door of logic and operation with pulse width modulated comparator output, second NOT gate and the output of turn-on time comparator are carried out second and door of logic and operation and carry out first or door of logic or operation with the output of inductance peak-to-valley value logic control circuit with door by second by the second NOT gate.BUCK converters in the present invention have fast transient response, when load sends short circuit exception, can stablize inductive current and be limited between peak value and valley, achieve the purpose that wide scope input and output.
Description
Technical field
The invention belongs to power electronics fields, and electricity is controlled more particularly to a kind of BUCK converters and its input and output
Road.
Background technology
Buck converters are also referred to as decompression transducer, are that a kind of output voltage is less than the single tube of input voltage not isolated DC
Converter.Currently, the BUCK converters based on adaptive turn-on time (ACOT) control framework, the expansion as sluggish control framework
Exhibition, it is simple to have a system structure, fast linear response and load response may be implemented, and it is low to be only applicable to high input voltage substantially
The application of output voltage, it is fresh to see there is the case where applied to wide scope input and output less.And the input and output of wide scope are answered
With more is all to be controlled using the voltage mode of conventional fixed-frequency, but loop structure is more complex, loop stability compensation
Also more complex, transient response is slower.
Lacking 100% Duty ratio control can make the BUCK converters based on ACOT frameworks not expand to greatest extent
The application of wide scope input and output, and load can not be jumped to greatest extent from underloading, output voltage is carried out soon when overloaded
Velocity modulation section.The minimum turn-on time of fixed setting, it is also difficult to the operating lag of matching inductance valley Current-Limiting Comparator.If setting is most
Small turn-on time (Min-off-time) is excessive, then influences transient response；If the minimum turn-on time (Min-off-time) of setting
It is too small, then influence valley current limliting of the BUCK converters when load sends short circuit.In addition valley inductor Current limited Control is only designed, then
Control of the BUCK converter applications to inductive current overload or short circuit when 100% duty ratio is cannot be satisfied, is especially being loaded
It sends from underloading to when the heavy duty big saltus step of transmission.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of BUCK converters and its inputs
Output control circuit, for solve in the prior art BUCK converters can not effectively expand to greatest extent wide scope input it is defeated
The application gone out, and load can not be jumped to greatest extent from underloading and asked when overloaded what output voltage was quickly adjusted
Topic.
In order to achieve the above objects and other related objects, the present invention provides a kind of input and output control electricity of BUCK converters
Road, the BUCK converters include：Include the adaptive turn-on time generation circuit of turn-on time comparator, pulsewidth modulation is compared
Device, rest-set flip-flop, closed loop control logic and are opened power switch driver circuit including PMOS power switch and NMOS power
The power stage output circuit of pass；The input/output control circuit of the BUCK converters includes：Duty ratio logic control circuit and
Inductance peak-to-valley value logic control circuit；The duty ratio logic control circuit includes：First input end, with the pulsewidth modulation ratio
Output end compared with device is connected；Second input terminal is connected with the output end of the inductance peak-to-valley value logic control circuit；Third inputs
End, is connected with the output end of the turn-on time comparator；Logic gates, including it is connected to the first of second input terminal
First NOT gate output is carried out first and door of logic and operation by NOT gate with the output of the pulse width modulated comparator, with
The output of second NOT gate and the turn-on time comparator is carried out logical AND fortune by the second NOT gate of first input end connection
Second calculated carries out logic or fortune with door and by the output of described second and door and the inductance peak-to-valley value logic control circuit
First or the door calculated；Wherein, described first is connected with door with the ends S of the rest-set flip-flop, described first or door and the RS touch
The ends R for sending out device are connected.
In one embodiment of the invention, the inductance peak-to-valley value logic control circuit includes：Inductance peak detection logic
Circuit, inductor valley detect logic circuit and respectively by the output of the inductance peak detection logic circuit and the inductor valleys
The output for detecting logic circuit carries out second or door of logic or operation；Described second or the output end of door be the inductance peak
The output end of valley logic control circuit.
In one embodiment of the invention, the phase is turned off in PMOS power switch conducting and the NMOS power switch
Between, the inductance peak detection logic circuit is detected inductive current；The NMOS power switch conducting and it is described
During PMOS power switch turns off, the inductor valley detection logic circuit is detected inductive current.
In one embodiment of the invention, the inductance peak detection logic circuit includes peak value Current-Limiting Comparator and peak value
Logic circuit；The inductor valley detection logic circuit includes valley Current-Limiting Comparator and valley logic circuit.
In one embodiment of the invention, the NMOS power switch conducting starts to the valley Current-Limiting Comparator to export
From it is logically high be turned to logic low during, it is height that the valley logic circuit, which forces the output of valley Current-Limiting Comparator output,
Level.
In one embodiment of the invention, when inductive current is reduced to cut-off current or less, the valley current limliting ratio is controlled
Output compared with device is low level.
In one embodiment of the invention, the rest-set flip-flop is by two nor gate input, output end interconnection groups
At.
The embodiment of the present invention also provides a kind of BUCK converters, and the BUCK converters include that BUCK as described above becomes
The input/output control circuit of parallel operation.
In one embodiment of the invention, the adaptive turn-on time generation circuit includes：It is connected to described lead in turn
The controlled current source of logical time comparator in-phase input end, timing capacitor and time switch；The turn-on time comparator it is anti-
Output voltage terminal is connected to input terminal.
In one embodiment of the invention, the in-phase input end of the pulse width modulated comparator connects error amplifier, instead
Output voltage sampling and synchronous slope generating circuit are connected to input terminal.
As described above, the BUCK converters and its input/output control circuit of the present invention, have the advantages that：
BUCK converters in the present invention can keep fast transient response possessed by ACOT frameworks always, and negative
When carrying transmission short circuit exception, BUCK converters, which can also stablize inductive current, be limited between peak value and valley, reach wide model
The purpose of input and output is enclosed, and the transient response performance and security reliability of BUCK converters can be promoted to greatest extent,
Extend practical ranges.
Description of the drawings
Fig. 1 is shown as the integrated circuit theory structure schematic diagram of the BUCK converters of the present invention.
Fig. 2 is shown as the circuit diagram of the input/output control circuit of the BUCK converters of the present invention.
Fig. 3 is shown as the control logic schematic diagram of the duty ratio logic control circuit of the BUCK converters of the present invention.
Fig. 4 is shown as the control schematic diagram of the generation load jump of the BUCK converters of the present invention.
Fig. 5 is shown as the control logic schematic diagram of the inductance peak-to-valley value logic control circuit of the BUCK converters of the present invention.
Fig. 6 is shown as the control minimum turn-on time that Cycle by Cycle includes valley current limliting information in the BUCK converters of the present invention
Control sequential figure.
Fig. 7 is shown as the electric operation control circuit figure of adaptive turn-on time generation circuit in the BUCK converters of the present invention.
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It please refers to Fig.1 to Fig. 7, it should be noted that the diagram provided in following embodiment only illustrates in a schematic way
The basic conception of the present invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
The purpose of the present embodiment is that a kind of BUCK converters and its input/output control circuit are provided, it is existing for solving
BUCK converters can not effectively expand to the application of wide scope input and output to greatest extent in technology, and can not be to greatest extent
The problem of quickly being adjusted to output voltage when overloaded is jumped to loading from underloading.The present invention's described in detail below
The principle and embodiment of BUCK converters and its input/output control circuit makes those skilled in the art not need creative labor
The dynamic BUCK converters and its input/output control circuit for being appreciated that the present invention.
The BUCK transformation that the BUCK converters and its input/output control circuit of the present embodiment are controlled based on traditional ACOT
Device integrated circuit introduces 100% Duty ratio control and the minimum turn-on time (Min-off- comprising valley current limliting CL Compare Logic
Time it) control and peak inductive current current limliting and valley inductor current current limliting and deposits, BUCK converters can be made to adapt to wide model
Enclose the application demand of input and output.The BUCK converters and its input/output control circuit of the present embodiment are carried out specifically below
It is bright.
The present embodiment provides a kind of BUCK converters, as shown in Figure 1, the BUCK converters 1 include：Including turn-on time
The adaptive turn-on time generation circuit 11 of comparator A1 (Cycle by Cycle compares frequency locking error Vferr and timing voltage Vct), pulsewidth
Modulate comparator A2 (Cycle by Cycle relative error voltage Vea and synchronous slope Vramp), rest-set flip-flop 12 (rest-set flip-flop 12 it is defeated
Go out the power switch work of logic Duty closed-loop control BUCK converters 1, when Duty is logically high, power power PMOS are led
Logical, power power NMOS are closed；When Duty logics are low, power power PMOS are closed, power power NMOS conductings.
Duty logics are the duty ratio that logically high time accounting is BUCK converters 1 within the period), closed loop control logic 13
(closed loop control logic 13 and power switch driver circuit 14 control BUCK converters 1 with power switch driver circuit 14
The working condition of closed-loop control and power switch and generate the non-overlapping power power PMOS of two-phase driving voltage GH and
The driving voltage GL of power power NMOS), including PMOS power switch (PMOS shown in Fig. 1) and NMOS power switch
Power stage output circuit.Power stage output circuit includes mainly PMOS power switch (PMOS shown in Fig. 1), NMOS power
Switch (NMOS shown in Fig. 1), filter inductance L, filter capacitor C and output loading, power stage output circuit undertake BUCK
1 power of converter and energy output.
Wherein, the adaptive turn-on time generation circuit 11 includes：It is connected to the turn-on time comparator A1 in turn
The controlled current source A of in-phase input end0(generating the electric current gm*Vin directly proportional to Vin), timing capacitor Ct and time switch Q；
The reverse input end of the turn-on time comparator A1 connects output voltage terminal.The homophase input of the pulse width modulated comparator A2
End connection error amplifier A3 (by detecting output feedback reference Vref and output feedback signal Vfb in real time, is obtained amplified
Error voltage Vea, as loop pulsewidth modulation foundation), reverse input end connects output voltage sampling and is generated with synchronous slope
Circuit 15 is (for generating output voltage feedback signal Vfb and the slope synchronous with inductive current letter needed for ACOT control models
Number Vramp).
In this present embodiment, the BUCK converters 1 further include input/output control circuit 10, as depicted in figs. 1 and 2,
The input/output control circuit 10 includes：Duty ratio logic control circuit 110 and inductance peak-to-valley value logic control circuit 120.
In this present embodiment, as shown in figure 3, the rest-set flip-flop 12 intersects company by two nor gate input, output ends
Connect composition.100% duty ratio and Min-off-time control logics used in the present embodiment is as shown in figure 3, rest-set flip-flop 12
Output logic Q be DUTY CYCLE, for control power switch conducting turn off.When PWM mode is run, DUTY
CYCLE=H (high level), PMOS power switch (PMOS shown in Fig. 1) conducting and NMOS power switch are (shown in Fig. 1
NMOS it) turns off；DUTY CYCLE=L (low level), NMOS power switch (NMOS shown in Fig. 1) conducting and PMOS power are opened
Close (PMOS shown in Fig. 1) shutdown.
Specifically, in this present embodiment, as shown in figure 3, the duty ratio logic control circuit 110 includes：First input
It holds at (ends Vset shown in Fig. 3), is connected with the output end of the pulse width modulated comparator A2；Second input terminal is (shown in Fig. 3
The ends OCP), be connected with the output end of the inductance peak-to-valley value logic control circuit 120；Third input terminal is (shown in Fig. 3
The ends Vrset), it is connected with the output end of the turn-on time comparator A1；Logic gates 111, including it is connected to described second
First NOT gate 111a of input terminal (ends OCP shown in Fig. 3), by the first NOT gate 111a outputs and the pulsewidth modulation ratio
Output compared with device A2 carries out first and door 111b of logic and operation, is connect with first input end (ends Vset shown in Fig. 3)
The second NOT gate 111c, the output of the second NOT gate 111c and the turn-on time comparator A1 are subjected to logic and operation
Second patrols with door 111d and by described second and door 111d and the output of the inductance peak-to-valley value logic control circuit 120
Volume or operation first or door 111e；Wherein, described first is connected with door 111b with the ends S of the rest-set flip-flop 12, and described
One or door 111e is connected with the ends R of the rest-set flip-flop 12.
The duty ratio logic control circuit 110 is by the inverted signal of the output logic Vset of pulse width modulated comparator A2 and leads
The output logic Vrset of logical time comparator A1 does logical AND.When the mistake that output voltage Vout and input voltage vin move closer to
The output logic Vset of Cheng Zhong, pulse width modulated comparator A2 are logically high by the maintenance for stepping into 100% duty ratio, shield and lead
Logical time comparator A1 exports the control to rest-set flip-flop 12R so that BUCK converters 1 step into the operation of 100% duty ratio.
The duty ratio logic control circuit 110 can not only be such that BUCK converters 1 are transported automatically into 100% duty ratio in stable state
Row keeps input Vin and output Vout straight-through, is also beneficial to accelerate load response.Load jump signal occurs for BUCK converters 1 such as
Shown in Fig. 4, when BUCK converters 1 are when occurring to load upper saltus step, output voltage Vout declines lead to that error amplifier A3's is defeated
Go out Vea raisings.When synchronizing ramp signal Vramp by than stable state at this time later be increased beyond Vea, during which pulse width modulated comparator
The output Vset of A2 just remains always logically high, and BUCK converters 1 enter 100% duty ratio and run, and maximally reduce defeated
The shake for going out voltage, improves transient response performance.
In order to adapt to wide scope input and output operation, need to design inductance peak value current limliting and inductor valley current limliting simultaneously
It deposits, and is also the monitoring inductive current of Cycle by Cycle.The Current limited Control that the present embodiment is used is as shown in Figure 5.
In this present embodiment, the inductance peak-to-valley value logic control circuit 120 includes：Inductance peak detection logic circuit
121, inductor valley detects logic circuit 122 and respectively by the output of the inductance peak detection logic circuit 121 and the electricity
The output for feeling valley detection logic circuit 122 carries out second or the door 123 of logic or operation.
In this present embodiment, the inductance peak detection logic circuit 121 includes peak value Current-Limiting Comparator CMP1 and peak value
Logic circuit 121a；The inductor valley detection logic circuit 122 includes valley Current-Limiting Comparator CMP2 and valley logic circuit
122a。
Specifically, in the PMOS power switch (PMOS shown in Fig. 1) conducting and described NMOS power switch (Fig. 1
Shown in NMOS) shutdown during, the inductance peak detection logic circuit 121 is detected inductive current；Described
During NMOS power switch (NMOS shown in Fig. 1) is connected and the PMOS power switch (PMOS shown in Fig. 1) turns off,
The inductor valley detection logic circuit 122 is detected inductive current.
Described second or door 123 output end be the inductance peak-to-valley value logic control circuit 120 output end.Current limliting
Logic export OCP be peak value current limliting logic POCP and valley current limliting logic VOCP logic or.As long as monitor inductance short circuit or
Overload, OCP will be set to logically high, force set the input S of rest-set flip-flop 12 as logic low, R is logically high, closing PMOS work(
Rate switchs (PMOS shown in Fig. 1), conducting NMOS power switch (NMOS shown in Fig. 1) so that inductive current declines.Most
Whole inductive current will be controlled between peak value current limliting and valley current limliting.
In this present embodiment, NMOS power switch (NMOS shown in Fig. 1) conducting starts to the valley current limliting
Comparator CMP2 output from it is logically high be turned to logic low during, the valley logic circuit 122a forces the valley current limliting ratio
Output compared with device CMP2 outputs is high level.When inductive current is reduced to cut-off current or less, controls the valley current limliting and compare
The output of device CMP2 is low level.
Specifically, minimum turn-on time (Min-off-time) the control sequential such as Fig. 6 for the Cycle by Cycle that the present embodiment is used
It is shown.Cycle by Cycle is detected by DUTY CYCLE and NMOS power switch (NMOS shown in Fig. 1) grid voltage GD_L
In DUTY CYCLE=H, (PMOS power switch (PMOS shown in Fig. 1) is connected the output VCMP of valley Current-Limiting Comparator CMP2
Turned off with NMOS power switch (NMOS shown in Fig. 1)) during, pressure is preset as logically high (detected in normal valley current limliting
When, it is logically high to show that inductive current has been more than valley current limliting).And in DUTY CYCLE=L, (NMOS power switch is (shown in Fig. 1
NMOS) conducting and PMOS power switch (PMOS shown in Fig. 1) shutdown) after, just discharge to valley Current-Limiting Comparator
CMP2 exports the pressure control of VCMP, so that it is started normal valley current limliting and judges.When basic Cycle by Cycle valley current limliting detects
Sequence from DUTY CYCLE are logically high as shown in fig. 6, be turned to logic low, i.e. NMOS power switch (NMOS shown in Fig. 1) is led
The beginning is opened up, to valley Current-Limiting Comparator CMP2 outputs from the logically high this period for being turned to logic low, valley current limliting is forced to be patrolled
It is height to collect VOCP so that it is logically high that rest-set flip-flop 12, which exports R, and S is logic low, and holding NMOS power switch is (shown in Fig. 1
NMOS it) is connected.
If inductive current is less than valley current limliting at this time, after a valley Current-Limiting Comparator CMP2 operating lag,
It exports VCMP and becomes logic low, and then valley current limliting logic VOCP is made to become logic low, discharge the control for PWM loops.If at this time
Inductive current is higher than valley current limliting, then is only reduced to cut-off current hereinafter, the CMP2 outputs of valley Current-Limiting Comparator in inductive current
Logic VCMP just becomes logic low, and otherwise valley current limliting logic VOCP will control rest-set flip-flop 12 and input S maintenance logic lows and R maintenances
It is logically high, pressure make NMOS power switch (NMOS shown in Fig. 1) conducting until inductive current be reduced to valley current limliting hereinafter,
Realize the Cycle by Cycle Min-off-time controls comprising valley current limliting information.Fig. 7 is used to be produced from for what the present embodiment was used
Turn-on time (Ton) comparator control of turn-on time is adapted to, output logic Vrset is in stable state as reset rest-set flip-flop 12
One of control condition of output.
The input/output control circuit 10 of BUCK converters 1 realizes answering for from 0% to 100% duty ratio in the present invention
With.VOUT=0.5V-3.4V is exported, answering for IOUT=0A-3A is loaded in input VIN=2.5V-5.5V by simulating, verifying
In the case of, BUCK converters 1 can keep fast transient response possessed by ACOT frameworks always, and short in load transmission
When the exception of road, BUCK converters 1 also can by inductive current stablize be limited between peak value and valley reach wide scope input it is defeated
The purpose gone out.
In conclusion the BUCK converters in the present invention can keep fast transient possessed by ACOT frameworks to ring always
Answer, and load send short circuit it is abnormal when, BUCK converters inductive current can also be stablized be limited in peak value and valley it
Between, achieve the purpose that wide scope input and output, and can be promoted to greatest extent BUCK converters transient response performance and
Security reliability extends practical ranges.So the present invention effectively overcomes various shortcoming in the prior art and has height
Industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of input/output control circuit of BUCK converters, which is characterized in that the BUCK converters include：Including conducting
The adaptive turn-on time generation circuit of time comparator, pulse width modulated comparator, rest-set flip-flop, closed loop control logic,
Power switch driver circuit and power stage output circuit including PMOS power switch and NMOS power switch；The BUCK becomes
The input/output control circuit of parallel operation includes：Duty ratio logic control circuit and inductance peak-to-valley value logic control circuit；
The duty ratio logic control circuit includes：
First input end is connected with the output end of the pulse width modulated comparator；
Second input terminal is connected with the output end of the inductance peak-to-valley value logic control circuit；
Third input terminal is connected with the output end of the turn-on time comparator；
Logic gates, including it is connected to the first NOT gate of second input terminal, by first NOT gate output and the arteries and veins
The output of wide modulation comparator carries out first and door of logic and operation, and the second NOT gate being connect with first input end will be described
The output of second NOT gate and the turn-on time comparator carries out the second of logic and operation with door and by described second and door
First or door of logic or operation are carried out with the output of the inductance peak-to-valley value logic control circuit；Wherein, described first and door
Be connected with the ends S of the rest-set flip-flop, described first or door be connected with the ends R of the rest-set flip-flop.
2. the input/output control circuit of BUCK converters according to claim 1, which is characterized in that the inductance peak valley
Value logic control circuit includes：Inductance peak detection logic circuit, inductor valley detect logic circuit and respectively by the inductance
The output of peak detection logic circuit and the output of inductor valley detection logic circuit carry out logic or operation second or
Door；Described second or door output end be the inductance peak-to-valley value logic control circuit output end.
3. the input/output control circuit of BUCK converters according to claim 2, which is characterized in that in the PMOS work(
During rate switch conduction and the NMOS power switch turn off, the inductance peak detection logic circuit examines inductive current
It surveys；During NMOS power switch conducting and PMOS power switch shutdown, the inductor valley detects logic circuit
Inductive current is detected.
4. the input/output control circuit of BUCK converters according to claim 2 or 3, which is characterized in that the inductance
Peak detection logic circuit includes peak value Current-Limiting Comparator and peak value logic circuit；The inductor valley detects logic circuit
Valley Current-Limiting Comparator and valley logic circuit.
5. the input/output control circuit of BUCK converters according to claim 4, which is characterized in that the NMOS power
Switch conduction start to the valley Current-Limiting Comparator output from it is logically high be turned to logic low during, the valley logic circuit
It is high level to force the output of the valley Current-Limiting Comparator output.
6. the input/output control circuit of BUCK converters according to claim 5, which is characterized in that dropped in inductive current
When as low as below cut-off current, the output for controlling the valley Current-Limiting Comparator is low level.
7. the input/output control circuit of BUCK converters according to claim 1 or 2, which is characterized in that the RS is touched
Hair device is made of two nor gate input, output end interconnections.
8. a kind of BUCK converters, which is characterized in that the BUCK converters include as claim 1 is any to claim 7
The input/output control circuit of BUCK converters described in claim.
9. BUCK converters according to claim 8, which is characterized in that the adaptive turn-on time generation circuit packet
It includes：It is connected to the controlled current source of the turn-on time comparator in-phase input end, timing capacitor and time switch in turn；It is described
The reverse input end of turn-on time comparator connects output voltage terminal.
10. BUCK converters according to claim 8 or claim 9, which is characterized in that the pulse width modulated comparator it is same mutually defeated
Enter end connection error amplifier, reverse input end connects output voltage sampling and synchronous slope generating circuit.
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| CN201810072927.4A CN108322048B (en) | 2018-01-25 | 2018-01-25 | BUCK converter and its input/output control circuit |
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| CN201810072927.4A CN108322048B (en) | 2018-01-25 | 2018-01-25 | BUCK converter and its input/output control circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110708048A (en) * | 2019-12-16 | 2020-01-17 | 峰岹科技（深圳）有限公司 | Hysteresis comparator circuit |
| CN113708626A (en) * | 2021-10-28 | 2021-11-26 | 南京模砾半导体有限责任公司 | Hundred percent duty cycle generating circuit suitable for COT voltage converter |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110204859A1 (en) * | 2010-02-19 | 2011-08-25 | Kabushiki Kaisha Toshiba | Switching power supply apparatus |
| US8169806B2 (en) * | 2009-02-12 | 2012-05-01 | Apple Inc. | Power converter system with pulsed power transfer |
| CN105245103A (en) * | 2014-07-01 | 2016-01-13 | 德克萨斯仪器股份有限公司 | DC to DC converter and pwm controller with adaptive compensation circuit |
| CN206099754U (en) * | 2016-09-30 | 2017-04-12 | 洛阳隆盛科技有限责任公司 | Wide input voltage range's auxiliary source circuit |
| CN107508476A (en) * | 2017-03-17 | 2017-12-22 | 苏州智浦芯联电子科技股份有限公司 | A kind of dutycycle counting circuit for Switching Power Supply line loss compensation |
| CN107546964A (en) * | 2017-08-22 | 2018-01-05 | 成都芯辰微电子技术有限公司 | A kind of loop control system and control method of DC DC converters |
-
2018
- 2018-01-25 CN CN201810072927.4A patent/CN108322048B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8169806B2 (en) * | 2009-02-12 | 2012-05-01 | Apple Inc. | Power converter system with pulsed power transfer |
| US20110204859A1 (en) * | 2010-02-19 | 2011-08-25 | Kabushiki Kaisha Toshiba | Switching power supply apparatus |
| CN105245103A (en) * | 2014-07-01 | 2016-01-13 | 德克萨斯仪器股份有限公司 | DC to DC converter and pwm controller with adaptive compensation circuit |
| CN206099754U (en) * | 2016-09-30 | 2017-04-12 | 洛阳隆盛科技有限责任公司 | Wide input voltage range's auxiliary source circuit |
| CN107508476A (en) * | 2017-03-17 | 2017-12-22 | 苏州智浦芯联电子科技股份有限公司 | A kind of dutycycle counting circuit for Switching Power Supply line loss compensation |
| CN107546964A (en) * | 2017-08-22 | 2018-01-05 | 成都芯辰微电子技术有限公司 | A kind of loop control system and control method of DC DC converters |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110708048A (en) * | 2019-12-16 | 2020-01-17 | 峰岹科技（深圳）有限公司 | Hysteresis comparator circuit |
| CN110708048B (en) * | 2019-12-16 | 2020-04-24 | 峰岹科技（深圳）有限公司 | Hysteresis comparator circuit |
| CN113708626A (en) * | 2021-10-28 | 2021-11-26 | 南京模砾半导体有限责任公司 | Hundred percent duty cycle generating circuit suitable for COT voltage converter |
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|---|---|
| CN108322048B (en) | 2019-05-31 |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co.,Ltd. Address before: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: FUZHOU ROCKCHIP ELECTRONICS Co.,Ltd. |
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Application publication date: 20180724 Assignee: Shanghai hanmai Electronic Technology Co.,Ltd. Assignor: Ruixin Microelectronics Co.,Ltd. Contract record no.: X2023350000313 Denomination of invention: BUCK Converter and Its Input Output Control Circuit Granted publication date: 20190531 License type: Common License Record date: 20230718 |