CN108305921B - A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof - Google Patents
A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof Download PDFInfo
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- CN108305921B CN108305921B CN201711396721.9A CN201711396721A CN108305921B CN 108305921 B CN108305921 B CN 108305921B CN 201711396721 A CN201711396721 A CN 201711396721A CN 108305921 B CN108305921 B CN 108305921B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Abstract
The invention discloses a kind of light emitting diode (LED) chip with vertical structure; including substrate layer and the bonded layer being set on substrate layer; the X-dots/Ag/Y mirror layer that bonded layer is equipped with the first protective layer and is set on first protective layer; the InGaN/GaN quantum well layer that X-dots/Ag/Y mirror layer is equipped with p-GaN layer and is set in p-GaN layer, the n-electrode layer that InGaN/GaN quantum well layer is equipped with n-GaN layers and is set on n-GaN layer.The invention also discloses a kind of preparation methods of light emitting diode (LED) chip with vertical structure.Good adhesion between light emitting diode (LED) chip with vertical structure mirror layer of the present invention and conductive substrates, prevents reflecting layer in subsequent preparation process from falling off, and also ensures good Ohmic contact between p-GaN layer and Ag layers.
Description
Technical field
The present invention relates to LED technology field, in particular to a kind of light emitting diode (LED) chip with vertical structure and the light emitting diode (LED) chip with vertical structure
Preparation method.
Background technique
As LED is in the gradually application of lighting area, the requirement that white light LED light is imitated in market is higher and higher.GaN base is vertical
There is structure LED single side to go out light, good heat-sinking capability, be able to bear Bulk current injection, and such a vertical structure LED
Chip can be equivalent to several formal dress fabric chips, and equivalent cost only has the part of positive assembling structure, at low cost, performance is excellent.
Therefore, GaN base light emitting diode (LED) chip with vertical structure be market institute to and semiconductor lighting develop inexorable trend.With traditional plane
Structure LED is compared, and vertical structure LED has many advantages: (1) two electrodes of vertical structure LED are respectively in the two sides of LED, electricity
Stream almost all flows vertically through epitaxial layer, not the electric current of lateral flow, homogeneous current distribution, and the heat of generation is reduced；(2) it adopts
Thermally conductive bad Sapphire Substrate is removed with the method for bonding and removing, changes good conductivity and the lining with high heat conductance into
Bottom can effectively radiate；(3) n-GaN layers are light-emitting surface, this layer has certain thickness, convenient for production surface micro-structure, to mention
Highlight extract efficiency.In short, compared with conventional planar structure, vertical structure light out, in terms of there is apparent advantage.
Reflecting mirror is one of most important structure of light emitting diode (LED) chip with vertical structure, forms the p-type Europe of low contact resistance high reflectance
Nurse contact is to obtain the necessary condition of the LED chip of low-voltage High Light Output power.At present mainly using Ag as reflecting mirror
Core material, because Ag is the highest metal of visible light wave range reflectivity.But Ag material also has apparent following a disadvantages:
(1) adhesion of the Ag on the surface GaN is poor, is easy to be easy to fall off in chip follow-up process, causes the electric leakage of chip
It is reduced with yield；(2) work function of Ag only has 4.65eV, and the work function of p-GaN is up to 7.5eV, exists between Ag and p-GaN
Biggish Schottky barrier, is handled even by high-temperature alloy, still suffers from higher contact resistance and exists, ultimately cause compared with
High forward voltage.
Summary of the invention
For overcome the deficiencies in the prior art, one of the objects of the present invention is to provide a kind of light emitting diode (LED) chip with vertical structure, with
It solves present in above-mentioned conventional vertical configuration LED chip Ag layers and is easy to happen to fall off, so that chip is caused to leak electricity and yield
The problems such as reduction, can also solve the problems, such as that Ag layers cannot form good Ohmic contact with p-GaN layer.
The second object of the present invention is to provide a kind of preparation method of light emitting diode (LED) chip with vertical structure, passes through the preparation method
The light emitting diode (LED) chip with vertical structure of preparation, which is able to solve above-mentioned Ag layers and is easy to happen, to fall off, so that causing chip electric leakage and yield drop
The problems such as low, can also solve the problems, such as that Ag layers cannot form good Ohmic contact with p-GaN layer.
An object of the present invention adopts the following technical scheme that realization:
A kind of light emitting diode (LED) chip with vertical structure, including substrate layer and the bonded layer being set on the substrate layer, the bonded layer
The X-dots/Ag/Y mirror layer for being equipped with the first protective layer and being set on first protective layer, the X-dots/Ag/Y
The InGaN/GaN quantum well layer that mirror layer is equipped with p-GaN layer and is set in the p-GaN layer, the InGaN/GaN amount
The n-electrode layer that sub- well layer is equipped with n-GaN layers and is set on the n-GaN layer；
The X be one of Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene,
The Y is one of Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl.
Further, in the X-dots/Ag/Y mirror layer, Ag with a thickness of 25~500nm, Y with a thickness of 10
~200nm.
Further, the X is Ni or Pd, and the Y is Ti or Ni.
Further, the substrate layer is Si substrate layer, and the bonded layer is Sn bonded layer, Au bonded layer or Sn/Au key
Layer is closed, first protective layer is Gr protective layer, Pt protective layer, Au protective layer, Gr/Pt protective layer, Gr/Au protective layer, Pt/Au
Protective layer or Gr/Pt/Au protective layer, the n-electrode layer be Ti electrode layer, Al electrode layer, Au electrode layer, Ti/Al electrode layer,
Al/Au electrode layer, Ti/Au electrode layer or Ti/Al/Au electrode layer, the p-GaN layer are p-type doping GaN film, the n-GaN
Layer is n-type doping GaN film.
The second object of the present invention adopts the following technical scheme that realization:
A kind of preparation method of light emitting diode (LED) chip with vertical structure characterized by comprising
A nano dot contact layer step) is grown:
Step 1: taking on substrate, successively growth has the LED extension of n-GaN layers, InGaN/GaN quantum well layer and p-GaN layer
Piece, in p-GaN layer growth regulation one contact layer X/Ag, the X with a thickness of 0.01~200nm, the Ag with a thickness of 25~
500nm, the X are one of Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene；
Step 2: the first contact layer X/Ag high annealing is obtained the first contact layer of alloying, the atmosphere of high annealing
For N2With O2Gaseous mixture, the temperature of high annealing are 300~800 DEG C, and the time of high annealing is 10~300s；
It impregnates, wash by water, drying step 3: the first contact of alloying is placed in corrosive liquid, nanometer point contact is made
Layer；
B mirror layer step) is grown:
Step 1: the growth regulation two-mirror layer Ag/Y on nano dot contact layer, the Ag with a thickness of 25~500nm,
The Y is one of Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl with a thickness of 10~200nm, the Y；
Step 2: the second mirror layer Ag/Y is carried out low-temperature annealing, X-dots/Ag/Y mirror layer is generated, low temperature moves back
The atmosphere of fire is N2With O2Gaseous mixture, the temperature of low-temperature annealing are 150~300 DEG C, and the low-temperature annealing time is 10~300s；
C) bonding and substrate transfer step: growing bonded layer on the mirror layer of LED epitaxial wafer, will by bonded layer
LED epitaxial wafer is transferred on conductive Si substrate, the LED epitaxial wafer after bonding is made；
D it) removes former substrate step: the LED epitaxial wafer after bonding being removed into former substrate by chemical attack, exposes n-GaN
Layer；
E it) prepares n-electrode step: depositing n-electrode on the n-GaN layer of exposing, light emitting diode (LED) chip with vertical structure is made.
Further, in the first step of growth nano dot contact layer, when X is Cr, Ni, Ti, Pt, Pd, In or Au, institute
State X with a thickness of 0.01~20nm；When X is one of NiO, TiO, ZnO, ITO, AZO, GIO or graphene, the X's
With a thickness of 1~200nm.
Further, in the second step of growth nano dot contact layer, the N2With O2The ratio between the amount of substance for 20:1~
1:20；In the second step of growth mirror layer, the N2With O2The ratio between the amount of substance be 20:1~1:20.
Further, in the third step for growing nano dot contact layer, the corrosive liquid is that acid etching solution or alkalinity are rotten
Lose liquid；
The acid etching solution is chloroazotic acid, and the alkaline corrosion liquid includes the mixed solution of ammonium hydroxide, hydrogen peroxide and water,
In, ammonium hydroxide: hydrogen peroxide: water (volume)=1~5:1:1.
Further, in bonding and substrate transfer step, preparatory growth regulation one is protected on the mirror layer of LED epitaxial wafer
Sheath, regrowth bonded layer；
First protective layer is Cr/Pt/Au coat of metal, and the bonded layer is Au/Sn metal bonding layer.
Further, in removing former substrate step, growth regulation two on the Si substrate of LED epitaxial wafer after bonding in advance
Then protective layer removes former substrate；
Second protective layer be Pt protective layer, the Pt protective layer with a thickness of 20~300nm；
The chemical attack is immersion corrosion solution, and the etchant solution is the mixed liquor of hydrofluoric acid and nitric acid, wherein hydrogen
The ratio between substance withdrawl syndrome of fluoric acid and nitric acid is 0.1:1~1:0.1.
Compared with prior art, the beneficial effects of the present invention are:
A kind of light emitting diode (LED) chip with vertical structure of the present invention is therefore ensured that by growing nano dot contact layer in p-GaN layer
X nano point is formed in p-GaN layer, and the Ag layer in mirror layer and Y layers of the growth on Ag layer are then grown on X nano point,
It is connect as a result, by Y layers with substrate for Ag layers, it is ensured that the good adhesion between mirror layer and conductive substrates prevents subsequent system
Reflecting layer is fallen off during standby；In addition, X nano point is arranged between p-GaN layer and Ag layers, X nano point thin layer is substantially reduced
The resistance of p-GaN layer and Ag layers of contact surface, ensure that good Ohmic contact between p-GaN layer and Ag layers；By means of X nano
The 2 D photon crystal quantum effect of point, the nano dot contact layer can also improve light emitting diode (LED) chip with vertical structure light extraction efficiency.
The preparation method of light emitting diode (LED) chip with vertical structure of the present invention prepares mirror layer using two-step method, is guaranteeing mirror layer
In Ag layer and p-GaN between while form good Ohmic contact, it is thus also avoided that the Ag layer in mirror layer occur cluster,
Oxidation and diffusion phenomena, can guarantee that the reflectivity in reflecting layer is not lowered；In addition, the system of light emitting diode (LED) chip with vertical structure of the present invention
Preparation Method is simple, and noble metal is also not used, is greatly saved cost while improving performance.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of light emitting diode (LED) chip with vertical structure of the present invention；
Fig. 2 is the structural schematic diagram of X-dots/Ag/Y mirror layer shown in Fig. 1；
Fig. 3 is the AFM shape appearance figure of the Ni-dots in the embodiment of the present invention 31；
Fig. 4 is the SEM shape appearance figure in embodiment 31 after the annealing of Ni-dots/Ag/Ti mirror layer；
Fig. 5 is SEM shape appearance figure after the annealing of the pure Ag mirror layer of tradition；
Fig. 6 is the SEM shape appearance figure after the annealing of tradition Ni/Ag mirror layer；
Fig. 7 is the reflectivity figure line of Ni-dots/Ag/Ti mirror layer prepared by embodiment 31；
Fig. 8 is the reflectivity figure line in conventional vertical configuration LED chip after the annealing of Ni/Ag mirror layer；
Fig. 9 is light emitting diode (LED) chip with vertical structure LOP-mapping figure prepared by embodiment 31；
Figure 10 is light emitting diode (LED) chip with vertical structure Vf2-mapping figure prepared by embodiment 31；
Figure 11 is conventional vertical knot LED chip LOP-mapping figure；
Figure 12 is conventional vertical knot LED chip Vf2-mapping figure；
Figure 13 is the AFM shape appearance figure of the Pd-dots in the embodiment of the present invention 33；
Figure 14 is the SEM shape appearance figure in embodiment 33 after the annealing of Pd-dots/Ag/Ni mirror layer；
Figure 15 is the reflectivity figure line of Pd-dots/Ag/Ni mirror layer prepared by embodiment 33；
Figure 16 is light emitting diode (LED) chip with vertical structure LOP-mapping figure prepared by embodiment 33；
Figure 17 is light emitting diode (LED) chip with vertical structure Vf2-mapping figure prepared by embodiment 33.
In figure: P1, substrate layer；P2, bonded layer；P3, protective layer；P4, X-dots/Ag/Y mirror layer；P41,X-dots
Nano dot contact layer；P42, Ag layers；P43, Y layers；P5, p-GaN layer；P6, InGaN/GaN quantum well layer；P7, n-GaN layers；P8,n
Electrode layer.
Specific embodiment
In the following, being described further in conjunction with attached drawing and specific embodiment to the present invention, it should be noted that not
Under the premise of conflicting, new implementation can be formed between various embodiments described below or between each technical characteristic in any combination
Example.
As shown in Figure 1, being the structural schematic diagram of light emitting diode (LED) chip with vertical structure of the present invention.The light emitting diode (LED) chip with vertical structure includes lining
The bottom P1 and bonded layer P2 being successively set to from bottom to up on substrate layer P1, protective layer P3X-dots/Ag/Y mirror layer P4,
P-GaN layer P5, InGaN/GaN quantum well layer P6, n-GaN layers of P7 and n-electrode layer P8.As shown in Fig. 2, for vertical junction shown in Fig. 1
The structural schematic diagram of X-dots/Ag/Y mirror layer P4 in structure LED chip, X-dots/Ag/Y mirror layer P4 includes X-
P41, Ag layers of P42 and Y layers of P43 of dots nano dot contact layer.The concrete type and its thickness and Y metal and its thickness of X-dots
Referring to table 1.
Table 1
As described in table 1, "/" is expressed as the metal or nano dot of multi ANN, such as X-dots/Ag/Y is expressed as in the past
The X-dots layer that grows layer by layer backward, Ag layers and Y layers (grow X-dots layer at first, then give birth on X-dots layer
It is Ag layers long, Y layers are finally grown on Ag layer), three layers of X-dots layer individually grown, Ag layers and Y layers close after annealing
Aurification becomes metal mirror layer P4.Metal mirror layer P4 is corresponding with a thickness of A/B/C, is expressed as X-dots layers of thickness
For A, Ag layers with a thickness of B, Y layers with a thickness of C.AgCu is expressed as Ag-Cu alloy, and AgMg is expressed as Ag-Mg alloy, AgAl table
It is shown as Ag-Al alloy.
As preferred embodiment, substrate layer P1 is Si substrate layer, and bonded layer P2 is Sn/Au bonded layer, protective layer P3
For Gr/Pt/Au protective layer, n-electrode layer P8 is Ti/Al/Au electrode layer, and p-GaN layer P5 is p-type doping GaN film, n-GaN layers
P7 is n-type doping GaN film.
Below by taking embodiment 31-34 as an example, the preparation method of the present invention will be described in detail light emitting diode (LED) chip with vertical structure.
Embodiment 31:
(1) LED epitaxial wafer is grown: epitaxial growth LED epitaxial wafer on a si substrate first, including growth n on a si substrate
Type adulterates GaN film (i.e. n-GaN layers of P7), InGaN/GaN Quantum Well (the i.e. InGaN/ being grown in n-type doping GaN film
GaN quantum well layer P6), the p-type doping GaN film (i.e. p-GaN layer P5) being grown in InGaN/GaN Quantum Well.
(2) it grows the first step (metal layer growth) of nano dot contact layer: using electron beam evaporation on LED epitaxial wafer surface
Equipment, be deposited the first contact layer W metal/Ag (layer of Ni is first deposited, then one layer of Ag is deposited), wherein Ni layers with a thickness of
3nm；Ag layers with a thickness of 100nm.
(3) nano dot contact layer second step (metal layer annealing) is grown: by the first contact layer W metal/Ag in short annealing
High annealing is carried out in furnace, makes its alloying, and the first contact layer of alloying is made；Wherein, annealing atmosphere is N2With O2Mixing
Gas, N2With O2The ratio between the amount of substance be N2: O2=3:1, annealing temperature are 500 DEG C, annealing time 40s.
(4) grow nano dot contact layer third step (wet etching generation nano dot): prepare acid etching solution chloroazotic acid (HCl:
HNO3=3:1), the first contact layer of alloying obtained in (3) is placed in the acid etching solution chloroazotic acid of preparation, is impregnated
It is taken out after 20s, bath drying, substantially confirms that the first contact layer W metal/Ag is removed completely substantially under microscope, prepare Ni and receive
Rice point contact layer (i.e. X-dots nano dot contact layer P41).
(5) the Ni nano dot contact layer of epitaxial wafer in step (4) is scanned in AFM (atomic force microscope), really
Recognize Ni nano dot, Ni nano dot is as shown in Figure 3.
(6) the mirror layer first step (metal layer growth) is grown: the Ni nanometer point contact of the epitaxial wafer after wet etching
Layer upper surface (is first deposited Ag layers and Ti layers is deposited again) using electron beam evaporation equipment growth regulation two-mirror layer Ag/Ti, wherein
Ag layers with a thickness of 100nm, Ti layers with a thickness of 60nm.
(7) mirror layer second step (metal layer annealing) is grown: by the second mirror layer Ag/Ti in step (6) into fast
Low-temperature annealing is carried out in fast annealing furnace, is made Ni-dots/Ag/Ti mirror layer (i.e. X-dots/Ag/Y mirror layer), annealing
Atmosphere is N2With O2Gaseous mixture, N2With O2The ratio between the amount of substance be N2: O2=6:1, annealing temperature are 200 DEG C, annealing time
For 25s.
(8) by Ag layer in the mirror layer after scanning electron microscope detection annealing, traditional pure Ag mirror layer and tradition Ni/Ag
The SEM shape appearance figure of mirror layer, detection method are identical.As shown in figure 4, for Ni-dots/Ag/Ti in step (7) in embodiment 31
SEM shape appearance figure after mirror layer annealing.Fig. 5 is the SEM shape appearance figure after the pure Ag mirror layer annealing of tradition.Fig. 6 is tradition Ni/
SEM shape appearance figure after the annealing of Ag mirror layer.It can be seen that pure Ag mirror layer shown in Fig. 5 has apparent Cluster Phenomenon, figure
Though Ni/Ag mirror layer shown in 6 is improved, Cluster Phenomenon is still obvious.Ni-dots/ manufactured in the present embodiment shown in Fig. 4
Ag/Ti reflecting mirror then essentially eliminates the phenomenon that Ag layers of cluster, and diffusion, cluster and the oxidation for avoiding traditional Ag radiation mirror layer are existing
As the thermal stability of Ag mirror layer greatly improved, be unlikely to cause the destruction to p-type doping GaN film.
(9) mirror layer and Ni/Ag in conventional vertical configuration LED chip in the present embodiment are measured by reflectance test instrument
The reflectivity of mirror layer, test method are consistent.Fig. 7 is the Ni-dots/Ag/Ti mirror layer of the present embodiment step (7) preparation
Reflectivity figure line, Fig. 8 be conventional vertical configuration LED chip in Ni/Ag mirror layer annealing after reflectivity figure line.Thus may be used
See, compared to the reflectivity of Ni/Ag mirror layer in conventional vertical configuration LED chip, Ni-dots/Ag/ manufactured in the present embodiment
The reflectivity of Ti mirror layer is substantially improved, and especially in blue wave band, the promotion of reflectivity is more obvious.
(10) electron beam bonding and substrate transfer: is passed through to the Ni-dots/Ag/Ti mirror layer surface of step (7) preparation
Cr/Pt/Au protective layer metal is deposited in evaporation equipment, and (i.e. first vapor deposition first layer protects metal Gr, then second layer protection metal is deposited
Pt is finally deposited third layer and protects metal Au), it is made protective layer P3 (i.e. the first protective layer).Equally, it is set by electron beam evaporation
The standby Au/Sn bond wire that is deposited on protective layer P3 (is first deposited first layer bond wire Au and first layer bond wire is deposited again
Sn), bonded layer P2 is made.Wherein Sn with a thickness of 2500nm, Au with a thickness of 60nm.The side being bonded using metallic high temperature high pressure
LED epitaxial wafer is transferred on conductive Si substrate layer P1 by formula, and temperature is 400 DEG C, bonding time 20min.Then, in key
Pt layers are deposited on Si substrate layer P1 after conjunction and is used as coat of metal (i.e. the second protective layer), with a thickness of 100nm.
(11) remove former substrate: removing original epitaxy Si substrate using chemical corrosion method, etchant solution be hydrofluoric acid with
The ratio between substance withdrawl syndrome of the mixed liquor of nitric acid, hydrofluoric acid and nitric acid is 10:1, thus exposes n-GaN layers of P7.
(12) it prepares n-electrode: SiO is deposited by PECVD (vapour deposition process of plasma enhanced chemical)2Passivation layer,
Using standard photolithography process such as spin coating, photoetching, developments, it is sequentially prepared LED chip n-electrode pattern, wherein spin coating uses negativity light
Photoresist, spin coating time 10s；The photoetching time is 20s, and developer solution uses negative photo glue developing solution, developing time 70s.Make
Deposited by electron beam evaporation equipment is sequentially depositing tri- layers of n-electrode gold of Ti/Al/Au on the surface for the n-GaN layer P7 that extension on piece exposes
Belong to and (first layer electrode metal Ti be first deposited, then second layer electrode metal Al is deposited, third layer electrode metal Au is finally deposited),
Wherein Ti is with a thickness of 40nm, and Al is with a thickness of 1800nm, and Au is with a thickness of 150nm.It is removed in such a way that blue film is pasted and is removed more
Remaining electrode metal, prepares light emitting diode (LED) chip with vertical structure.
(13) it chooses light emitting diode (LED) chip with vertical structure manufactured in the present embodiment and conventional vertical knot LED chip (is reflected comprising pure Ag
Mirror), using the photoelectric properties parameter of both point measurement machine tests.Fig. 9 is light emitting diode (LED) chip with vertical structure LOP- manufactured in the present embodiment
Mapping figure；Figure 10 is light emitting diode (LED) chip with vertical structure Vf2-mapping manufactured in the present embodiment figure；Figure 11 is conventional vertical knot
LED chip LOP-mapping figure；Figure 12 is conventional vertical knot LED chip Vf2-mapping figure.It follows that the present embodiment system
The LOP mean value of standby light emitting diode (LED) chip with vertical structure is 460mW, and Vf2 mean value is 2.87V；The LOP mean value of conventional vertical knot LED chip
For 315mW, Vf2 mean value is 3.1V.In contrast, the photoelectric properties that the present invention prepares light emitting diode (LED) chip with vertical structure have obtained huge
Big promotion, wherein LOP mean value improves 46.3%, and average voltage has dropped 7.4%.
Embodiment 32
The method that embodiment 32 prepares light emitting diode (LED) chip with vertical structure is generally identical as embodiment 31, and difference is:
(3) nano dot contact layer second step (metal layer annealing) is grown: N2With O2The ratio between the amount of substance be N2: O2=20:
1, annealing temperature is 300 DEG C, annealing time 300s.
(4) nano dot contact layer third step (wet etching generation nano dot) is grown: by the of alloying obtained in (3)
One contact layer is placed in the acid etching solution chloroazotic acid of preparation, is taken out after impregnating 3s.
(7) mirror layer second step (metal layer annealing) is grown: N2With O2The ratio between the amount of substance be N2: O2=1:20, is moved back
Fiery temperature is 300 DEG C, annealing time 10s.
(10) bonding and substrate transfer: Sn with a thickness of 3000nm, Au with a thickness of 10nm.Use metallic high temperature high pressure key
LED epitaxial wafer is transferred on conductive Si substrate layer P1 by the mode of conjunction, and temperature is 500 DEG C, and bonding time is 3 minutes.
(12) n-electrode: spin coating time 0.1s is prepared；The photoetching time is 50s, developing time 300s.Ti with a thickness of
10nm, Al are with a thickness of 500nm, and Au is with a thickness of 10nm.
(2), the hot evaporation equipment in (6) and (10) is substituted for magnetron sputtering apparatus.
Embodiment 33
(1) LED epitaxial wafer is grown: epitaxial growth LED epitaxial wafer on a si substrate first, including growth n on a si substrate
Type adulterates GaN film (i.e. n-GaN layers of P7), InGaN/GaN Quantum Well (the i.e. InGaN/ being grown in n-type doping GaN film
GaN quantum well layer P6), the p-type doping GaN film (i.e. p-GaN layer P5) being grown in InGaN/GaN Quantum Well.
(2) it grows the first step (metal layer growth) of nano dot contact layer: being set on LED epitaxial wafer surface using hot evaporation
It is standby, vapor deposition the first contact layer metal Pd/Ag (i.e. first be deposited one layer of Pd, then one layer of Ag is deposited), wherein Pd layers with a thickness of
1.5nm；Ag layers with a thickness of 150nm.
(3) nano dot contact layer second step (metal layer annealing) is grown: by the first contact layer metal Pd/Ag in short annealing
High annealing is carried out in furnace, makes its alloying, and the first contact layer of alloying is made；Wherein, annealing atmosphere is N2With O2Mixing
Gas, N2With O2The ratio between the amount of substance be N2: O2=3:1, annealing temperature are 400 DEG C, annealing time 60s.
(4) it grows nano dot contact layer third step (wet etching generation nano dot): it is (ammonium hydroxide, double to prepare alkaline corrosion liquid
The volume proportion of oxygen water and water is 3:1:1), the alkalinity that the first contact layer of alloying obtained in (3) is placed in preparation is rotten
It loses in liquid, is taken out after impregnating 8s, bath dries, substantially confirm that the first contact layer metal Pd/Ag is removed completely substantially under microscope,
Prepare Pd nano dot contact layer (i.e. X-dots nano dot contact layer P41).
(5) the Pd nano dot contact layer of epitaxial wafer in step (4) is scanned in AFM (atomic force microscope), really
Recognize Pd nano dot, Pd nano dot is as shown in figure 13.
(6) the mirror layer first step (metal layer growth) is grown: the Pd nanometer point contact of the epitaxial wafer after wet etching
Layer upper surface (is first deposited Ag layers and Ni layers is deposited again) using hot evaporation equipment growth regulation two-mirror layer Ag/Ni, wherein Ag layers
With a thickness of 100nm, Ni layers with a thickness of 30nm.
(7) mirror layer second step (metal layer annealing) is grown: by the second mirror layer Ag/Ni in step (6) into fast
Low-temperature annealing is carried out in fast annealing furnace, is made Pd-dots/Ag/Ni mirror layer (i.e. X-dots/Ag/Y mirror layer), annealing
Atmosphere is N2With O2Gaseous mixture, N2With O2The ratio between the amount of substance be N2: O2=4:1, annealing temperature are 180 DEG C, annealing time
For 60s.
(8) by Ag layer in the mirror layer after scanning electron microscope detection annealing, traditional pure Ag mirror layer and tradition Ni/Ag
The SEM shape appearance figure of mirror layer, detection method are identical.As shown in figure 14, be embodiment 33 the step of (7) in Pd-dots/Ag/
SEM shape appearance figure after the annealing of Ni mirror layer.It can be seen that compared to traditional pure Ag mirror layer and Ni/Ag mirror layer,
The phenomenon that Pd-dots/Ag/Ni reflecting mirror manufactured in the present embodiment then essentially eliminates Ag layers of cluster avoids traditional Ag radiation
Diffusion, cluster and the oxidative phenomena of mirror layer, greatly improved the thermal stability of Ag mirror layer, be unlikely to cause to p-type doping
The destruction of GaN film.
(9) mirror layer and Ni/Ag in conventional vertical configuration LED chip in the present embodiment are measured by reflectance test instrument
The reflectivity of mirror layer, test method are consistent with the above.Figure 15 is the Pd-dots/Ag/Ni of the present embodiment step (7) preparation
The reflectivity figure line of mirror layer.It can be seen that compared to the reflection of Ni/Ag mirror layer in conventional vertical configuration LED chip
The reflectivity of rate, Pd-dots/Ag/Ni mirror layer manufactured in the present embodiment is substantially improved, especially in blue wave band, instead
The promotion for penetrating rate is more obvious.
(10) hot evaporation bonding and substrate transfer: is passed through to the Pd-dots/Ag/Ni mirror layer surface of step (7) preparation
Cr/Pt/Au protective layer metal is deposited in equipment, and (i.e. first vapor deposition first layer protects metal Gr, then second layer protection Pt metal is deposited, most
Vapor deposition third layer protects metal Au afterwards), it is made protective layer P3 (i.e. the first protective layer).Equally, it is being protected by hot evaporation equipment
Au/Sn bond wire (i.e. first first layer bond wire Sn is deposited in vapor deposition first layer bond wire Au again) is deposited on layer P3, is made
Bonded layer P2.Wherein Sn with a thickness of 2500nm, Au with a thickness of 60nm.The mode being bonded using metallic high temperature high pressure is by LED
Epitaxial wafer is transferred on conductive Si substrate layer P1, and temperature is 400 DEG C, bonding time 20min.Then, after bonding
Pt is deposited on Si substrate layer P1 as coat of metal (i.e. the second protective layer), with a thickness of 100nm.
(11) remove former substrate: removing original epitaxy Si substrate using chemical corrosion method, etchant solution be hydrofluoric acid with
The ratio between substance withdrawl syndrome of the mixed liquor of nitric acid, hydrofluoric acid and nitric acid is 1:10, thus exposes n-GaN layers of P7.
(12) it prepares n-electrode: SiO is deposited by PECVD (vapour deposition process of plasma enhanced chemical)2Passivation layer,
Using standard photolithography process such as spin coating, photoetching, developments, it is sequentially prepared LED chip n-electrode pattern, wherein spin coating uses negativity light
Photoresist, spin coating time 10s；The photoetching time is 20s, and developer solution uses negative photo glue developing solution, developing time 70s.Make
Deposited by electron beam evaporation equipment is sequentially depositing tri- layers of n-electrode gold of Ti/Al/Au on the surface for the n-GaN layer P7 that extension on piece exposes
Belong to and (first layer electrode metal Ti be first deposited, then second layer electrode metal Al is deposited, third layer electrode metal Au is finally deposited),
Wherein Ti is with a thickness of 40nm, and Al is with a thickness of 1800nm, and Au is with a thickness of 150nm.It is removed in such a way that blue film is pasted and is removed more
Remaining electrode metal, prepares light emitting diode (LED) chip with vertical structure.
(13) light emitting diode (LED) chip with vertical structure manufactured in the present embodiment is chosen, the photoelectric properties using both point measurement machine tests are joined
Number test method and above-described embodiment 31 are consistent.Figure 16 is light emitting diode (LED) chip with vertical structure LOP-mapping manufactured in the present embodiment
Figure；Figure 17 is light emitting diode (LED) chip with vertical structure Vf2-mapping manufactured in the present embodiment figure.It follows that manufactured in the present embodiment hang down
The LOP mean value of straight structure LED chip is 455mW, and Vf2 mean value is 2.85V.In contrast, the present invention prepares vertical structure LED
The photoelectric properties of chip have obtained huge promotion, and wherein LOP mean value improves 44.1%, and average voltage has dropped 8.1%.
Embodiment 34
The method that embodiment 34 prepares light emitting diode (LED) chip with vertical structure is generally identical as embodiment 33, and difference is:
(3) nano dot contact layer second step (metal layer annealing) is grown: N2With O2The ratio between the amount of substance be N2: O2=1:
20, annealing temperature is 800 DEG C, annealing time 10s.
(4) nano dot contact layer third step (wet etching generation nano dot) is grown: by the of alloying obtained in (3)
One contact layer is placed in the acid etching solution chloroazotic acid of preparation, is taken out after impregnating 3s.
(7) mirror layer second step (metal layer annealing) is grown: N2With O2The ratio between the amount of substance be N2: O2=20:1, is moved back
Fiery temperature is 150 DEG C, annealing time 300s.
(10) bonding and substrate transfer: Sn with a thickness of 100nm, Au with a thickness of 200nm.Use metallic high temperature high pressure key
LED epitaxial wafer is transferred on conductive Si substrate layer P1 by the mode of conjunction, and temperature is 200 DEG C, and bonding time is 20 minutes.
(12) n-electrode: spin coating time 20s is prepared；The photoetching time is 1s, developing time 20s.Ti with a thickness of 100nm,
Al is with a thickness of 2000nm, and Au is with a thickness of 200nm.
(2), the hot evaporation equipment in (6) and (10) is substituted for magnetron sputtering apparatus.
The phenomenon that light emitting diode (LED) chip with vertical structure of embodiment 31-34 preparation essentially eliminates Ag layers of cluster, avoids tradition
Ag radiates diffusion, cluster and the oxidative phenomena of mirror layer, and reflecting layer emissivity is high；Meanwhile photoelectric properties have obtained huge mention
It rises,
The above embodiment is only the preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto,
The variation and replacement for any unsubstantiality that those skilled in the art is done on the basis of the present invention belong to institute of the present invention
Claimed range.
Claims (10)
1. a kind of light emitting diode (LED) chip with vertical structure, which is characterized in that including substrate layer and the bonded layer that is set on the substrate layer,
The X-dots/Ag/Y mirror layer that the bonded layer is equipped with the first protective layer and is set on first protective layer, it is described
The InGaN/GaN quantum well layer that X-dots/Ag/Y mirror layer is equipped with p-GaN layer and is set in the p-GaN layer, it is described
The n-electrode layer that InGaN/GaN quantum well layer is equipped with n-GaN layers and is set on the n-GaN layer；
The X is one of Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene, the Y
For one of Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl；
Light emitting diode (LED) chip with vertical structure is prepared in accordance with the following methods:
A nano dot contact layer step) is grown:
Step 1: taking on substrate, successively growth has the LED epitaxial wafer of n-GaN layers, InGaN/GaN quantum well layer and p-GaN layer,
In p-GaN layer growth regulation one contact layer X/Ag, the X with a thickness of 0.01~200nm, the Ag with a thickness of 25~500nm,
The X is one of Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene；
Step 2: the first contact layer X/Ag high annealing is obtained the first contact layer of alloying, the atmosphere of high annealing is N2
With O2Gaseous mixture, the temperature of high annealing are 300~800 DEG C, and the time of high annealing is 10~300s；
It impregnates, wash by water, drying step 3: the first contact of alloying is placed in corrosive liquid, nano dot contact layer is made；
B mirror layer step) is grown:
Step 1: the growth regulation two-mirror layer Ag/Y on nano dot contact layer, the Ag with a thickness of 25~500nm, the Y
With a thickness of 10~200nm, the Y is one of Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl；
Step 2: the second mirror layer Ag/Y is carried out low-temperature annealing, X-dots/Ag/Y mirror layer is generated, low-temperature annealing
Atmosphere is N2With O2Gaseous mixture, the temperature of low-temperature annealing are 150~300 DEG C, and the low-temperature annealing time is 10~300s；
C) bonding and substrate transfer step: growing bonded layer on the mirror layer of LED epitaxial wafer, will be outside LED by bonded layer
Prolong piece to be transferred on conductive Si substrate, the LED epitaxial wafer after bonding is made；
D it) removes former substrate step: the LED epitaxial wafer after bonding being removed into former substrate by chemical attack, exposes n-GaN layers；
E it) prepares n-electrode step: depositing n-electrode on the n-GaN layer of exposing, light emitting diode (LED) chip with vertical structure is made.
2. light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that in the X-dots/Ag/Y mirror layer
In, Ag with a thickness of 25~500nm, Y with a thickness of 10~200nm.
3. light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that the X be Ni or Pd, the Y be Ti or
Ni。
4. light emitting diode (LED) chip with vertical structure as described in any one of claims 1-3, which is characterized in that the substrate layer is Si substrate
Layer, the bonded layer are Sn bonded layer, Au bonded layer or Sn/Au bonded layer, and first protective layer is Gr protective layer, Pt guarantor
Sheath, Au protective layer, Gr/Pt protective layer, Gr/Au protective layer, Pt/Au protective layer or Gr/Pt/Au protective layer, the n-electrode layer
For Ti electrode layer, Al electrode layer, Au electrode layer, Ti/Al electrode layer, Al/Au electrode layer, Ti/Au electrode layer or Ti/Al/Au electricity
Pole layer, the p-GaN layer are p-type doping GaN film, and described n-GaN layers is n-type doping GaN film.
5. a kind of preparation method of light emitting diode (LED) chip with vertical structure characterized by comprising
A nano dot contact layer step) is grown:
Step 1: taking on substrate, successively growth has the LED epitaxial wafer of n-GaN layers, InGaN/GaN quantum well layer and p-GaN layer,
In p-GaN layer growth regulation one contact layer X/Ag, the X with a thickness of 0.01~200nm, the Ag with a thickness of 25~500nm,
The X is one of Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene；
Step 2: the first contact layer X/Ag high annealing is obtained the first contact layer of alloying, the atmosphere of high annealing is N2
With O2Gaseous mixture, the temperature of high annealing are 300~800 DEG C, and the time of high annealing is 10~300s；
It impregnates, wash by water, drying step 3: the first contact of alloying is placed in corrosive liquid, nano dot contact layer is made；
B mirror layer step) is grown:
Step 1: the growth regulation two-mirror layer Ag/Y on nano dot contact layer, the Ag with a thickness of 25~500nm, the Y
With a thickness of 10~200nm, the Y is one of Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl；
Step 2: the second mirror layer Ag/Y is carried out low-temperature annealing, X-dots/Ag/Y mirror layer is generated, low-temperature annealing
Atmosphere is N2With O2Gaseous mixture, the temperature of low-temperature annealing are 150~300 DEG C, and the low-temperature annealing time is 10~300s；
C) bonding and substrate transfer step: growing bonded layer on the mirror layer of LED epitaxial wafer, will be outside LED by bonded layer
Prolong piece to be transferred on conductive Si substrate, the LED epitaxial wafer after bonding is made；
D it) removes former substrate step: the LED epitaxial wafer after bonding being removed into former substrate by chemical attack, exposes n-GaN layers；
E it) prepares n-electrode step: depositing n-electrode on the n-GaN layer of exposing, light emitting diode (LED) chip with vertical structure is made.
6. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that in growth nanometer point contact
Layer the first step in, when X be Cr, Ni, Ti, Pt, Pd, In or Au when, the X with a thickness of 0.01~20nm；When X be NiO,
When one of TiO, ZnO, ITO, AZO, GIO and graphene, the X with a thickness of 1~200nm.
7. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that in growth nanometer point contact
In the second step of layer, the N2With O2The ratio between the amount of substance be 20:1~1:20；In the second step of growth mirror layer, institute
State N2With O2The ratio between the amount of substance be 20:1~1:20.
8. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that growth nano dot contact layer
Third step in, the corrosive liquid be acid etching solution or alkaline corrosion liquid；
The acid etching solution is chloroazotic acid, and the alkaline corrosion liquid includes the mixed solution of ammonium hydroxide, hydrogen peroxide and water, wherein ammonia
Water: hydrogen peroxide: water (volume)=1~5:1:1.
9. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that shifted in bonding and substrate
In step, one protective layer of preparatory growth regulation, regrowth bonded layer on the mirror layer of LED epitaxial wafer；
First protective layer is Cr/Pt/Au coat of metal, and the bonded layer is Au/Sn metal bonding layer.
10. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that removing former substrate step
In, two protective layer of growth regulation on the Si substrate of LED epitaxial wafer after bonding, then removes former substrate in advance；
Second protective layer be Pt protective layer, the Pt protective layer with a thickness of 20~300nm；
The chemical attack is immersion corrosion solution, and the etchant solution is the mixed liquor of hydrofluoric acid and nitric acid, wherein hydrofluoric acid
It is 0.1:1~1:0.1 with the ratio between the substance withdrawl syndrome of nitric acid.
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Denomination of invention: A vertical structure LED chip and its preparation method Effective date of registration: 20220520 Granted publication date: 20191018 Pledgee: Bank of China Limited by Share Ltd. Heyuan branch Pledgor: HEYUAN CHOICORE PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Registration number: Y2022980006017 |