CN108305921A - A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof - Google Patents
A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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Abstract
The invention discloses a kind of light emitting diode (LED) chip with vertical structure; including substrate layer and the bonded layer being set on substrate layer; the X dots/Ag/Y mirror layers that bonded layer is equipped with the first protective layer and is set on first protective layer; the InGaN/GaN quantum well layers that X dots/Ag/Y mirror layers are equipped with p GaN layers and are set in p GaN layers, the n-electrode layer that InGaN/GaN quantum well layers are equipped with n GaN layers and are set in n GaN layers.The invention also discloses a kind of preparation methods of light emitting diode (LED) chip with vertical structure.Good adhesion between light emitting diode (LED) chip with vertical structure mirror layer of the present invention and conductive substrates, prevents reflecting layer in subsequent preparation process from falling off, and also ensures good Ohmic contact between p GaN layers and Ag layers.
Description
Technical field
The present invention relates to LED technology field, more particularly to a kind of light emitting diode (LED) chip with vertical structure and the light emitting diode (LED) chip with vertical structure
Preparation method.
Background technology
As LED is in the gradually application of lighting area, the requirement that white light LED light is imitated in market is higher and higher.GaN base is vertical
Structure LED has single side light extraction, good heat-sinking capability, can bear Bulk current injection, and such a vertical structure LED
Chip can be equivalent to several formal dress fabric chips, and equivalent cost only has the part of positive assembling structure, at low cost, performance is excellent.
Therefore, GaN base light emitting diode (LED) chip with vertical structure be market institute to and semiconductor lighting develop inexorable trend.With traditional plane
Structure LED is compared, and vertical structure LED has many advantages：(1) two electrodes of vertical structure LED are respectively in the both sides of LED, electricity
Stream almost all flows vertically through epitaxial layer, not the electric current of lateral flow, homogeneous current distribution, and the heat of generation is reduced；(2) it adopts
The bad Sapphire Substrate of heat conduction is removed with the method for bonding and stripping, changes good conductivity and the lining with high heat conductance into
Bottom can effectively radiate；(3) n-GaN layers are light-emitting surface, this layer has certain thickness, convenient for making surface micro-structure, to carry
Highlight extract efficiency.In short, compared with conventional planar structure, vertical structure has apparent advantage in light extraction, heat dissipation etc..
Speculum is one of most important structure of light emitting diode (LED) chip with vertical structure, forms the p-type Europe of low contact resistance high reflectance
Nurse contact is the necessary condition for the LED chip for obtaining low-voltage High Light Output power.At present mainly using Ag as speculum
Core material, because Ag is the highest metal of visible light wave range reflectivity.But Ag materials also have apparent following a disadvantages：
(1) adhesions of the Ag on the surfaces GaN is poor, is easy to be easy to fall off in chip follow-up process, causes the electric leakage of chip
It is reduced with yield；(2) work function of Ag only has 4.65eV, and the work function of p-GaN is up to 7.5eV, exists between Ag and p-GaN
Larger Schottky barrier, is handled even by high-temperature alloy, still suffers from higher contact resistance and exists, ultimately cause compared with
High forward voltage.
Invention content
For overcome the deficiencies in the prior art, one of the objects of the present invention is to provide a kind of light emitting diode (LED) chip with vertical structure, with
It solves present in above-mentioned conventional vertical configuration LED chip Ag layers and is easy to happen to fall off, so that chip is caused to leak electricity and yield
The problems such as reduction, can also solve the problems, such as that Ag layers cannot form good Ohmic contact with p-GaN layer.
The second object of the present invention is to provide a kind of preparation method of light emitting diode (LED) chip with vertical structure, passes through the preparation method
The light emitting diode (LED) chip with vertical structure of preparation can solve above-mentioned Ag layers and be easy to happen to fall off, so that causing chip electric leakage and yield drop
The problems such as low, can also solve the problems, such as that Ag layers cannot form good Ohmic contact with p-GaN layer.
An object of the present invention adopts the following technical scheme that realization：
A kind of light emitting diode (LED) chip with vertical structure, including substrate layer and the bonded layer being set on the substrate layer, the bonded layer
The X-dots/Ag/Y mirror layers for being equipped with the first protective layer and being set on first protective layer, the X-dots/Ag/Y
The InGaN/GaN quantum well layers that mirror layer is equipped with p-GaN layer and is set in the p-GaN layer, the InGaN/GaN amounts
The n-electrode layer that sub- well layer is equipped with n-GaN layers and is set on the n-GaN layers；
The X is one kind in Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene,
The Y is one kind in Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl.
Further, in the X-dots/Ag/Y mirror layers, the thickness of Ag is 25~500nm, and the thickness of Y is 10
~200nm.
Further, the X is Ni or Pd, and the Y is Ti or Ni.
Further, the substrate layer is Si substrate layers, and the bonded layer is Sn bonded layers, Au bonded layers or Sn/Au keys
Layer is closed, first protective layer is Gr protective layers, Pt protective layers, Au protective layers, Gr/Pt protective layers, Gr/Au protective layers, Pt/Au
Protective layer or Gr/Pt/Au protective layers, the n-electrode layer be Ti electrode layers, Al electrode layers, Au electrode layers, Ti/Al electrode layers,
Al/Au electrode layers, Ti/Au electrode layers or Ti/Al/Au electrode layers, the p-GaN layer are that p-type adulterates GaN film, the n-GaN
Layer is that N-shaped adulterates GaN film.
The second object of the present invention adopts the following technical scheme that realization：
A kind of preparation method of light emitting diode (LED) chip with vertical structure, which is characterized in that including：
A nano dot contact layer step) is grown：
The first step：Growth successively is taken on substrate to have n-GaN layers, the LED extensions of InGaN/GaN quantum well layers and p-GaN layer
Piece, the thickness of growth regulation one contact layer X/Ag, the X are 0.01~200nm in p-GaN layer, the thickness of the Ag is 25~
500nm, the X are one kind in Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene；
Second step：By the first contact layer X/Ag high annealings, the first contact layer of alloying, the atmosphere of high annealing are obtained
For N2With O2The temperature of gaseous mixture, high annealing is 300~800 DEG C, and the time of high annealing is 10~300s；
Third walks：First contact of alloying is placed in corrosive liquid and impregnates, wash by water, drying, nanometer point contact is made
Layer；
B mirror layer step) is grown：
The first step：The thickness of the growth regulation two-mirror layer Ag/Y on nano dot contact layer, the Ag are 25~500nm,
The thickness of the Y is 10~200nm, and the Y is one kind in Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl；
Second step：Second mirror layer Ag/Y is subjected to process annealing, generates X-dots/Ag/Y mirror layers, low temperature moves back
The atmosphere of fire is N2With O2The temperature of gaseous mixture, process annealing is 150~300 DEG C, and the process annealing time is 10~300s；
C) bonding and substrate transfer step：Bonded layer is grown on the mirror layer of LED epitaxial wafer, it will by bonded layer
LED epitaxial wafer is transferred on conductive Si substrates, and the LED epitaxial wafer after bonding is made；
D former substrate step) is removed：LED epitaxial wafer after bonding is removed into former substrate by chemical attack, exposes n-GaN
Layer；
E n-electrode step) is prepared：N-electrode is deposited on the n-GaN layers of exposing, light emitting diode (LED) chip with vertical structure is made.
Further, in the first step of growth nano dot contact layer, when X is Cr, Ni, Ti, Pt, Pd, In or Au, institute
The thickness for stating X is 0.01~20nm；When X is a kind of in NiO, TiO, ZnO, ITO, AZO, GIO or graphene, the X's
Thickness is 1~200nm.
Further, in the second step of growth nano dot contact layer, the N2With O2The ratio between the amount of substance be 20：1~
1：20；In the second step of growth mirror layer, the N2With O2The ratio between the amount of substance be 20：1~1：20.
Further, in the third step of growth nano dot contact layer, the corrosive liquid is that acid etching solution or alkalinity are rotten
Lose liquid；
The acid etching solution is chloroazotic acid, and the alkaline corrosion liquid includes the mixed solution of ammonium hydroxide, hydrogen peroxide and water,
In, ammonium hydroxide：Hydrogen peroxide：Water (volume)=1~5：1：1.
Further, in bonding and substrate transfer step, advance growth regulation one is protected on the mirror layer of LED epitaxial wafer
Sheath, regrowth bonded layer；
First protective layer is Cr/Pt/Au coat of metal, and the bonded layer is Au/Sn metal bonding layers.
Further, in the former substrate step of stripping, Si Growns second of LED epitaxial wafer after bonding in advance
Then protective layer removes former substrate；
Second protective layer is Pt protective layers, and the thickness of the Pt protective layers is 20~300nm；
The chemical attack is immersion corrosion solution, and the etchant solution is the mixed liquor of hydrofluoric acid and nitric acid, wherein hydrogen
The ratio between substance withdrawl syndrome of fluoric acid and nitric acid is 0.1:1~1:0.1.
Compared with prior art, the beneficial effects of the present invention are：
A kind of light emitting diode (LED) chip with vertical structure of the present invention is therefore ensured that by growing nano dot contact layer in p-GaN layer
X nano point is formed in p-GaN layer, and the Ag layers in mirror layer and Y layers of the growth on Ag layers are then grown on X nano point,
It is connect as a result, with substrate by Y layers for Ag layers, it is ensured that the good adhesion between mirror layer and conductive substrates prevents from subsequently making
Reflecting layer is fallen off during standby；In addition, X nano point is arranged between p-GaN layer and Ag layers, X nano point thin layer substantially reduces
The resistance of p-GaN layer and Ag layers of contact surface, ensure that good Ohmic contact between p-GaN layer and Ag layers；By means of X nano
The 2 D photon crystal quantum effect of point, the nano dot contact layer can also improve light emitting diode (LED) chip with vertical structure light extraction efficiency.
The preparation method of light emitting diode (LED) chip with vertical structure of the present invention prepares mirror layer using two-step method, is ensureing mirror layer
In Ag layers and p-GaN between while form good Ohmic contact, it is thus also avoided that the Ag layers in mirror layer occur cluster,
Oxidation and diffusion phenomena, can ensure that the reflectivity in reflecting layer is not lowered；In addition, the system of light emitting diode (LED) chip with vertical structure of the present invention
Preparation Method is simple, and noble metal is also not used, cost is greatly saved while improving performance.
Description of the drawings
Fig. 1 is the structural schematic diagram of light emitting diode (LED) chip with vertical structure of the present invention；
Fig. 2 is the structural schematic diagram of X-dots/Ag/Y mirror layers shown in Fig. 1；
Fig. 3 is the AFM shape appearance figures of the Ni-dots in the embodiment of the present invention 31；
Fig. 4 is the SEM shape appearance figures after the annealing of Ni-dots/Ag/Ti mirror layers in embodiment 31；
Fig. 5 is SEM shape appearance figures after the annealing of the pure Ag mirror layers of tradition；
Fig. 6 is the SEM shape appearance figures after the annealing of tradition Ni/Ag mirror layers；
Fig. 7 is the reflectivity figure line of Ni-dots/Ag/Ti mirror layers prepared by embodiment 31；
Fig. 8 is the reflectivity figure line after the annealing of Ni/Ag mirror layers in conventional vertical configuration LED chip；
Fig. 9 is light emitting diode (LED) chip with vertical structure LOP-mapping figures prepared by embodiment 31；
Figure 10 is light emitting diode (LED) chip with vertical structure Vf2-mapping figures prepared by embodiment 31；
Figure 11 is conventional vertical knot LED chip LOP-mapping figures；
Figure 12 is conventional vertical knot LED chip Vf2-mapping figures；
Figure 13 is the AFM shape appearance figures of the Pd-dots in the embodiment of the present invention 33；
Figure 14 is the SEM shape appearance figures after the annealing of Pd-dots/Ag/Ni mirror layers in embodiment 33；
Figure 15 is the reflectivity figure line of Pd-dots/Ag/Ni mirror layers prepared by embodiment 33；
Figure 16 is light emitting diode (LED) chip with vertical structure LOP-mapping figures prepared by embodiment 33；
Figure 17 is light emitting diode (LED) chip with vertical structure Vf2-mapping figures prepared by embodiment 33.
In figure：P1, substrate layer；P2, bonded layer；P3, protective layer；P4, X-dots/Ag/Y mirror layer；P41、X-dots
Nano dot contact layer；P42, Ag layers；P43, Y layers；P5, p-GaN layer；P6, InGaN/GaN quantum well layer；P7, n-GaN layers；P8、n
Electrode layer.
Specific implementation mode
In the following, in conjunction with attached drawing and specific implementation mode, the present invention is described further, it should be noted that not
Under the premise of conflicting, new implementation can be formed between various embodiments described below or between each technical characteristic in any combination
Example.
As shown in Figure 1, for the structural schematic diagram of light emitting diode (LED) chip with vertical structure of the present invention.The light emitting diode (LED) chip with vertical structure includes lining
The bottom P1 and bonded layer P2 being set to from bottom to up successively on substrate layer P1, protective layer P3X-dots/Ag/Y mirror layers P4,
P-GaN layer P5, InGaN/GaN quantum well layer P6, n-GaN layers of P7 and n-electrode layer P8.As shown in Fig. 2, for vertical junction shown in Fig. 1
The structural schematic diagram of X-dots/Ag/Y mirror layers P4 in structure LED chip, X-dots/Ag/Y mirror layers P4 includes X-
P41, Ag layers of P42 and Y layers of P43 of dots nano dot contact layers.The concrete type and its thickness and Y metals and its thickness of X-dots
Referring to table 1.
Table 1
As described in table 1, "/" is expressed as the metal or nano dot of multi ANN, such as X-dots/Ag/Y is expressed as in the past
The X-dots layers that grow layer by layer backward, Ag layers and Y layers (grow X-dots layer, are then given birth on X-dots layers at first
It is Ag layers long, finally on Ag layers grow Y layers), three layers of X-dots layers individually grown, Ag layers and Y layers closed after annealing
Aurification becomes metal mirror layer P4.The corresponding thickness of metal mirror layer P4 is A/B/C, is expressed as X-dots layers of thickness
For A, Ag layers of thickness is B, and Y layers of thickness is C.AgCu is expressed as Ag-Cu alloys, and AgMg is expressed as Ag-Mg alloys, AgAl tables
It is shown as Ag-Al alloys.
As preferred embodiment, substrate layer P1 is Si substrate layers, and bonded layer P2 is Sn/Au bonded layers, protective layer P3
For Gr/Pt/Au protective layers, n-electrode layer P8 is Ti/Al/Au electrode layers, and p-GaN layer P5 is that p-type adulterates GaN film, n-GaN layers
P7 is that N-shaped adulterates GaN film.
Below by taking embodiment 31-34 as an example, the preparation method of the present invention will be described in detail light emitting diode (LED) chip with vertical structure.
Embodiment 31：
(1) LED epitaxial wafer is grown：Epitaxial growth LED epitaxial wafer on a si substrate first, including growth n on a si substrate
Type adulterates GaN film (i.e. n-GaN layers of P7), InGaN/GaN Quantum Well (the i.e. InGaN/ being grown in N-shaped doping GaN film
GaN quantum well layer P6), the p-type doping GaN film (i.e. p-GaN layer P5) being grown in InGaN/GaN Quantum Well.
(2) first step (metal layer growth) of nano dot contact layer is grown：Electron beam evaporation is used on LED epitaxial wafer surface
Equipment, vapor deposition the first contact layer W metal/Ag (layer of Ni is first deposited, then one layer of Ag is deposited), wherein Ni layers of thickness is
3nm；Ag layers of thickness is 100nm.
(3) growth nano dot contact layer second step (metal layer annealing)：By the first contact layer W metal/Ag in short annealing
High annealing is carried out in stove, makes its alloying, and the first contact layer of alloying is made；Wherein, annealing atmosphere is N2With O2Mixing
Gas, N2With O2The ratio between the amount of substance be N2：O2=3：1, annealing temperature is 500 DEG C, annealing time 40s.
(4) growth nano dot contact layer third step (wet etching generation nano dot)：Prepare acid etching solution chloroazotic acid (HCl：
HNO3=3：1), the first contact layer of alloying obtained in (3) is positioned in the acid etching solution chloroazotic acid of preparation, is impregnated
It is taken out after 20s, bath drying, substantially confirms that the first contact layer W metal/Ag is removed totally substantially under microscope, prepare Ni and receive
Rice point contact layer (i.e. X-dots nano dots contact layer P41).
(5) the Ni nano dots contact layer of epitaxial wafer in step (4) is scanned in AFM (atomic force microscope), really
Recognize Ni nano dots, Ni nano dots are as shown in Figure 3.
(6) the growth mirror layer first step (metal layer growth)：The Ni nanometer point contacts of epitaxial wafer after wet etching
Layer upper surface (is first deposited Ag layers and Ti layers is deposited again) using electron beam evaporation equipment growth regulation two-mirror layer Ag/Ti, wherein
Ag layers of thickness is 100nm, and Ti layers of thickness is 60nm.
(7) growth mirror layer second step (metal layer annealing)：By the second mirror layer Ag/Ti in step (6) into fast
Process annealing is carried out in fast annealing stove, and Ni-dots/Ag/Ti mirror layers (i.e. X-dots/Ag/Y mirror layers), annealing is made
Atmosphere is N2With O2Gaseous mixture, N2With O2The ratio between the amount of substance be N2：O2=6：1, annealing temperature is 200 DEG C, annealing time
For 25s.
(8) by Ag layer in the mirror layer after scanning electron microscope detection annealing, traditional pure Ag mirror layers and tradition Ni/Ag
The SEM shape appearance figures of mirror layer, detection method are identical.As shown in figure 4, for Ni-dots/Ag/Ti in step (7) in embodiment 31
SEM shape appearance figures after mirror layer annealing.Fig. 5 is the SEM shape appearance figures after the pure Ag mirror layers annealing of tradition.Fig. 6 is tradition Ni/
SEM shape appearance figures after the annealing of Ag mirror layers.It can be seen that pure Ag mirror layers shown in Fig. 5 have apparent Cluster Phenomenon, figure
Though Ni/Ag mirror layers shown in 6 is improved, Cluster Phenomenon is still apparent.Ni-dots/ manufactured in the present embodiment shown in Fig. 4
Ag/Ti speculums then essentially eliminate the phenomenon that Ag layers of cluster, and diffusion, cluster and the oxidation for avoiding traditional Ag radiation mirror layer are existing
As the thermal stability of Ag mirror layers greatly improved, be unlikely to the destruction for causing to adulterate p-type GaN film.
(9) mirror layer and Ni/Ag in conventional vertical configuration LED chip in the present embodiment are measured by reflectance test instrument
The reflectivity of mirror layer, test method are consistent.Fig. 7 is Ni-dots/Ag/Ti mirror layers prepared by the present embodiment step (7)
Reflectivity figure line, Fig. 8 be conventional vertical configuration LED chip in Ni/Ag mirror layers annealing after reflectivity figure line.Thus may be used
See, compared to the reflectivity of Ni/Ag mirror layers in conventional vertical configuration LED chip, Ni-dots/Ag/ manufactured in the present embodiment
The reflectivity of Ti mirror layers is substantially improved, and especially in blue wave band, the promotion of reflectivity is more obvious.
(10) bonding and substrate transfer：The Ni-dots/Ag/Ti mirror layers surface prepared to step (7) passes through electron beam
Cr/Pt/Au protective layers metal is deposited in evaporation equipment, and (i.e. first vapor deposition first layer protects metal Gr, then second layer protection metal is deposited
Pt is finally deposited third layer and protects metal Au), protective layer P3 (i.e. the first protective layer) is made.Equally, it is set by electron beam evaporation
The standby Au/Sn bond wires that are deposited on protective layer P3 (are first deposited first layer bond wire Au and first layer bond wire are deposited again
Sn), bonded layer P2 is made.Wherein the thickness of Sn is 2500nm, and the thickness of Au is 60nm.The side being bonded using metallic high temperature high pressure
LED epitaxial wafer is transferred on conductive Si substrate layers P1 by formula, and temperature is 400 DEG C, bonding time 20min.Then, in key
Pt layers are deposited on Si substrate layers P1 after conjunction and is used as coat of metal (i.e. the second protective layer), thickness 100nm.
(11) former substrate is removed：Remove original epitaxy Si substrate using chemical corrosion method, etchant solution be hydrofluoric acid with
The ratio between substance withdrawl syndrome of the mixed liquor of nitric acid, hydrofluoric acid and nitric acid is 10:1, thus expose n-GaN layers of P7.
(12) n-electrode is prepared：SiO is deposited by PECVD (vapour deposition process of plasma enhanced chemical)2Passivation layer,
Using standard photolithography process such as spin coating, photoetching, developments, it is sequentially prepared LED chip n-electrode pattern, wherein spin coating uses negativity light
Photoresist, spin coating time 10s；The photoetching time is 20s, and developer solution uses negative photo glue developing solution, developing time 70s.Make
Deposited by electron beam evaporation equipment is sequentially depositing tri- layers of n-electrode gold of Ti/Al/Au on the surface for the n-GaN layers P7 that extension on piece exposes
Belong to and (first layer electrode metal Ti be first deposited, then second layer electrode metal Al is deposited, third layer electrode metal Au is finally deposited),
Wherein Ti thickness is 40nm, and Al thickness is 1800nm, and Au thickness is 150nm.It is removed in such a way that blue film is pasted and is removed more
Remaining electrode metal, prepares light emitting diode (LED) chip with vertical structure.
(13) it chooses light emitting diode (LED) chip with vertical structure manufactured in the present embodiment and conventional vertical knot LED chip (is reflected comprising pure Ag
Mirror), using the photoelectric properties parameter of both point measurement machine tests.Fig. 9 is light emitting diode (LED) chip with vertical structure LOP- manufactured in the present embodiment
Mapping schemes；Figure 10 schemes for light emitting diode (LED) chip with vertical structure Vf2-mapping manufactured in the present embodiment；Figure 11 is conventional vertical knot
LED chip LOP-mapping figures；Figure 12 is conventional vertical knot LED chip Vf2-mapping figures.It follows that the present embodiment system
The LOP mean values of standby light emitting diode (LED) chip with vertical structure are 460mW, and Vf2 mean values are 2.87V；The LOP mean values of conventional vertical knot LED chip
For 315mW, Vf2 mean values are 3.1V.In contrast, the present invention prepare light emitting diode (LED) chip with vertical structure photoelectric properties obtained it is huge
Big promotion, wherein LOP mean values improve 46.3%, and average voltage has dropped 7.4%.
Embodiment 32
The method that embodiment 32 prepares light emitting diode (LED) chip with vertical structure is generally identical as embodiment 31, and difference is：
(3) growth nano dot contact layer second step (metal layer annealing)：N2With O2The ratio between the amount of substance be N2：O2=20：
1, annealing temperature is 300 DEG C, annealing time 300s.
(4) growth nano dot contact layer third step (wet etching generation nano dot)：By of alloying obtained in (3)
One contact layer is positioned in the acid etching solution chloroazotic acid of preparation, is taken out after impregnating 3s.
(7) growth mirror layer second step (metal layer annealing)：N2With O2The ratio between the amount of substance be N2：O2=1：20, it moves back
Fiery temperature is 300 DEG C, annealing time 10s.
(10) bonding and substrate transfer：The thickness of Sn is 3000nm, and the thickness of Au is 10nm.Use metallic high temperature high pressure key
LED epitaxial wafer is transferred on conductive Si substrate layers P1 by the mode of conjunction, and temperature is 500 DEG C, and bonding time is 3 minutes.
(12) n-electrode is prepared：Spin coating time is 0.1s；The photoetching time is 50s, developing time 300s.Ti thickness is
10nm, Al thickness are 500nm, and Au thickness is 10nm.
(2), the hot evaporation equipment in (6) and (10) is substituted for magnetron sputtering apparatus.
Embodiment 33
(1) LED epitaxial wafer is grown：Epitaxial growth LED epitaxial wafer on a si substrate first, including growth n on a si substrate
Type adulterates GaN film (i.e. n-GaN layers of P7), InGaN/GaN Quantum Well (the i.e. InGaN/ being grown in N-shaped doping GaN film
GaN quantum well layer P6), the p-type doping GaN film (i.e. p-GaN layer P5) being grown in InGaN/GaN Quantum Well.
(2) first step (metal layer growth) of nano dot contact layer is grown：It is set using hot evaporation on LED epitaxial wafer surface
It is standby, vapor deposition the first contact layer metal Pd/Ag (i.e. first one layer of Pd of vapor deposition, then one layer of Ag is deposited), wherein Pd layers of thickness is
1.5nm；Ag layers of thickness is 150nm.
(3) growth nano dot contact layer second step (metal layer annealing)：By the first contact layer metal Pd/Ag in short annealing
High annealing is carried out in stove, makes its alloying, and the first contact layer of alloying is made；Wherein, annealing atmosphere is N2With O2Mixing
Gas, N2With O2The ratio between the amount of substance be N2：O2=3：1, annealing temperature is 400 DEG C, annealing time 60s.
(4) growth nano dot contact layer third step (wet etching generation nano dot)：It is (ammonium hydroxide, double to prepare alkaline corrosion liquid
The volume proportion of oxygen water and water is 3：1：1) alkalinity that the first contact layer of alloying obtained in (3), is positioned over to preparation is rotten
It loses in liquid, is taken out after impregnating 8s, bath dries, and substantially confirms that the first contact layer metal Pd/Ag is removed totally substantially under microscope,
Prepare Pd nano dots contact layer (i.e. X-dots nano dots contact layer P41).
(5) the Pd nano dots contact layer of epitaxial wafer in step (4) is scanned in AFM (atomic force microscope), really
Recognize Pd nano dots, Pd nano dots are as shown in figure 13.
(6) the growth mirror layer first step (metal layer growth)：The Pd nanometer point contacts of epitaxial wafer after wet etching
Layer upper surface (is first deposited Ag layers and Ni layers is deposited again) using hot evaporation equipment growth regulation two-mirror layer Ag/Ni, wherein Ag layers
Thickness be 100nm, Ni layer of thickness is 30nm.
(7) growth mirror layer second step (metal layer annealing)：By the second mirror layer Ag/Ni in step (6) into fast
Process annealing is carried out in fast annealing stove, and Pd-dots/Ag/Ni mirror layers (i.e. X-dots/Ag/Y mirror layers), annealing is made
Atmosphere is N2With O2Gaseous mixture, N2With O2The ratio between the amount of substance be N2：O2=4：1, annealing temperature is 180 DEG C, annealing time
For 60s.
(8) by Ag layer in the mirror layer after scanning electron microscope detection annealing, traditional pure Ag mirror layers and tradition Ni/Ag
The SEM shape appearance figures of mirror layer, detection method are identical.As shown in figure 14, be embodiment 33 the step of (7) in Pd-dots/Ag/
SEM shape appearance figures after the annealing of Ni mirror layers.It can be seen that compared to traditional pure Ag mirror layers and Ni/Ag mirror layers,
The phenomenon that Pd-dots/Ag/Ni speculums manufactured in the present embodiment then essentially eliminate Ag layers of cluster avoids traditional Ag radiation
Diffusion, cluster and the oxidative phenomena of mirror layer, greatly improved the thermal stability of Ag mirror layers, be unlikely to cause to adulterate p-type
The destruction of GaN film.
(9) mirror layer and Ni/Ag in conventional vertical configuration LED chip in the present embodiment are measured by reflectance test instrument
The reflectivity of mirror layer, test method are consistent with the above.Figure 15 is Pd-dots/Ag/Ni prepared by the present embodiment step (7)
The reflectivity figure line of mirror layer.It can be seen that compared to the reflection of Ni/Ag mirror layers in conventional vertical configuration LED chip
The reflectivity of rate, Pd-dots/Ag/Ni mirror layers manufactured in the present embodiment is substantially improved, especially in blue wave band, instead
The promotion for penetrating rate is more obvious.
(10) bonding and substrate transfer：The Pd-dots/Ag/Ni mirror layers surface prepared to step (7) passes through hot evaporation
Cr/Pt/Au protective layers metal is deposited in equipment, and (i.e. first vapor deposition first layer protects metal Gr, then second layer protection Pt metal is deposited, most
Vapor deposition third layer protects metal Au afterwards), protective layer P3 (i.e. the first protective layer) is made.Equally, it is being protected by hot evaporation equipment
Vapor deposition Au/Sn bond wires (i.e. first first layer bond wire Sn is deposited in vapor deposition first layer bond wire Au again), is made on layer P3
Bonded layer P2.Wherein the thickness of Sn is 2500nm, and the thickness of Au is 60nm.The mode being bonded using metallic high temperature high pressure is by LED
Epitaxial wafer is transferred on conductive Si substrate layers P1, and temperature is 400 DEG C, bonding time 20min.Then, after bonding
Pt is deposited on Si substrate layers P1 as coat of metal (i.e. the second protective layer), thickness 100nm.
(11) former substrate is removed：Remove original epitaxy Si substrate using chemical corrosion method, etchant solution be hydrofluoric acid with
The ratio between substance withdrawl syndrome of the mixed liquor of nitric acid, hydrofluoric acid and nitric acid is 1:10, thus expose n-GaN layers of P7.
(12) n-electrode is prepared：SiO is deposited by PECVD (vapour deposition process of plasma enhanced chemical)2Passivation layer,
Using standard photolithography process such as spin coating, photoetching, developments, it is sequentially prepared LED chip n-electrode pattern, wherein spin coating uses negativity light
Photoresist, spin coating time 10s；The photoetching time is 20s, and developer solution uses negative photo glue developing solution, developing time 70s.Make
Deposited by electron beam evaporation equipment is sequentially depositing tri- layers of n-electrode gold of Ti/Al/Au on the surface for the n-GaN layers P7 that extension on piece exposes
Belong to and (first layer electrode metal Ti be first deposited, then second layer electrode metal Al is deposited, third layer electrode metal Au is finally deposited),
Wherein Ti thickness is 40nm, and Al thickness is 1800nm, and Au thickness is 150nm.It is removed in such a way that blue film is pasted and is removed more
Remaining electrode metal, prepares light emitting diode (LED) chip with vertical structure.
(13) light emitting diode (LED) chip with vertical structure manufactured in the present embodiment is chosen, the photoelectric properties using both point measurement machine tests are joined
Number test method is consistent with above-described embodiment 31.Figure 16 is light emitting diode (LED) chip with vertical structure LOP-mapping manufactured in the present embodiment
Figure；Figure 17 schemes for light emitting diode (LED) chip with vertical structure Vf2-mapping manufactured in the present embodiment.It follows that manufactured in the present embodiment hang down
The LOP mean values of straight structure LED chip are 455mW, and Vf2 mean values are 2.85V.In contrast, the present invention prepares vertical structure LED
The photoelectric properties of chip have obtained huge promotion, and wherein LOP mean values improve 44.1%, and average voltage has dropped 8.1%.
Embodiment 34
The method that embodiment 34 prepares light emitting diode (LED) chip with vertical structure is generally identical as embodiment 33, and difference is：
(3) growth nano dot contact layer second step (metal layer annealing)：N2With O2The ratio between the amount of substance be N2：O2=1：
20, annealing temperature is 800 DEG C, annealing time 10s.
(4) growth nano dot contact layer third step (wet etching generation nano dot)：By of alloying obtained in (3)
One contact layer is positioned in the acid etching solution chloroazotic acid of preparation, is taken out after impregnating 3s.
(7) growth mirror layer second step (metal layer annealing)：N2With O2The ratio between the amount of substance be N2：O2=20：1, it moves back
Fiery temperature is 150 DEG C, annealing time 300s.
(10) bonding and substrate transfer：The thickness of Sn is 100nm, and the thickness of Au is 200nm.Use metallic high temperature high pressure key
LED epitaxial wafer is transferred on conductive Si substrate layers P1 by the mode of conjunction, and temperature is 200 DEG C, and bonding time is 20 minutes.
(12) n-electrode is prepared：Spin coating time is 20s；The photoetching time is 1s, developing time 20s.Ti thickness is 100nm,
Al thickness is 2000nm, and Au thickness is 200nm.
(2), the hot evaporation equipment in (6) and (10) is substituted for magnetron sputtering apparatus.
The phenomenon that light emitting diode (LED) chip with vertical structure prepared by embodiment 31-34 essentially eliminates Ag layers of cluster, avoids tradition
Ag radiates diffusion, cluster and the oxidative phenomena of mirror layer, and reflecting layer emissivity is high；Meanwhile photoelectric properties have obtained huge carry
It rises,
The above embodiment is only the preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto,
The variation and replacement for any unsubstantiality that those skilled in the art is done on the basis of the present invention belong to institute of the present invention
Claimed range.
Claims (10)
1. a kind of light emitting diode (LED) chip with vertical structure, which is characterized in that including substrate layer and the bonded layer that is set on the substrate layer,
The X-dots/Ag/Y mirror layers that the bonded layer is equipped with the first protective layer and is set on first protective layer, it is described
The InGaN/GaN quantum well layers that X-dots/Ag/Y mirror layers are equipped with p-GaN layer and are set in the p-GaN layer, it is described
The n-electrode layer that InGaN/GaN quantum well layers are equipped with n-GaN layers and are set on the n-GaN layers；
The X is one kind in Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene, the Y
For one kind in Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl.
2. light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that in the X-dots/Ag/Y mirror layers
In, the thickness of Ag is 25~500nm, and the thickness of Y is 10~200nm.
3. light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that the X be Ni or Pd, the Y be Ti or
Ni。
4. light emitting diode (LED) chip with vertical structure as described in any one of claims 1-3, which is characterized in that the substrate layer is Si substrates
Layer, the bonded layer are Sn bonded layers, Au bonded layers or Sn/Au bonded layers, and first protective layer is Gr protective layers, Pt guarantors
Sheath, Au protective layers, Gr/Pt protective layers, Gr/Au protective layers, Pt/Au protective layers or Gr/Pt/Au protective layers, the n-electrode layer
For Ti electrode layers, Al electrode layers, Au electrode layers, Ti/Al electrode layers, Al/Au electrode layers, Ti/Au electrode layers or Ti/Al/Au electricity
Pole layer, the p-GaN layer are that p-type adulterates GaN film, and described n-GaN layers is adulterated GaN film for N-shaped.
5. a kind of preparation method of light emitting diode (LED) chip with vertical structure, which is characterized in that including：
A nano dot contact layer step) is grown：
The first step：Growth successively is taken on substrate to have n-GaN layers, the LED epitaxial wafer of InGaN/GaN quantum well layers and p-GaN layer,
The thickness of growth regulation one contact layer X/Ag, the X are 0.01~200nm in p-GaN layer, and the thickness of the Ag is 25~500nm,
The X is one kind in Cr, Ni, Ti, Pt, Pd, In, Au, NiO, TiO, ZnO, ITO, AZO, GIO and graphene；
Second step：By the first contact layer X/Ag high annealings, the first contact layer of alloying is obtained, the atmosphere of high annealing is N2
With O2The temperature of gaseous mixture, high annealing is 300~800 DEG C, and the time of high annealing is 10~300s；
Third walks：First contact of alloying is placed in corrosive liquid and impregnates, wash by water, drying, nano dot contact layer is made；
B mirror layer step) is grown：
The first step：The thickness of the growth regulation two-mirror layer Ag/Y on nano dot contact layer, the Ag are 25~500nm, the Y
Thickness be 10~200nm, the Y be Ni, Ti, Mg, Pt, Au, W, AgCu, AgMg and AgAl in one kind；
Second step：Second mirror layer Ag/Y is subjected to process annealing, generates X-dots/Ag/Y mirror layers, process annealing
Atmosphere is N2With O2The temperature of gaseous mixture, process annealing is 150~300 DEG C, and the process annealing time is 10~300s；
C) bonding and substrate transfer step：Bonded layer is grown on the mirror layer of LED epitaxial wafer, it will be outside LED by bonded layer
Prolong piece to be transferred on conductive Si substrates, the LED epitaxial wafer after bonding is made；
D former substrate step) is removed：LED epitaxial wafer after bonding is removed into former substrate by chemical attack, exposes n-GaN layers；
E n-electrode step) is prepared：N-electrode is deposited on the n-GaN layers of exposing, light emitting diode (LED) chip with vertical structure is made.
6. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that in growth nanometer point contact
In the first step of layer, when X is Cr, Ni, Ti, Pt, Pd, In or Au, the thickness of the X is 0.01~20nm；When X be NiO,
When a kind of in TiO, ZnO, ITO, AZO, GIO and graphene, the thickness of the X is 1~200nm.
7. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that in growth nanometer point contact
In the second step of layer, the N2With O2The ratio between the amount of substance be 20：1~1：20；In the second step of growth mirror layer, institute
State N2With O2The ratio between the amount of substance be 20：1~1：20.
8. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that growth nano dot contact layer
Third step in, the corrosive liquid be acid etching solution or alkaline corrosion liquid；
The acid etching solution is chloroazotic acid, and the alkaline corrosion liquid includes the mixed solution of ammonium hydroxide, hydrogen peroxide and water, wherein ammonia
Water：Hydrogen peroxide：Water (volume)=1~5：1：1.
9. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that shifted in bonding and substrate
In step, one protective layer of advance growth regulation, regrowth bonded layer on the mirror layer of LED epitaxial wafer；
First protective layer is Cr/Pt/Au coat of metal, and the bonded layer is Au/Sn metal bonding layers.
10. the preparation method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that in the former substrate step of stripping
In, the second protective layer of Si Growns of LED epitaxial wafer after bonding, then removes former substrate in advance；
Second protective layer is Pt protective layers, and the thickness of the Pt protective layers is 20~300nm；
The chemical attack is immersion corrosion solution, and the etchant solution is the mixed liquor of hydrofluoric acid and nitric acid, wherein hydrofluoric acid
It is 0.1 with the ratio between the substance withdrawl syndrome of nitric acid:1~1:0.1.
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| CN113437194A (en) * | 2021-05-26 | 2021-09-24 | 南昌大学 | Preparation method of high-reflection low-ohmic contact electrode |
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Denomination of invention: A vertical structure LED chip and its preparation method Effective date of registration: 20220520 Granted publication date: 20191018 Pledgee: Bank of China Limited by Share Ltd. Heyuan branch Pledgor: HEYUAN CHOICORE PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Registration number: Y2022980006017 |
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