CN108292644B - 螺线管电感器 - Google Patents
螺线管电感器 Download PDFInfo
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- CN108292644B CN108292644B CN201680064640.6A CN201680064640A CN108292644B CN 108292644 B CN108292644 B CN 108292644B CN 201680064640 A CN201680064640 A CN 201680064640A CN 108292644 B CN108292644 B CN 108292644B
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Abstract
提出了具有多个线圈的电感器和其上集成有这种电感器的半导体器件。在一方面,该半导体器件可以包括基板上的管芯、该管芯上的电感器,其中该电感器包括具有在该管芯上方的多个非平面线圈的导线。在另一方面,该半导体器件可以包括基板上的管芯上的多个柱子、以及该管芯上的电感器。该电感器可以包括环绕该多个柱子的导线,使得该电感器包括多个非平面线圈。
Description
相关申请的交叉引用
本专利申请要求于2015年11月8日提交的题为“SOLENOID INDUCTOR WITH AIRCORE(具有空芯的螺线管电感器)”的美国临时专利申请No.62/252,567的权益,该临时申请待决并且已被转让给本申请受让人并由此通过援引明确地整体纳入于此。
公开领域
本公开的一个或多个方面一般涉及电感器,并且尤其涉及管芯上的螺线管电感器。
背景技术
现有的薄膜工艺不足以生成高性能的3D电感器。例如,图1中解说的常规近场通信(NFC)天线100(其本质上是电感器)的尺寸是50mm×85mm(4,250mm2)。对于诸如智能电话和其他移动设备之类的应用而言,这代表了相当大量的表面积。
概述
本概述标识了一些示例方面的特征,并且不是对所公开的主题内容的排他性或穷尽性描述。各特征或各方面是被包括在本概述中还是从本概述中省略不旨在指示这些特征的相对重要性。描述了附加特征和方面,并且这些附加特征和方面将在阅读以下详细描述并查看形成该详细描述的一部分的附图之际变得对本领域技术人员显而易见。
第一方面可以涉及一种半导体器件。该半导体器件可以包括基板、该基板上的管芯、以及该管芯上的电感器。该电感器可以包括具有在该管芯上方的多个非平面线圈的导线。
第二方面可以涉及一种形成半导体器件的方法。该方法可以包括提供基板,在该基板上提供管芯,以及在该管芯上形成电感器。形成电感器可以包括环绕导线,使得该电感器包括在该管芯上方的多个非平面线圈。
第三方面可以涉及一种半导体器件。该半导体器件可以包括基板、该基板上的管芯、该管芯上的电感器、以及也在该管芯上的用于终接该电感器的装置。该电感器可以包括具有在该管芯上方的多个非平面线圈的导线。
附图简述
给出附图以帮助描述所公开的各实施例,并且提供附图是为了示出各实施例的解说而非对其进行限制。
图1解说了常规的近场通信天线;
图2解说了电感器的示例实施例;
图3A-3F解说了制造具有一个或多个片上电感器的器件的示例方法的各阶段;
图4A-4B解说了形成有多个柱子的电感器的示例实施例;
图5A-5E解说了制造具有使用多个柱子在管芯上形成的电感器的器件的示例方法的各阶段;
图6A-6D解说了形成有多个柱子的电感器的更多示例实施例;
图7A-7F解说了用于制造具有相交电感器的半导体器件的示例过程的各阶段;
图8解说了制造器件的示例方法的流程图;以及
图9解说了具有其中集成了电感器的器件的设备的示例。
详细描述
在以下针对本公开的一个或多个方面的具体实施例的描述和相关附图中公开了各方面。可以设计替换实施例而不会脱离本论述的范围。另外,众所周知的元素将不被详细描述或将被省去以免混淆相关细节。
措辞“示例性”在本文中用于表示“用作示例、实例、或解说”。本文中描述为“示例性”的任何实施例不必被解释为优于或胜过其他实施例。同样,术语“实施例”并不要求所公开主题内容的所有实施例都包括所讨论的特征、优点、或操作模式。
本文所使用的术语仅出于描述特定实施例的目的,而并不旨在限定。如本文所使用的,单数形式的“一”、“某”和“该”旨在也包括复数形式,除非上下文另有明确指示。还将理解,术语“包括”、“具有”、“包含”和/或“含有”在本文中使用时指明所陈述的特征、整数、步骤、操作、元素、和/或组件的存在,但并不排除一个或多个其他特征、整数、步骤、操作、元素、组件和/或其群组的存在或添加。
此外,许多实施例是根据将由例如计算设备的元件执行的动作序列来描述的。将认识到,本文中所描述的各种动作能由专用电路(例如,专用集成电路(ASIC))、由正被一个或多个处理器执行的程序指令、或由这两者的组合来执行。另外,本文中所描述的这些动作序列可被认为是完全体现在任何形式的计算机可读存储介质内,该计算机可读存储介质内存储有一经执行就将使相关联的处理器执行本文所描述的功能性的对应计算机指令集。由此,各个方面可以用数种不同的形式来体现,所有这些形式都已被构想落在所要求保护的主题内容的范围内。另外,对于本文中所描述的每个实施例,任何此类实施例的对应形式可在本文中被描述为例如“被配置成执行所描述的动作的逻辑”。
如以上所指出的,片上电感器技术的当前状态存在限制。常规的薄膜工艺不能生成高性能的3D电感器。然而,在一个或多个方面,提出了芯片上的螺线管电感器,其缓解了常规片上电感器的一些或全部限制。
图2解说了3D电感器(诸如螺线管电感器)的非限制性示例实施例。在该图中,示出了具有在基板205(例如,PCB)上的芯片或管芯210上的两个电感器的器件200(例如,半导体器件)。左侧的电感器250可以包括缠绕或环绕柱子220的导线240。导线240的端部终接于接合焊盘230上。接合焊盘230可以是用于终接电感器的装置的示例。右侧的电感器250可以包括不包围任何柱子220的环形导线240,即,右侧电感器250可以具有空芯。
对于每个电感器250,优选的是导线240垂直地环绕,即,电感器250可以具有多个非平面线圈。这不同于常规电感器线圈的表面安装线圈,诸如图1所解说的NFC天线。注意,常规天线100的线圈全部在单个平面上。然而,图2的每个电感器250可以包括多个非平面线圈,其包括第一线圈和第二线圈,其中第一线圈不在与第二线圈相同的平面上。而且,第一线圈和第二线圈可以至少部分地彼此垂直地交叠。导线440的端部可以终接于接合焊盘230上。非穷举性的优点列表包括:
●减少磁场损失;
●非常高的电感器性能;
●垂直方向的磁场限制了与管芯上或基板上的其他电感器的耦合;以及
●可以在管芯上调整电感。
图3A-3F解说了用于制造具有在芯片或管芯上的一个或多个电感器的半导体器件的非限制性示例方法的各阶段的侧视图。在可能的情况下,将沿用图2的元件编号,使得图2与图3A-3F之间的相关性更清楚。如在图3A中所见,可以在管芯210上形成一个或多个接合焊盘230。接合焊盘230可以被假定为导电的并且用作电感器250的端接点(见图3C)。而且,接合焊盘230可以电耦合到管芯210的电路***(未示出)。
如在图3B中所见的,可以在管芯210上形成一个或多个柱子220。柱子220可以是导电的或不导电的。柱子220也可以由可渗透材料形成。然后如在图3C中所见的,可以通过使导线240环绕柱子220来在管芯210上形成一个或多个电感器250。每个电感器250可以包括多个非平面线圈。柱子220可以用作导线240可以被环绕或缠绕到的引导件。应注意,对于每个电感器250,相应的导线240的两端终接于不同的接合焊盘230处。导线240可以是绝缘的或非绝缘的。如果柱子220是导电的,则优选绝缘导线240。如果柱子220不导电,则可以使用非绝缘导线240。当然,也可以使绝缘导线240缠绕非导电柱子220。
图3C中所解说的电感器250可以满足某些应用。换言之,半导体器件200的制造可以在此阶段停止(与图2中的左侧电感器250相比)。然而,制造可以继续进行到图3D所解说的阶段。在此阶段中,可以移除柱子220,使得电感器250具有空芯。图3D中具有空芯的电感器250相比于图3C中具有柱子220的电感器可以提供改进的性能。注意,由于这些线圈,磁场将是垂直的(如最右边电感器内的箭头所示)。垂直取向的磁场对于图3C也成立。这将有助于限制管芯210上的各电感器250之间的耦合。尽管图3C解说了所有柱子220皆被移除的示例,但这不是必须的。即,可以保留一个或多个柱子220。
制造也可以在图3D所解说的阶段停止。但是如在图3E中所见的,制造可以继续进行到用盖子370覆盖电感器250以用于附加保护的阶段。在一个方面,盖子370可以简单地包围电感器250,使得盖子370内部除了电感器250之外未被填充。在另一方面,代替用盖子370包围电感器250,制造可以继续进行到可以通过用模塑360进行封装来保护电感器250的阶段,如在图3F中所见。
虽然未示出,但各种电感器组合是可能的。例如,当存在多个电感器250时,可以存在具有和不具有柱子220的电感器250的组合。作为另一示例,一些电感器250可以用盖子370覆盖,一些电感器可以用模塑360封装,而其他电感器可能既不用盖子370覆盖、也不用模塑360封装。还要强调的是,电感器250不同于具有表面安装的平面线圈的常规电感器。例如,电感器250的线圈可以在不同的平面上。而且,各线圈可以至少部分地垂直交叠。也就是说,电感器250的一个线圈不需要完全位于同一电感器250的另一个线圈内部。
在图2和3A-3F中,每个电感器250被示为通过使导线240多次环绕单个柱子220而形成。然而,其他电感器可以通过使导线环绕多个(两个或更多个)柱子而形成。图4A-4B解说了3D电感器的非限制性示例实施例,其中可以使用多个柱子来形成电感器。在图4A中,半导体器件400可以包括基板上的管芯410(未示出基板)、管芯410上的多个柱子420、以及在管芯410上形成的一个或多个电感器450。至少一个电感器450可以包括环绕多个柱子420的导线440。
在此特定实例中,将描述左侧的电感器450。如所见到的,电感器450可以包括环绕两个柱子420的导线440。如所见到的,导线440可以多次环绕柱子420。而且,电感器450的多个线圈可以是非平面的。电感器450的两端(即,相应导线440的两端)可终接于两个接合焊盘430——第一接合焊盘430-1和第二接合焊盘430-2。电感器450可用模塑460来封装。
图4B解说了具有使用多个柱子420形成的电感器450的器件400的另一个实施例。图4B的器件类似于图4A的器件。但是代替模塑460,器件400的电感器450可以用盖子470来覆盖。在一方面,除了电感器450之外,盖子470内部可以未被填充。
虽然未示出,但还设想到,在一些实施例中,电感器450不需要设置有盖子470或模塑460。同样对于图4A和/或4B,在一些实施例中可以移除柱子420,使得电感器450的芯是空气。
图5A-5E解说了制造具有使用多个柱子在管芯上形成的电感器的器件的非限制性示例方法的各阶段。在可能的情况下,将沿用图4A和4B的元件编号。如在图5A中所见,可以在管芯410上形成多个接合焊盘430。接合焊盘430可以被假定为导电的并且用作电感器450的端接点。而且,接合焊盘430可以电耦合到管芯410的电路***(未示出)。
如在图5B中所见的,可以在管芯410上形成多个柱子420。然后,如在图5C中所见的,通过使导线440环绕多个柱子420,可以在管芯410上形成电感器450。同样,电感器450可以包括多个线圈。还优选地,这些线圈可以是垂直取向的或非平面的。也就是说,电感器450的至少第一线圈和第二线圈可以在不同的平面上。第一和第二线圈还可以至少部分地垂直相交。多个柱子420可以是导电的或不导电的。与电感器450相对应的导线440的两端可以终接于第一和第二接合焊盘430-1、430-2处。导线440可以是绝缘或非绝缘的。如果柱子420是导电的,则导线440可以是绝缘的。如果柱子420不导电,则导线440可以是绝缘的或不绝缘的。
对于某些应用,图5C中所解说的电感器450可以是满足要求的,并且因此半导体器件400的制造可以在此阶段停止。然而,对于其他应用,制造可以继续进行到图5D所解说的阶段,其中用模塑460来封装电感器450(具有或不具有柱子420)。也参见图4A。替换地,制造可以继续进行到图5E中所解说的阶段,其中电感器450被盖子470覆盖而不是被封装。也参见图4B。同样,除了电感器450(具有或不具有柱子420)之外,盖子470内部可以是未填充的。
各种电感器组合是可能的。例如,在以上提及的一个方面,该过程可以在图5C中所解说的阶段之后停止。在另一方面,该过程可以继续在图5C所解说的阶段之后移除柱子420(未示出),然后制造过程可以停止。替换地,不管柱子420是否被移除,制造过程然后可以继续提供盖子470或模塑460(未示出)。
图4A-4B和5A-5E解说了具有使用多个柱子420形成的电感器450的实现的器件400的侧视图。图6A-6D解说了可以利用多个柱子420形成的不同类型的电感器的一些特定实现的示例的俯视图。在可能的情况下,将沿用图4A、4B和5A-5D的元件编号。而且,在图6A-6D中,将不显示模塑460和盖子470以最小化混乱。但是应该认识到,一些实施例的封装器件可以包括模塑460和/或盖子470。图6A-6D可以被视为解说与图5C的侧视图相对应的半导体器件400的一些特定实现的俯视图,其中可以通过使导线440环绕多个柱子420来形成电感器450。
图6A解说了具有可用作近场通信(NFC)天线和/或用在诸如无线充电等应用中的电感器450的半导体器件400。在该图中,示出了四个柱子420,并且可以使导线440多次环绕四个柱子420。注意,对于此类应用,导线440可以非平面地环绕任何数量的柱子420(例如,三个或更多个)。导线440的第一端和第二端可以终接于第一接合焊盘430-1和第二接合焊盘430-2。
在此特定示例中,电感器450的线圈都不是完全缠绕任何个体柱子420。然而,这不是必须的。在一方面,电感器450可以包括并非完全缠绕多个柱子420中的任何个体柱子420的至少一个线圈(未示出)。
对于NFC应用(例如,在13.56MHz处操作),图6A的配置可以提供必要的电感L(例如,在1μH和3.6μH之间),同时需要比常规NFC天线更小的面积。例如,矩形线圈Lrect的电感可以通过下式(1)来近似。然后,通过提供具有以下特性(线圈=6.5,面积=11mm×11mm,导线=10μm Cu)的电感器450,可以达成电感L~2μH。换言之,与常规的NFC天线(50mm×85mm,参见图1)相比,可以在占用显著更小面积(11mm×11mm)的同时达成足够的电感。
图6B解说了具有通过按8字形环绕导线440而形成的电感器450的半导体器件400。如所见到的,示出了两个柱子420,其也可以被称为第一柱子420-1和第二柱子420-2。导线440的第一端和第二端可以终接于第一接合焊盘430-1和第二接合焊盘430-2。导线440可多次环绕第一柱子420-1和第二柱子420-2,使得各线圈是非平面的。利用这样的配置,可以生成向上取向的磁场和向下取向的磁场。例如,可以实现磁场回路。
虽然未示出,但可以利用不止两个柱子420。例如,除了第一柱子420-1和第二柱子420-2之外,还可以提供一个或多个柱子420,使得可以使用单根导线440来形成多个8字形。再次,电感器450可以包括并非完全缠绕任何个体柱子420的至少一个线圈。
图6C解说了具有可用于检测功率的电感器450的半导体器件400。图6C的电感器450可以环绕输入/输出连接650。示例可以是触点。例如,触点650可以被配置成电耦合到管芯410的输入引脚、输出引脚、电源引脚或接地引脚中的任一者。触点650可以形成在管芯410的表面上。在一个或多个实施例中,触点650可以是焊球。
利用图6C的电感器450,可以检测在触点650处发生的电切换(例如,当通电/断电时,当逻辑从低切换到高时,反之亦然)。电感器450可以通过使导线440多次环绕多个柱子420以便包围触点650而形成。导线440的端部可以终接于接合焊盘430-1、430-2处。虽然仅示出三个柱子420,但柱子420的数量可以更多。注意,随着柱子420的数量增长,电感器线圈的形状可以更好地符合触点650的形状。至少一个线圈可以使得其并非完全缠绕任何个体柱子420。
图6D解说了具有彼此相邻的两个电感器450-1、450-2的半导体器件。在该图中,多个柱子420可以被视为包括第一多个柱子420-1、420-2和第二多个柱子420-3、420-4。第一电感器450-1可以通过使第一导线440-1多次环绕第一多个柱子420-1、420-2例如以便形成非平面线圈而形成。第一导线440-1的端部可终接于接合焊盘430-1、430-2处。而且,第二电感器450-2可以通过使第二导线440-2多次环绕第二多个柱子420-3、420-4例如以便形成非平面线圈而形成。第二导线440-2的端部可以终接于接合焊盘430-3、430-3。
在图6D中,两个相邻电感器450-1、450-2被示为垂直相交。采用这种配置,可按需隔离或抵消磁场。然而,不要求电感器450-1、450-2垂直相交。例如,虽然未示出,但是一个电感器(例如,第一电感器450-1)可以放置在另一个电感器(例如,第二电感器450-2)内部。两个电感器450-1、450-2可以充分靠近彼此放置,从而可以发生一些耦合(例如,用于磁场隔离和/或抵消)。注意,可以控制耦合量。而且,第一和/或第二多个柱子420中的一者或两者可以包括不止两个柱子420(未示出)。另外,可以有不止两个电感器450放置在彼此附近(未示出)。
图7A-7F解说了用于制造图6D中所解说的半导体器件400的非限制性示例过程的一些阶段。图7A解说了在管芯410上形成的第一多个柱子420-1、420-2,第二多个柱子420-3、420-4,以及接合焊盘430-1、430-2、430-3、430-4。在图7B中,第一导线440-1被解说为环绕第一多个柱子420-1、420-2以形成第一电感器450-1。第一导线440-1可以接合到柱子420-1附近的接合焊盘430-1并且环绕在柱子420-2外部。如图7C所见,第一导线440-1可以按8字形绕着柱子420-1并且在图7B中先前所示的第一导线440-1的部分之上继续。第一导线440-1可以按该8字形环绕多次(也参见图6B的电感器450)到接合至接合焊盘430-2之处以完成第一电感器450-1。
以类似的方式,可以形成第二电感器450-2。如在图7D中所见的,第二导线440-2可以接合到靠近柱子420-3的接合焊盘430-3并且环绕在柱子420-4外部。如图7E所见,第二导线440-2可以再次按8字形绕着柱子420-3并且在图7D中先前所示的第二导线440-1的部分之上继续。第二导线440-2可以按该8字形环绕多次到接合至接合焊盘430-4之处以完成第二电感器450-2。第二导线440-2可以在第一导线440-1上方。
图7F解说了沿着图7E的线A-A的半导体器件的横截面的侧视图。注意,第二导线440-2的线圈(以点解说)位于第一导线440-1的线圈上方。在该侧视图中,第一导线440-1(对应于第一电感器450-1)被示为具有多个非平面线圈。类似地,第二导线440-2(对应于第二电感器450-2)被示为具有多个非平面线圈。
关于通过利用多个柱子420形成的电感器450,导线440不需要完全缠绕任何个体柱子420。而且,各线圈可以是一致的。也就是说,电感器450的各线圈可以彼此垂直交叠。以这种方式,可以使电感器450的芯内的磁场更均匀。在一个或多个方面,当使用多个柱子420形成电感器450时,可以说对于电感器450的至少一个线圈,对应于电感器450的导线440不需要完全缠绕任何个体柱子420。也可以说电感器450的至少一个线圈可以与电感器450的至少一个其他线圈垂直交叠。
图8解说了制造器件(诸如器件200、400)的非限制性示例方法的流程图。应注意,并非图8所解说的所有框都需要被执行,即,一些框可以是可任选的。而且,对图8的框的数字引用不应被视为要求这些框应当按特定顺序执行。
在框810中,可以在基板205(诸如PCB)上提供管芯210、410。在框820中,可以在管芯210、410上形成一个或多个接合焊盘230、430。图3A和5A可以对应于框820。在框830中,可以在管芯210、410上形成一个或多个柱子220、420。图3B和图5B可以对应于框830。
在框840中,可以形成一个或多个电感器250、450。图3C和5C可以对应于框840。电感器250、450可以通过环绕导线240、440来形成,以使得电感器250、450包括在管芯210、410上方的多个非平面线圈。电感器250可以通过使导线240环绕单个柱子220而形成,如在图3C中所见的。
电感器450可以通过使导线440环绕多个柱子420而形成,如在图5C中所见的。具体的示例实现在图6A(例如,NFC天线)、6B(例如,8字形线圈)和6C(例如,功率检测)中解说。在一方面,电感器450的至少一个线圈不需要完全缠绕任何个体柱子420。制造方法800可以在框840之后停止。
方法800还可以在框860中继续,其中可以移除柱子220、420。图3D可以对应于框830。该框是可任选的,因为柱子220、420不需要被移除。如果柱子220、420被移除,则电感器250、450可具有空芯。制造方法800可以在框860之后停止。
在框870中,电感器250、450可以被盖子370、470包围。图3E和5E可以对应于框870。替换地,在框880中,电感器250、450可以用模塑360、460来封装。图3F和5D可对应于框880。
如果期望功率检测电感器(参见图6C),则方法800在框835中可以在管芯410上形成触点650,并且可以在框840中形成电感器450以包围触点650。触点650可以耦合至管芯410的输入引脚、输出引脚、电源引脚和接地引脚中的任一者。
如果期望多个电感器(参见图6D、7A-7F),则除了在框840中形成第一电感器450-1之外,方法800在框845中可以在框845中形成第二电感器450-2。例如,第二电感器450-2可以通过使第二导线440环绕第二多个柱子420-3、420-4而形成。第二电感器450-2可以包括在管芯410上方的多个非平面线圈。第二电感器450-2也可以与第一电感器450-1垂直相交。
图9解说了可以集成有包括电感器250、450的任何前述器件200、400的各种电子设备。例如,移动电话设备902、膝上型计算机设备904和固定位置终端设备906可以包括如本文所述的器件封装900。器件封装900可以是例如集成电路、管芯、集成器件、集成电路器件、器件封装、半导体器件、层叠封装器件等中的任一者。图9中所解说的设备902、904、906仅是示例性的。其他电子设备也可以将器件200、400作为特征,包括但不限于包括以下各项的设备群(例如电子设备):移动设备、手持个人通信***(PCS)单元、便携式数据单元(诸如个人数字助理)、启用全球定位***(GPS)的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单元(诸如仪表读取装备)、通信设备、智能手机、平板电脑、计算机、可穿戴设备、服务器、路由器、在机动车辆(例如自主车辆)中实现的电子设备、或者存储或检索数据或计算机指令的任何其他设备、或其任何组合。
本领域技术人员将领会,信息和信号可使用各种不同技术和技艺中的任何一种来表示。例如,贯穿上面说明始终可能被述及的数据、指令、命令、信息、信号、比特、码元和码片可由电压、电流、电磁波、磁场或磁粒子、光场或光粒子、或其任何组合来表示。
此外,本领域技术人员将领会,结合本文所公开的实现所描述的各种解说性逻辑框、模块、电路和算法可被实现为电子硬件、计算机软件、或两者的组合。为清楚地解说硬件与软件的这种可互换性,各种解说性组件、框、模块、电路、以及过程在上面是以其功能性的形式作一般化描述的。此类功能性是被实现为硬件还是软件取决于具体应用和施加于整体***的设计约束。技术人员可针对每种特定应用以不同方式来实现所描述的功能性,但此类实现决策不应被解读为致使脱离本文描述的本技术的范围。
结合本文所公开的实现所描述的方法、序列和/或算法可直接在硬件中、在由处理器执行的软件模块中、或在这两者的组合中体现。软件模块可驻留在RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动盘、CD-ROM或者本领域中所知的任何其他形式的存储介质中。示例性存储介质耦合到处理器以使得该处理器能从/向该存储介质读写信息。替换地,存储介质可以被整合到处理器。
相应地,本文描述的技术的实现可包括体现制造半导体器件的方法的计算机可读介质。相应地,本文所描述的技术不限于所解说的示例,并且用于执行本文所描述的功能性的任何手段均被包括在本文所描述的技术的实现中。
尽管前面的公开示出了本文所描述的技术的解说性实现,但是应当注意,可在其中作出各种改变和修改而不会脱离如所附权利要求定义的本文所描述的技术的范围。根据本文所描述的技术的实现的方法权利要求的功能和/或动作无需按任何特定次序来执行。此外,尽管本文所描述的技术的要素可能是以单数来描述或主张权利的,但是复数也是已构想了的,除非显式地声明了限定于单数。
Claims (18)
1.一种半导体器件,包括:
基板;
所述基板上的管芯;
所述管芯上的第一多个柱子和第二多个柱子;以及
所述管芯上的第一电感器和第二电感器,
其中所述第一电感器包括环绕所述第一多个柱子的第一导线,并且所述第一电感器具有在所述管芯上方的多个非平面线圈,
其中所述第二电感器包括环绕所述第二多个柱子的第二导线,并且所述第二电感器具有在所述管芯上方的多个非平面线圈,以及
其中所述第一电感器与所述第二电感器垂直相交或者所述第一电感器在所述第二电感器内部。
2.如权利要求1所述的半导体器件,其特征在于,还包括在所述管芯上并且包围所述第一电感器的盖子。
3.如权利要求2所述的半导体器件,其特征在于,所述盖子内部除了所述第一电感器以外未被填充。
4.如权利要求1所述的半导体器件,其特征在于,还包括在所述管芯上的模塑,所述模塑封装所述第一电感器。
5.如权利要求1所述的半导体器件,其特征在于,所述第一电感器并非完全缠绕所述第一多个柱子中的任何个体柱子。
6.如权利要求1所述的半导体器件,其特征在于,所述第一电感器的至少一个线圈并非完全缠绕所述第一多个柱子中的任何个体柱子。
7.如权利要求1所述的半导体器件,其特征在于,
所述第一多个柱子包括第一柱子和第二柱子,并且
所述第一导线按8字形环绕所述第一柱子和第二柱子。
8.如权利要求1所述的半导体器件,其特征在于,还包括在所述管芯上的触点,
其中所述触点被配置为电耦合到所述管芯的输入引脚、输出引脚、电源引脚和接地引脚之一,并且
其中所述第一电感器包围所述触点。
9.如权利要求1所述的半导体器件,其特征在于,还包括所述管芯上的第一和第二接合焊盘,
其中所述第一导线的第一端和第二端分别终接于第一和第二接合焊盘。
10.如权利要求1所述的半导体器件,其特征在于,
所述第一多个柱子是导电柱子,并且所述第一导线是绝缘导线,或者
所述第一多个柱子是非导电柱子,并且所述第一导线是非绝缘导线。
11.一种制造半导体器件的方法,所述方法包括:
在基板上提供管芯;
在所述管芯上形成第一多个柱子和第二多个柱子;以及
在所述管芯上形成第一电感器和第二电感器,
其中形成所述第一电感器包括使第一导线环绕所述第一多个柱子,使得所述第一电感器包括在所述管芯上方的多个非平面线圈,
其中形成所述第二电感器包括使第二导线环绕所述第二多个柱子,使得所述第二电感器包括在所述管芯上方的多个非平面线圈,以及
其中形成所述第二电感器包括形成所述第二电感器以便与所述第一电感器垂直相交或者使得所述第一电感器在所述第二电感器内部。
12.如权利要求11所述的方法,其特征在于,还包括在所述管芯上用盖子包围所述第一电感器。
13.如权利要求11所述的方法,其特征在于,还包括在所述管芯上用模塑封装所述第一电感器。
14.如权利要求11所述的方法,其特征在于,形成所述第一电感器包括使所述第一导线环绕所述第一多个柱子,使得所述第一电感器的至少一个线圈并非完全缠绕所述第一多个柱子中的任何个体柱子。
15.如权利要求11所述的方法,其特征在于,
形成所述第一多个柱子包括形成第一柱子和第二柱子,并且
形成所述第一电感器包括使所第一述导线以8字形环绕所述第一柱子和第二柱子。
16.如权利要求11所述的方法,其特征在于,还包括在所述管芯上形成触点并且所述触点电耦合到所述管芯的输入引脚、输出引脚、电源引脚和接地引脚之一,并且
其中形成所述第一电感器包括形成所述第一电感器以包围所述触点。
17.一种半导体器件,包括:
基板;
所述基板上的管芯;
所述管芯上的第一多个柱子和第二多个柱子;
所述管芯上的第一电感器和第二电感器;以及
在所述管芯上的用于终接所述第一电感器和所述第二电感器的装置,
其中所述第一电感器包括环绕所述第一多个柱子的第一导线,并且所述第一电感器具有在所述管芯上方的多个非平面线圈,
其中所述第二电感器包括环绕所述第二多个柱子的第二导线,并且所述第二电感器具有在所述管芯上方的多个非平面线圈,以及
其中所述第一电感器与所述第二电感器垂直相交或者所述第一电感器在所述第二电感器内部。
18.如权利要求17所述的半导体器件,其中所述第一电感器的至少一个线圈并非完全缠绕所述第一多个柱子中的任何个体柱子。
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US20050285262A1 (en) * | 2002-09-10 | 2005-12-29 | James Knapp | Semiconductor device with wire bond inductor and method |
US20070296056A1 (en) * | 2006-06-27 | 2007-12-27 | Texas Instruments Incorporated | Integrated Circuits Having Controlled Inductances |
CN103650075A (zh) * | 2011-06-30 | 2014-03-19 | 美国亚德诺半导体公司 | 芯片上的具有磁性的隔离型功率转换器 |
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Also Published As
Publication number | Publication date |
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CN108292644A (zh) | 2018-07-17 |
US20170133148A1 (en) | 2017-05-11 |
US10332671B2 (en) | 2019-06-25 |
WO2017079767A9 (en) | 2017-06-01 |
JP2018538685A (ja) | 2018-12-27 |
WO2017079767A1 (en) | 2017-05-11 |
EP3371827A1 (en) | 2018-09-12 |
EP3371827B1 (en) | 2021-09-15 |
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