CN108269784A - 中介层，以及包含中介层的半导体封装体及其制作方法 - Google Patents

中介层，以及包含中介层的半导体封装体及其制作方法 Download PDF

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CN108269784A
CN108269784A CN201710085776.1A CN201710085776A CN108269784A CN 108269784 A CN108269784 A CN 108269784A CN 201710085776 A CN201710085776 A CN 201710085776A CN 108269784 A CN108269784 A CN 108269784A
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layer
electrode
redistribution
organic substrate
conductive column
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CN108269784B (zh
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施信益
管式凡
吴铁将
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明公开了一种中介层，以及包含中介层的半导体封装体及其制作方法，其中中介层包括第一重分布层、有机基板、电容、硬罩层、第一导电柱及第二重分布层。有机基板位于第一重分布层上。电容嵌设于有机基板中且包括第一电极层、第二电极层，以及位于第一电极层及第二电极层之间的电容介电层，第一电极层电性连接第一重分布层。硬罩层位于有机基板上。导电柱嵌设于有机基板及硬罩层中且电性连接第一重分布层。第二重分布层位于硬罩层上且电性连接第二电极层及导电柱。电容嵌设于有机基板中，而有益于微缩中介层的尺寸，有机基板则可降低制作中介层的成本，并且，硬罩层可避免中介层发生翘曲。

Description

中介层，以及包含中介层的半导体封装体及其制作方法
技术领域
本发明是关于具有嵌入的金属—绝缘体—金属(Metal-insulator-metal，MIM)电容的半导体封装体及其制作方法。本发明特别是关于具有嵌入的MIM电容的中介层、含有此中介层的半导体封装体及制作此半导体封装体的方法。
背景技术
半导体集成电路(Integrated circuit，IC)产业历经快速发展，在发展期间，半导体装置的尺寸及形状均巨幅地缩小。近期以来，工业上已发展出能够垂直整合半导体装置的技术，其中一种常见的已知方法为2.5维(2.5-dimensional，2.5D)封装技术。
在2.5维封装技术中，常利用将主动元件和被动元件(例如：电容)形成于硅中介层上的方式来形成半导体封装体。然而，这些主动元件和被动元件通常需要较大的安装空间，因此，要进一步微缩半导体封装体的尺寸是困难的。因此，目前亟需发展出改良的中介层、改良的半导体封装体及制作此半导体封装体的方法。
发明内容
本发明的目的在于提供一种中介层、含有此中介层的半导体封装体及制作此半导体封装体的方法，其将电容嵌设于有机基板中，而有益于微缩中介层的尺寸，有机基板则可降低制作中介层的成本，并且，硬罩层可避免中介层发生翘曲。
为实现上述目的，本发明提供一种中介层，中介层包括第一重分布层、有机基板、电容、硬罩层、第一导电柱及第二重分布层。有机基板位于第一重分布层上。电容嵌设于有机基板中且包括第一电极层、第二电极层，以及位于第一电极层及第二电极层之间的电容介电层，第一电极层电性连接第一重分布层。硬罩层位于有机基板上。第一导电柱嵌设于有机基板及硬罩层中且电性连接第一重分布层。第二重分布层位于硬罩层上且电性连接第二电极层及第一导电柱。
在一实施方式中，第一电极层围绕第二电极层，且与第二电极层共轴。
在一实施方式中，电容贯穿有机基板。
在一实施方式中，第一导电柱贯穿硬罩层及有机基板。
在一实施方式中，第一导电柱通过第二重分布层电性连接第二电极层。
在一实施方式中，第一电极层具有与第一重分布层共平面的平面。
在一实施方式中，第一电极层具有与硬罩层共平面的平面。
在一实施方式中，第一导电柱具有与第二重分布层共平面的平面。
在一实施方式中，中介层进一步包括微凸块，微凸块电性连接第一重分布层。
在一实施方式中，中介层进一步包括第二导电柱，第二导电柱嵌设于硬罩层中，且介于第二电极层及第二重分布层之间。
为实现前述目的，本发明又提供一种半导体封装体，半导体封装体包括中介层、微凸块及晶片。中介层包括第一重分布层、有机基板、电容、硬罩层、第一导电柱及第二重分布层。有机基板位于第一重分布层上。电容嵌设于有机基板中且包括第一电极层、第二电极层，以及位于第一电极层及第二电极层之间的电容介电层，第一电极层电性连接第一重分布层。硬罩层位于有机基板上。第一导电柱嵌设于有机基板及硬罩层中且电性连接第一重分布层。第二重分布层位于硬罩层上且电性连接第二电极层及第一导电柱。微凸块电性连接第一重分布层。晶片连接微凸块。
在一实施方式中，第一电极层围绕第二电极层，且与第二电极层共轴。
在一实施方式中，第一导电柱通过第二重分布层电性连接第二电极层。
在一实施方式中，第一电极层具有与硬罩层共平面的平面。
为实现前述目的，本发明还提供一种制作半导体封装体的方法。该方法包含：在第一重分布层上形成有机基板。在有机基板中嵌设电容，电容包括第一电极层、第二电极层，以及位于第一电极层及第二电极层之间的电容介电层，第一电极层电性连接第一重分布层。在有机基板上形成硬罩层。在硬罩层及有机基板中嵌设第一导电柱以电性连接第一重分布层。在硬罩层上形成第二重分布层以电性连接第一导电柱及第二电极层。形成微凸块以电性连接第一重分布层。将晶片与微凸块连接。
在一实施方式中，在有机基板中嵌设电容包括以下步骤，在有机基板中形成沟槽以暴露出第一重分布层；在沟槽中形成第一电极层；在第一电极层上形成电容介电层；以及在电容介电层上形成第二电极层。
在一实施方式中，在硬罩层及有机基板中嵌设第一导电柱包括以下步骤：通过具有孔洞的硬罩层蚀刻有机基板以形成沟槽以暴露出第一重分布层；以及在沟槽中形成第一导电柱。
在一实施方式中，制作半导体封装体的方法进一步包括在硬罩层中和第二电极层及第二重分布层之间嵌设第二导电柱。
在一实施方式中，在第一重分布层上形成有机基板之前，制作半导体封装体的方法进一步包括在钝化层上形成第一重分布层，其中微凸块嵌设于钝化层中且接触第一重分布层。
在一实施方式中，电容的第二电极层通过第二重分布层电性连接第一导电柱。
本发明与现有技术相比，其将电容嵌设于有机基板中，具有益于微缩中介层的尺寸，降低制作中介层的成本，免中介层发生翘曲的有益效果。
应该理解的是，前述的一般性描述和下列具体说明仅仅是示例性和解释性的，并旨在提供所要求的本发明的进一步说明。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，结合附图详细说明如下：
图1是根据各种实施方式的制作半导体封装体的方法的流程图。
图2～15是根据各种实施方式的半导体封装体在各种制作阶段的剖面图。
具体实施方式
为了使本发明的叙述更加详尽与完备，可参照所附的附图及以下所述各种实施例，附图中相同的号码代表相同或相似的元件。
以下将以附图公开本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化附图起见，一些公知惯用的结构与元件在附图中将以简单示意的方式绘示。
当一个元件被称为“连接”或“耦接”至另一个元件时，它可以为直接连接或耦接至另一个元件，又或是其中有一个额外元件存在。相对的，当一个元件被称为“直接连接”或“直接耦接”至另一个元件时，其中是没有额外元件存在。
请同时参阅图1及图2～15。图1是根据各种实施方式的制作如图15所示的半导体封装体的方法100的流程图。方法100包括操作112～132。图2～15是根据各种实施方式的半导体封装体200在各种制作阶段的剖面图。虽然下文中利用一系列的操作来说明在此公开的方法，但是这些操作所示的顺序不应被解释为本发明的限制。例如，某些操作可以按不同顺序进行及/或与其它操作同时进行。此外，并非必须执行所有绘示的操作才能实现本发明的实施方式。此外，在此所述的每一个操作可以包含数个子步骤或动作。
在操作112，如图2所示，在第一载体层210及钝化层220上形成第一重分布层230。钝化层220是设置于第一载体层210上。第一重分布层230包括第一互连结构232及第一介电层234。第一互连结构232嵌设于第一介电层234中，且可包括多层金属层。第一介电层234可包括多层介电层。
在一实施方式中，第一载体层210为玻璃基板、金属基板、硅基板或陶瓷基板。此外，钝化层220可包括无机材料或有机材料。举例来说，钝化层220的材料包括但不限于二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、碳化硅(SiC)、聚酰亚胺(Polyimide，PI)、聚苯恶唑(Polybenzoxazole，PBO)或其组合。
在操作114，如图3所示，在第一重分布层230上形成有机基板240。举例来说，有机基板240的材料包括但不限于聚酰亚胺、苯并环丁烯(Benzocyclobutene，BCB)、聚苯恶唑、环氧树脂或其组合。
在操作116，如图6所示，在有机基板240中嵌设电容250a及电容250b以电性连接第一重分布层230。电容250a及电容250b皆具有金属—绝缘体—金属结构，且可通过下列步骤形成。请参阅图4～6，如图4所示，在有机基板240中形成沟槽T1以暴露出第一重分布层230，更详细来说，第一互连结构232的一部分会通过沟槽T1而暴露出来，随后，如图5所示，在沟槽T1中及有机基板240上形成第一电极层252，在第一电极层252上形成电容介电层254，并且在电容介电层254上形成第二电极层256。举例来说，第一电极层252及第二电极层256可通过电镀(Electroplating)、非电解电镀(Electroless plating)或溅镀(Sputtering)来形成，并且电容介电层254可通过原子层沉积(Atomic layer deposition，ALD)或电浆辅助化学气相沈积(Plasma-enhanced chemical vapor deposition，PECVD)来形成。在一实施方式中，第一电极层252包括阻障层(Barrier layer)及导电层。第一电极层252及第二电极层256可通过任何合适的导电材料所组成，导电材料例如为铜、铬、镍、铝、金、银、钨、钛、钽、锡、铂、钯、氮化钛(titanium nitride，TiN)、钛钨(titanium tungsten，TiW)、氮化钽(tantalum nitride，TaN)、镍钒(nickel vanadium，NiV)或铬铜(chromium copper，CrCu)。接下来，如图6所示，平坦化第一电极层252、电容介电层254及第二电极层256以在沟槽T1中形成电容250a及电容250b。在一实施方式中，在平坦化后，电容250a的上表面与有机基板240共平面。然而，在其他实施方式中，在平坦化后，电容250a的上表面为凹型上表面。举例来说，平坦化工艺可为化学机械研磨(Chemical mechanical polishing，CMP)工艺。
如图6所示，电容250a贯穿有机基板240，且包括第一电极层252a、电容电极层254a及第二电极层256a。电容电极层254a位于第一电极层252a及第二电极层256a间，使得第一电极层252a可通过电容电极层254a与第二电极层256a绝缘。详细来说，第一电极层252a围绕电容电极层254a，且与电容电极层254a共轴，并且，电容电极层254a围绕第二电极层256a，且与第二电极层256a共轴。因此，第一电极层252a围绕第二电极层256a，且与第二电极层256a共轴。此外，第一电极层252a具有与第一重分布层共平面的平面S1。因此，第一电极层252a是接触第一重分布层230的第一互连结构232，且与第一重分布层230电性连接。电容250b包括第一电极层252b、电容电极层254b及第二电极层256b。由于电容250b的结构与电容250a相同，在此无须赘述。
在操作118，如图7所示，在有机基板240、电容250a及电容250b上形成硬罩层260。硬罩层260具有孔洞H1及孔洞H2。举例来说，孔洞H1及孔洞H2可通过图案化光阻层蚀刻硬罩层来形成，图案化光阻层则可通过曝光和显影工艺来形成。电容250a和电容250b是通过孔洞H1暴露出来，而有机基板240的一些部分则通过孔洞H2暴露出来。硬罩层260可通过任何具有低热膨胀系数(coefficient of thermal expansion，CTE)的合适材料形成，举例来说，硬罩层260的材料包括二氧化硅(silicon dioxide，SiO2)、氮化硅(silicon nitride，Si3N4)、氮氧化硅(silicon oxynitride，SiON)或其组合。
如先前所述，在一实施方式中，电容250a的上表面与有机基板240共平面。因此，在此实施方式中，电容250a的上表面与硬罩层260共平面。详细来说，第一电极层252a具有与硬罩层260共平面的平面S2，电容介电层254a具有与硬罩层260共平面的平面S3，第二电极层256a具有与硬罩层260共平面的平面S4。
在操作120，如图9所示，在硬罩层260及有机基板240中嵌设第一导电柱272以电性连接第一重分布层230。第一导电柱272可通过以下步骤形成，请参阅图8～9，如图8所示，通过硬罩层260的孔洞H2蚀刻有机基板240以形成沟槽T2以暴露出第一重分布层230。详细来说，第一互连结构232的一些部分是通过沟槽T2而暴露出来。如图9所示，在沟槽T2中形成第一导电柱272，同时，在孔洞H1中形成第二导电柱274。
如图9所示，第一导电柱272贯穿硬罩层260及有机基板240，并且接触第一重分布层230的第一互连结构232，因此，第一导电柱272能够电性连接第一重分布层230。此外，第二导电柱274贯穿硬罩层260，并且接触第二电极层256a及256b，因此，第二导电柱274能够电性连接第二电极层256a及256b。
在操作122，如图10所示，在硬罩层260上形成第二重分布层280以电性连接第一导电柱272及电容250a及电容250b。第二重分布层280包括第二互连结构282及第二介电层284。第二互连结构282嵌设于第二介电层284中。因此，详细来说，第一导电柱272是配置于第一互连结构232及第二互连结构282之间。此外，第二互连结构282可包括多层金属层。第二介电层284可包括多层介电层。
如图10所示，第二互连结构282接触第一导电柱272及第二导电柱274，使得第二互连结构282能够与第一导电柱272及第二导电柱274电性连接。在一实施方式中，各第一导电柱272具有与第二重分布层280共平面的平面S5，并且各第二导电柱274也具有与第二重分布层280共平面的平面S6。此外，第二电极层256a通过第二重分布层280电性连接第一导电柱272的其中一个。然而，第二电极层256b并没有通过第二重分布层280电性连接任何的第一导电柱272。在一实施方式中，第二电极层256b是与第一导电柱272电性绝缘。
在操作124，如图11所示，在第二重分布层280中嵌设凸块下金属层(Under bumpmetallization，UBM)结构286。凸块下金属层结构286接触第二互连结构282，因而电性连接第二互连结构282。此外，凸块下金属层结构286的上表面皆暴露出来以在后续的操作中用于连接焊球。在一实施方式中，凸块下金属层结构286包括黏着层(Adhesion layer)、阻障层(Barrier layer)、晶种层(Seed layer)、润湿层(Wetting layer)或其组合。凸块下金属层结构286的材料包括但不限于铜、铬、镍、铝、金、银、钨、钛、钽、锡、铂、钯、氮化钛、钛钨、氮化钽、镍钒或铬铜。
在操作126，如图12所示，移除第一载体层210以暴露出钝化层220，并在第二重分布层280上形成第二载体层294。详细来说，第二载体层294系通过黏着层292附着于第二重分布层280上。在一实施方式中，第一载体层210可通过研磨(Grinding)、蚀刻或上述两种方法来移除。在一实施方式中，第二载体层294为玻璃基板、金属基板、硅基板或陶瓷基板。
在操作128，如图13所示，形成微凸块300以电性连接第一重分布层230。详细来说，在钝化层220中嵌设微凸块300，且使微凸块300接触第一重分布层230的第一互连结构232。
在操作130，如图14所示，将晶片310a及晶片310b与微凸块300连接。并且，为了封装晶片310a及晶片310b，形成封胶胶材(Molding compound)320围绕晶片310a及晶片310b、微凸块300及钝化层220。在一实施方式中，晶片310a的类型与晶片310b相同。在其他实施方式中，晶片310a的类型与晶片310b不相同。
在操作132，如图15所示，形成焊球330以电性连接第二重分布层280以形成半导体封装体200。详细来说，在形成焊球330前，先移除黏着层292及第二载体层294以暴露出凸块下金属层结构286，随后，在凸块下金属层结构286上形成焊球330，因而电性连接第二重分布层280。在一实施方式中，半导体封装体200进一步包括封装体基板(未示出)，例如：印刷电路板(printed circuit board，PCB)。而焊球330可与印刷电路板连接。
如图15所示，半导体封装体200包括中介层400、晶片310a、晶片310b及封胶胶材320。中介层400包括钝化层220、第一重分布层230、有机基板240、电容250a、电容250b、硬罩层260、第一导电柱272、第二导电柱274、第二重分布层280、微凸块300、凸块下金属层结构286及微凸块300。第一重分布层230位于钝化层220上。微凸块300嵌设于钝化层220中并与第一重分布层230电性连接。有机基板240位于第一重分布层230上。电容250a及电容250b嵌设于有机基板240，电容250a包括第一电极层252a、第二电极层256a，以及位于第一电极层252a及第二电极层256a间的电容介电层254a，电容250b包括第一电极层252b、第二电极层256b，以及位于第一电极层252b及第二电极层256b间的电容介电层254b。第一电极层252a及第一电极层252b电性连接第一重分布层230。硬罩层260位于有机基板240上。第一导电柱272嵌设于有机基板240及硬罩层260中且电性连接第一重分布层230。第二重分布层280位于硬罩层260上且电性连接第二电极层256a、第二电极层256b及第一导电柱272。凸块下金属层结构286嵌设于第二重分布层280中。焊球330位于凸块下金属层结构286及第二重分布层280上且电性连接第二重分布层280。
综上所述，本发明的中介层和半导体封装体至少具有以下优点，嵌设于有机基板中的电容为沟槽式而因此具有较高的电容值。并且，这些电容仅需小的安装空间，而因此有益于微缩半导体封装体的尺寸。此外，使用有机基板可以降低制作中介层及半导体封装体的成本。具有低热膨胀系数的硬罩层可避免中介层翘曲(Warpage)及半导体封装体翘曲。
虽然本发明已以实施方式公开如上，以上所述仅为本发明的优选实施例，并非用以限定本发明，任何本领域的一般技术人员，在不脱离本发明的精神和范围内，当可作各种的均等变化与修饰，皆应属本发明的涵盖范围，因此本发明的保护范围当视权利要求所界定的为准。

Claims (20)

1.一种中介层，其特征在于，包括：
第一重分布层；
有机基板，位于所述第一重分布层上；
电容，嵌设于所述有机基板中，所述电容包括第一电极层、第二电极层，以及位于所述第一电极层及所述第二电极层之间的电容介电层，所述第一电极层电性连接所述第一重分布层；
硬罩层，位于所述有机基板上；
第一导电柱，嵌设于所述有机基板及所述硬罩层中，所述第一导电柱电性连接所述第一重分布层；以及
第二重分布层，位于所述硬罩层上，所述第二重分布层电性连接所述第二电极层及所述第一导电柱。
2.如权利要求1所述的中介层，其特征在于，所述第一电极层围绕所述第二电极层，且与所述第二电极层共轴。
3.如权利要求1所述的中介层，其特征在于，所述电容贯穿所述有机基板。
4.如权利要求1所述的中介层，其特征在于，所述第一导电柱贯穿所述硬罩层及所述有机基板。
5.如权利要求1所述的中介层，其特征在于，所述第一导电柱通过所述第二重分布层电性连接所述第二电极层。
6.如权利要求1所述的中介层，其特征在于，所述第一电极层具有与所述第一重分布层共平面的平面。
7.如权利要求1所述的中介层，其特征在于，所述第一电极层具有与所述硬罩层共平面的平面。
8.如权利要求1所述的中介层，其特征在于，所述第一导电柱具有与所述第二重分布层共平面的平面。
9.如权利要求1所述的中介层，其特征在于，进一步包括微凸块，所述微凸块电性连接所述第一重分布层。
10.如权利要求1所述的中介层，其特征在于，进一步包括第二导电柱，所述第二导电柱嵌设于所述硬罩层中，且介于所述第二电极层及所述第二重分布层之间。
11.一种半导体封装体，其特征在于，包括：
如权利要求1所述的中介层；
微凸块，电性连接所述第一重分布层；以及
晶片，连接所述微凸块。
12.如权利要求11所述的半导体封装体，其特征在于，所述第一电极层围绕所述第二电极层，且与所述第二电极层共轴。
13.如权利要求11所述的半导体封装体，其特征在于，所述第一导电柱通过所述第二重分布层电性连接所述第二电极层。
14.如权利要求11所述的半导体封装体，其特征在于，所述第一电极层具有与所述硬罩层共平面的平面。
15.一种制作半导体封装体的方法，其特征在于，包括：
在第一重分布层上形成有机基板；
在所述有机基板中嵌设电容，所述电容包括第一电极层、第二电极层，以及位于所述第一电极层及所述第二电极层之间的电容介电层，所述第一电极层电性连接所述第一重分布层；
在所述有机基板上形成硬罩层；
在所述硬罩层及所述有机基板中嵌设第一导电柱以电性连接所述第一重分布层；
在所述硬罩层上形成第二重分布层以电性连接所述第一导电柱及所述第二电极层；
形成微凸块以电性连接所述第一重分布层；以及
将晶片与所述微凸块连接。
16.如权利要求15所述的制作半导体封装体的方法，其特征在于，在所述有机基板中嵌设所述电容包括：
在所述有机基板中形成沟槽以暴露出所述第一重分布层；
在所述沟槽中形成所述第一电极层；
在所述第一电极层上形成所述电容介电层；以及
在所述电容介电层上形成所述第二电极层。
17.如权利要求15所述的制作半导体封装体的方法，其特征在于，在所述硬罩层及所述有机基板中嵌设所述第一导电柱包括：
通过具有孔洞的所述硬罩层蚀刻所述有机基板以形成沟槽以暴露出所述第一重分布层；以及
在所述沟槽中形成所述第一导电柱。
18.如权利要求15所述的制作半导体封装体的方法，其特征在于，进一步包括在所述硬罩层中和所述第二电极层及所述第二重分布层之间嵌设第二导电柱。
19.如权利要求15所述的制作半导体封装体的方法，其特征在于，在所述第一重分布层上形成所述有机基板之前，进一步包括在钝化层上形成所述第一重分布层，其中所述微凸块嵌设于所述钝化层中且接触所述第一重分布层。
20.如权利要求15所述的制作半导体封装体的方法，其特征在于，所述电容的所述第二电极层通过所述第二重分布层电性连接所述第一导电柱。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128955A (zh) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 中介层电路、基材上覆晶圆上覆晶片电路与利用介面电路的方法
CN114914196A (zh) * 2022-07-19 2022-08-16 武汉大学 基于芯粒概念的局部中介层2.5d扇出封装结构及工艺

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11195805B2 (en) * 2018-03-30 2021-12-07 Intel Corporation Capacitor die embedded in package substrate for providing capacitance to surface mounted die
US11189538B2 (en) * 2018-09-28 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with polyimide packaging and manufacturing method
US11610864B2 (en) * 2019-09-09 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method of forming the same
KR20220015632A (ko) * 2020-07-31 2022-02-08 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR20220067630A (ko) 2020-11-17 2022-05-25 삼성전자주식회사 반도체 패키지
US20230063343A1 (en) * 2021-08-24 2023-03-02 Texas Instruments Incorporated Multilevel package substrate device with bga pin out and coaxial signal connections
US11908838B2 (en) 2021-08-26 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Three-dimensional device structure including embedded integrated passive device and methods of making the same
FR3142602A1 (fr) * 2022-11-30 2024-05-31 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif électronique

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120133021A1 (en) * 2010-11-30 2012-05-31 Stmicroelectronics (Crolles 2) Sas Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
CN102956440A (zh) * 2011-08-26 2013-03-06 台湾积体电路制造股份有限公司 电容器及其制造方法
US20140367828A1 (en) * 2013-06-18 2014-12-18 Stmicroelectronics (Crolles 2) Sas Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device
TWM495926U (zh) * 2014-11-11 2015-02-21 Poul Chang Metal Industry Co Ltd 防盜套筒
US20150145011A1 (en) * 2010-04-28 2015-05-28 Ps4 Luxco S.A.R.L. Semiconductor device
US20150221714A1 (en) * 2014-01-31 2015-08-06 Qualcomm Incorporated Metal-insulator-metal (mim) capacitor in redistribution layer (rdl) of an integrated device
US20150250058A1 (en) * 2014-02-28 2015-09-03 Qualcomm Incorporated Integrated interposer with embedded active devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331568B1 (ko) * 2000-05-26 2002-04-06 윤종용 반도체 메모리 소자 및 그 제조방법
US7250334B2 (en) * 2004-07-31 2007-07-31 Texas Instruments Incorporated Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode
JP5089880B2 (ja) * 2005-11-30 2012-12-05 日本特殊陶業株式会社 配線基板内蔵用キャパシタ、キャパシタ内蔵配線基板及びその製造方法
US7989270B2 (en) * 2009-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
US8748284B2 (en) * 2011-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing decoupling MIM capacitor designs for interposers
US20130328167A1 (en) * 2012-06-06 2013-12-12 International Business Machines Corporation Self-aligned metal-insulator-metal (mim) capacitor
KR101405675B1 (ko) * 2012-07-20 2014-06-10 주식회사다스 스마트 카시트 및 그 제조방법
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US20150264813A1 (en) 2014-03-11 2015-09-17 United Microelectronics Corp. Chip-stack interposer structure including passive device and method for fabricating the same
US9449953B1 (en) 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150145011A1 (en) * 2010-04-28 2015-05-28 Ps4 Luxco S.A.R.L. Semiconductor device
US20120133021A1 (en) * 2010-11-30 2012-05-31 Stmicroelectronics (Crolles 2) Sas Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
CN102956440A (zh) * 2011-08-26 2013-03-06 台湾积体电路制造股份有限公司 电容器及其制造方法
US20140367828A1 (en) * 2013-06-18 2014-12-18 Stmicroelectronics (Crolles 2) Sas Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device
US20150221714A1 (en) * 2014-01-31 2015-08-06 Qualcomm Incorporated Metal-insulator-metal (mim) capacitor in redistribution layer (rdl) of an integrated device
US20150250058A1 (en) * 2014-02-28 2015-09-03 Qualcomm Incorporated Integrated interposer with embedded active devices
TWM495926U (zh) * 2014-11-11 2015-02-21 Poul Chang Metal Industry Co Ltd 防盜套筒

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128955A (zh) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 中介层电路、基材上覆晶圆上覆晶片电路与利用介面电路的方法
CN111128955B (zh) * 2018-10-31 2022-03-01 台湾积体电路制造股份有限公司 中介层电路、基材上覆晶圆上覆晶片电路与利用介面电路的方法
CN114914196A (zh) * 2022-07-19 2022-08-16 武汉大学 基于芯粒概念的局部中介层2.5d扇出封装结构及工艺

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