CN206757602U - A kind of device that multiple SPI interface standard groups are supported based on SoC - Google Patents
A kind of device that multiple SPI interface standard groups are supported based on SoC Download PDFInfo
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- CN206757602U CN206757602U CN201720583041.7U CN201720583041U CN206757602U CN 206757602 U CN206757602 U CN 206757602U CN 201720583041 U CN201720583041 U CN 201720583041U CN 206757602 U CN206757602 U CN 206757602U
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Abstract
The utility model discloses a kind of device that multiple SPI interface standard groups are supported based on SoC, inside complete programmable SoC, communicated between arm processor and field programmable gate array FPGA by AXI bus communications, field programmable gate array FPGA and ancillary equipment by SPI interface standard group；Programmable gate display one AXI protocol parsing module of FPGA indoor designs and multiple SPI controller modules at the scene, realize the communication of arm processor and peripheral SPI interface equipment；AXI protocol parsing module and each SPI controller module inside field programmable gate array FPGA are independently transmitted control signal and receiving and transmitting data signals.The utility model can design 1 AXI parsing module using logical resource unnecessary FPGA inside SoC and 4 SPI controller modules avoid the need for individually purchasing 4 SPI controller chips with the multiple external equipments of parallel deployment.
Description
Technical field
The present invention relates to integrated circuit control field, more particularly to a kind of multiple SPI interface standard groups are supported based on SoC
Apparatus and method.
Background technology
Programmable SoC (System-on-a-Chip) is integrated with arm processor (Advanced RISC Machines) entirely
The hardware of software programmable and on-site programmable gate array FPGA (Field-Programmable Gate Array) can
Programmatic.Communication mode has AXI between arm processor and on-site programmable gate array FPGA inside programmable SoC entirely
(Advanced extensible Interface) and EMIO (Extendable multiplexed I/O).
AXI (Advanced extensible Interface) is a kind of bus protocol, and the agreement is that ARM companies propose
AMBA (Advanced Microcontroller Bus Architecture) 3.0 agreements in most important part, be a kind of
Towards high-performance, high bandwidth, low latency bus on chip.Its address/control and data phase are separation, support not lining up
Data transfer, while in burst transfer, it is only necessary to first address, while the read-write data channel that separates and support
Outstanding transmission accesses and out of order access, and is more prone to carry out timing closure.AXI is a new high property in AMBA
Can agreement.AXI technologies enrich existing AMBA standard contents, meet very-high performance and the design of complicated on-chip system (SoC)
Demand.
Complete programmable SoC has redefined the possibility of embedded system, is pushed away for System Architect and software developer
Go out new solution and provide a flexible platform, while be traditional ASIC (Application
SpecificIntegrated Circuit) and SoC user provide a complete programmable alternative.Double-core ARM
Cortex-A9 processors and 28nm FPGAs that are leading, having high-performance power dissipation ratio are ingenious integrated, the work(of realization
Consumption and the far super discrete processors of performance rate and FPGA system.SoC relies on peak performance-price-power dissipation ratio, and the product turns into very
The optimal selection of multi-embedding formula application field, including small-sized honeycomb base station, multi-cam driver assistance system, industrial automation
Machine vision, medical endoscope and 4K2K ultra high-definition TVs.
At one may be programmed SoC entirely as in circuit single plate of the system control with algorithm process, programmable SoC needs same entirely
When with the device or chip communication of multiple SPI (Serial Peripheral Interface) interface standard group.Such as wireless
In the design of repeater, the entirely programmable SoC on radio frequency unit RU (Radio Unit) circuit single plate needs and 4 SPI connect
The equipment communication of mouth standard group, for example AD9370 chips are exactly the equipment of SPI interface standard group.
Only two SPI controllers on arm processor unit inside one complete programmable SoC, in RU circuit single plates
The PHY chip communication of the SPI controller and a kind of SPI interface of one of arm processor is needed to use, solves RU circuit single plates
The problem of middle Ethernet interface is inadequate.Complete programmable SoC, which only remains next SPI controller, under these conditions to use, this
Sample cannot meet the needs of may be programmed SoC needs and 4 AD9370 chip communications on a RU circuit single plate entirely.
The content of the invention
For problems of the prior art, the purpose of the present invention is one new apparatus and method of design, using complete
Arm processor and on-site programmable gate array FPGA inside programmable SoC chip, realize that programmable SoC and multiple SPI connects entirely
Mouth standard group equipment communication, and possess the parallel initialization ability to SPI interface equipment.
In order to realize foregoing invention purpose, the technical solution adopted by the present invention is：One kind supports multiple SPI to connect based on SoC
The device of mouth standard group, it is characterised in that：Including complete programmable SoC, arm processor, field programmable gate array FPGA, complete
Pass through AXI bus communications, field-programmable between arm processor and on-site programmable gate array FPGA inside programmable SoC
Gate array FPGA and ancillary equipment are communicated by SPI interface standard group；Programmable gate display FPGA indoor designs 1 at the scene
AXI protocol parsing module and 4 SPI controller modules, realize the communication of arm processor and peripheral SPI interface equipment；Scene can
AXI protocol parsing module and each SPI controller module inside programming gate array FPGA be independently transmitted control signal and
Receiving and transmitting data signals.
The address and data-signal that AXI protocol parsing module parsing arm processor is sended over by AXI buses, and handle
Signal is sent to corresponding control register or reads the data of corresponding register；
AXI protocol parsing module sets register to each SPI controller, is respectively：
WR_EABLE, arm processor can control SPI controller to send or connect to external chip by this register
Receive data.It is WR that this register, which connects signal name with SPI controller,；
TRANSMIT_REG, the data-signal that arm processor sends needs to external chip are stored in advance in this and posted
Storage；
TRANSMIT_CTRL, arm processor can control the mode of operation of SPI controller by this register；
RECEIVER_REG, the number that arm processor is received by this register reading SPI controller from external equipment
It is believed that number；
STATUS_REG, arm processor inquire about the working condition of SPI controller by this register, current to judge
Data whether can be write to SPI and the enabled SPI controller of triggering sends and receives data toward external equipment.
Further, TRANSMIT_CTRL registers include 5 control information, and they are LEN, CPOL, CPHA respectively,
MODE, CS_ENABLE；
LEN input signals configuration SPI controller once reads and writes the length of data；
The idle condition of the serial synchronization clock of CPOL input signals configuration SPI controller output；
CPHA input signals configuration SPI controller is configured to one of two kinds of different host-host protocols of selection and carries out data biography
It is defeated；
MODE input signals control the priority of SPI controller output data；
The CS signals of CS_ENABLE input signals control SPI controller output.
SPI controller module and AXI parsing modules in on-site programmable gate array FPGA pass through self-defined signal communication.
The input port of SPI controller includes signals below, and these signals communicate with AXI protocol parsing module；
1) CLK input signals are the system clock input ports of SPI controller；
2) RST input signals are the reset signals of SPI controller；
3) WR input signals are the read-write enable signals of SPI controller, when WR level redirects from low to high, are touched
Send out SPI controller start-up operation read-write data；
4) LEN input signals configuration SPI controller once reads and writes the length of data；1 byte is once read and write during LEN=0,
2 bytes are once read and write during LEN=1；
5) idle condition of the serial synchronization clock of CPOL input signals configuration SPI controller output；If CPOL=0,
The idle condition of serial synchronization clock is low level, if CPOL=1, the idle condition of serial synchronization clock is high level；
6) CPHA input signals configuration SPI controller is configured to one of two kinds of different host-host protocols of selection and carries out data
Transmission；CPHA=0, it is sampled in first hopping edge data of serial synchronization clock；If CPHA=1, in serial synchronous
Second hopping edge data of clock are sampled；
7) priority of MODE input signals control SPI controller output data, MSB is preceding during MODE=0, during MODE=1
LSB is preceding；
8) the CS signals of CS_ENABLE input signals control SPI controller output, CS outputs high electricity during CS_ENABLE=1
Flat, the state of CS output signals is low level during CS_ENABLE=0；
9) TRANSMIT_REG data signal inputs mouth, this signal are the data to be sent of SPI controller, data bit
Width is 16bit；
10) RECEIVER_REG data signal outputs mouth, this signal are the reception data of SPI controller, data bit
Width is 16bit；
11) STATUS_REG status signal outputs mouth, this signal are the status registers of SPI controller, data bit
Width is 2bit；
The output port of SPI controller includes signals below, and these signals are set with the SPI interface standard group of outside respectively
Standby communication：
12) SDI is the spi bus data-in port of SPI controller；
13) SDO is the spi bus data-out port of SPI controller；
14) SCLK is the spi bus output terminal of clock mouth of SPI controller；
15) CS is the spi bus piece selected control output port of SPI controller.
The invention also discloses a kind of method that multiple SPI interface standard groups are supported based on SoC, when device starts
Wait, arm processor is communicated by AXI protocol parsing module and SPI controller, then according to the algorithm of arm processor operation simultaneously
The equipment of the SPI interface standard group of row configuration periphery.
On RU circuit single plates after electricity, complete programmable SoC systems need the SPI interface standard group on initializing circuit plate
Equipment.It is the initialization flow of system as follows.
1.1, arm processor first passes through AXI protocol parsing module and initializes 4 SPI controllers, configures SPI controller
Mode of operation and clock frequency.
1.2：Arm processor to SPI0 controllers before data are write, it is necessary to first inquire about the work shape of SPI0 controllers
State, if SPI0 controllers are in idle condition, arm processor can transfer data to SPI0 controls by AXI parsing modules
Device processed；If SPI0 controllers are in transmission datamation state, arm processor software can skip the behaviour of SPI0 controllers
Make, perform the instruction of operation SPI1 controllers.
1.3：After data write-in SPI0 controllers, arm processor triggers SPI0 controls by AXI protocol parsing module again
The read-write enable signal of device, enabled SPI0 controllers write data into the SPI interface standard group equipment of outside.
1.4：After arm processor is completed to a write operation of SPI0 controllers, may proceed to order to SPI1, SPI2 and
SPI3 performs same processing mode；
1.5：After a write operation for having performed SPI3 controllers, arm processor software can judge each according to algorithm
All the external equipment of individual SPI controller control whether complete by initialization.
1.6：If the equipment of 4 SPI interface standard groups all complete by initialization, the software of arm processor can jump to
Etc. the state of SPI interface standard group initialization command to be received；If not initializing completion, arm processor software algorithm meeting
The initialization external equipment for performing control SPI0 controllers is jumped to, after the write operation of SPI0 controllers is completed, ARM processing
The software of device can repeat the order of the above.
The speed with the transmission of spi bus interface serial data low speed is so quickly sent using AXI protocol interface concurrent data
Spend the time difference, can be parallel initialization this 4 SPI interface standard groups equipment.Circuit single plate uses this initial method
The startup time can be made to be reduced to original a quarter.
Arm processor after power-up can be according to the SPI interface standard group outside order parallel initialization in the present invention
Equipment.This system and device individually can also lead to after equipment initialization is completed with one of SPI interface equipment
Letter, the data of write-in to external equipment or read data from external equipment.
It is flow of the arm processor to an external equipment write-in data below.
2.1：Arm processor configures the mode of operation of SPI controller by AXI parsing modules, is write into control register
Enter control signal, the interface signal of corresponding SPI controller is LEN, CPOL, CPHA, MODE, CS_ENABLE；
2.2：Arm processor writes data to be sent the TRANSMIT_REG FPDPs of SPI controller；
2.3：Arm processor inquires about whether SPI controller is in idle condition by AXI protocol parsing module, if SPI is controlled
Device processed is in idle condition, and arm processor writes data to SPI WR_EABLE registers by AXI protocol parsing module, made
Energy SPI controller writes data to external equipment；If SPI controller is not at idle condition, sentence again after waiting the scheduled time
It is disconnected；
2.4：Arm processor judges whether the write operation of external equipment is fully completed, if completing to jump to step
2.1, continue to write data to external equipment if not completing to jump to step 2.2.
It is the flow that arm processor reads data from external equipment below.
3.1：Arm processor configures the mode of operation of SPI controller by AXI parsing modules, is write into control register
Enter control signal, the interface signal of corresponding SPI controller is LEN, CPOL, CPHA, MODE, CS_ENABLE；
3.2：Arm processor writes data to be sent the TRANSMIT_REG FPDPs of SPI controller；
3.3：Arm processor inquires about whether SPI controller is in idle condition by AXI protocol parsing module, if SPI is controlled
Device processed is in idle condition, and arm processor writes data to SPI WR_EABLE registers by AXI protocol parsing module, made
Energy SPI controller writes data to external equipment；If SPI controller is not at idle condition, sentence again after waiting for a period of time
It is disconnected；
3.4：Arm processor inquires about STATUS_REG state, judges whether SPI controller completes data transmission, if
Complete, triggering read-write enable signal；If it is not complete, rejudged after waiting for a period of time；
3.5：Arm processor writes data by AXI protocol parsing module to SPI WR_EABLE registers, enables SPI
Controller sends the clock signal of a cycle, and the data that external equipment is sent write SPI controller internal register,
3.6：Arm processor inquires about STATUS_REG state, judges whether SPI controller completes data receiver, if
Complete, arm processor reads the data of the RECEIVE_REG FPDPs of SPI controller by AXI protocol parsing module, such as
Fruit is not completed, and is rejudged after waiting for a period of time；
3.7：Judge to read whether data are fully completed from external equipment, if completing to jump to step 3.1, if do not had
Completion jumps to step 3.2 and continues to read data from external equipment.
Beneficial effect：1st, the present invention solves the circuit single plate based on SoC design, because SoC is without 4 SPI controllers
Part and can not be with 4 outside SPI interface standard devices communication the problem of.2nd, the present invention possess SoC can be outer with parallel deployment 4
The ability of portion's equipment, circuit single plate can make the startup time be reduced to original a quarter using this initial method.3、
The present invention avoids the need for individually purchasing 4 SPI using logical resource unnecessary FPGA inside SoC, 4 SPI controllers of design
Controller chip.4th, the present invention reduces the startup time of circuit single plate, such as an AD9370 in wireless discharging-directly station RU veneers
Radio frequency chip needs 15 seconds by the initialization time of spi bus, therefore the startup initialization radio frequency chip of a RU circuit board
Time need 60 seconds.If using design method of the present invention, AD9370 is initialized using parallel deployment, radio frequency chip it is initial
Changing the time only needs 15 seconds.
Brief description of the drawings
Fig. 1 is the entirely programmable SoC of the embodiment of the present invention and multiple SPI interface standard group apparatus structure schematic diagrams.
Fig. 2 is the flow chart of the method initialization external equipment of the embodiment of the present invention.
Fig. 3 is the arm processor of the embodiment of the present invention and the details block diagram of SPI0 controllers communication.
Spi bus data transfer timing diagram when Fig. 4 is the CPHA=0 of the embodiment of the present invention.
Spi bus data transfer timing diagram when Fig. 5 is the CPHA=1 of the embodiment of the present invention.
Fig. 6 be the embodiment of the present invention arm processor by AXI protocol parsing module and SPI controller to external equipment
Write the flow chart of data.
Fig. 7 be the embodiment of the present invention arm processor by AXI protocol parsing module and SPI controller from external equipment
Read the flow chart of data.
Embodiment
For the ease of the understanding of those skilled in the art, the present invention is made further with reference to embodiment and accompanying drawing
It is bright.
When this system and device start, arm processor can pass through AXI protocol parsing module and SPI controller
Communication, the equipment of the SPI interface standard group for the algorithm parallel deployment periphery then run according to arm processor.
A kind of device that multiple SPI interface standard groups are supported based on SoC of the present embodiment, including programmable SoC, ARM entirely
Processor, field programmable gate array FPGA, arm processor and field programmable gate array inside complete programmable SoC
Communicated between FPGA by AXI bus communications, on-site programmable gate array FPGA and ancillary equipment by SPI interface standard group；
One AXI protocol parsing module of programmable gate array FPGA indoor design at the scene, realizes arm processor and field programmable gate
SPI controller communication inside array FPGA, AXI protocol parsing module and each SPI in on-site programmable gate array FPGA inside
Controller is all independently transmitted control signal and receiving and transmitting data signals.
The address and data-signal that AXI protocol parsing module parsing arm processor is sended over by AXI buses, and handle
Signal is sent to corresponding control register or reads the data of corresponding register.AXI protocol parsing module controls to each SPI
Device sets register, is respectively：
WR_EABLE, arm processor control SPI controller to send or connect to external chip by WR_EABLE registers
Receive data；It is WR that WR_EABLE registers, which connect signal name with SPI controller,；
TRANSMIT_REG, arm processor are stored in advance in the data-signal to external chip transmission is needed
TRANSMIT_REG registers；
TRANSMIT_CTRL, arm processor control the Working mould of SPI controller by TRANSMIT_CTRL registers
Formula；
RECEIVER_REG, arm processor read SPI controller by RECEIVER_REG registers and connect from external equipment
The data-signal received；
STATUS_REG, arm processor inquires about the working condition of SPI controller by STATUS_REG registers, to sentence
It is disconnected current whether to write data to SPI and the enabled SPI controller of triggering sends and receives data toward external equipment.
As shown in figure 1, according to the structural representation of the present embodiment, the AXI between arm processor and AXI parsing modules is total
The clock rate of line is 100M, and data bit width is 32bit.According to the algorithm of AXI protocol parsing module, received from arm processor
One 32bit parallel data needs 8 clock cycle (80ns).SPI controller inside on-site programmable gate array FPGA
It is 16bit to send data bit width, therefore SPI controls only can receive the low 16bit data that arm processor is sent.Because SPI is controlled
The traffic rate of device processed and outside SPI interface standard group chip is 10M, so SPI controller serially transfers 16bit toward AD9370
Data need 1600ns.The write order of a SPI controller is completed, it is necessary to 3 instruction cycles of AXI bus communications, ARM processing
The time of SPI interface standard groups needs is outside device parallel deployment 4：80ns*4*3=960ns ＜ 1600ns, so at ARM
Reason device can initialize 4 outside SPI interface standard group equipment simultaneously.
On RU circuit single plates after electricity, complete programmable SoC systems need the SPI interface standard group on initializing circuit plate
Equipment.It is the initialization flow of system as follows.The present apparatus and the flow of method initialization external equipment are as shown in Figure 2.
Step 1.1：Arm processor first passes through AXI protocol parsing module and initializes 4 SPI controllers, configuration SPI controls
The mode of operation and clock frequency of device.
Step 1.2：Arm processor to SPI0 controllers before data are write, it is necessary to first inquire about the work of SPI0 controllers
Make state, if SPI0 controllers are in idle condition, arm processor can transfer data to SPI by AXI parsing modules
Controller.If SPI0 controllers are in transmission datamation state, arm processor software can skip the behaviour of SPI0 controllers
Make, perform the instruction of operation SPI1 controllers.
Step 1.3：After data write-in SPI0 controllers, arm processor triggers SPI0 by AXI protocol parsing module again
The read-write enable signal of controller, enabled SPI0 controllers write data into the SPI interface standard group equipment of outside.
Step 1.4：After arm processor is completed to a write operation of SPI0 controllers, order is may proceed to SPI1,
SPI2 and SPI3 performs same processing mode；
Step 1.5：After a write operation for having performed SPI3 controllers, arm processor software can judge according to algorithm
All the external equipment of each SPI controller control whether complete by initialization.
Step 1.6：If the equipment of 4 SPI interface standard groups all complete by initialization, the software of arm processor can jump
The state of SPI interface standard group initialization command to be received such as go to；If not initializing completion, arm processor software is calculated
Method can redirect the initialization external equipment for being carried out controlling SPI0 controllers, after the write operation of SPI0 controllers is completed, ARM
The software of processor can repeat the order of the above.
The speed with the transmission of spi bus interface serial data low speed is so quickly sent using AXI protocol interface concurrent data
Spend the time difference, can be parallel initialization this 4 SPI interface standard groups equipment.Circuit single plate uses this initial method
The startup time can be made to be reduced to original a quarter.
The effect of newly-designed AXI protocol parsing module is that parsing arm processor is sent by AXI buses in the present embodiment
The address to come over and data-signal, and the base address defined according to four SPI controllers and offset address send signal to correspondingly
Control register or read the data of corresponding register.
It is respectively to the base address that 4 SPI controllers (SPI0, SPI1, SPI2, SPI3) define in AXI parsing modules
0x10,0x20,0x30,0x40, while AXI parsing module also define 5 registers to each SPI controller, and this 5 are posted
The offset address of storage is 0x0,0x1,0x2,0x3,0x4.The absolute address of register is base address plus inclined in SPI controller
Move address, absolute address=base address+offset address.
5 registers that AXI parsing modules give each independent SPI controller to define are respectively：
1：WR_EABLE, arm processor can by this register control SPI controller to external chip send or
Receive data.It is WR that this register, which connects signal name with SPI controller,；
2：TRANSMIT_REG, arm processor are stored in advance in this data-signal to external chip transmission is needed
Register.
3：TRANSMIT_CTRL, arm processor can control the mode of operation of SPI controller by this register.This
Individual register includes 5 control information, and they are LEN, CPOL, CPHA, MODE, CS_ENABLE respectively；
LEN input signals configuration SPI controller once reads and writes the length of data；
The idle condition of the serial synchronization clock of CPOL input signals configuration SPI controller output；
CPHA input signals configuration SPI controller is configured to one of two kinds of different host-host protocols of selection and carries out data biography
It is defeated；
MODE input signals control the priority of SPI controller output data；
The CS signals of CS_ENABLE input signals control SPI controller output.
4：RECEIVER_REG, arm processor read what SPI controller received from external equipment by this register
Data-signal；
5：STATUS_REG, arm processor inquire about the working condition of SPI controller by this register, to judge to work as
The preceding enabled SPI controller of data and triggering that whether can be write to SPI sends and receives data toward external equipment.
SPI controller module and AXI parsing modules in on-site programmable gate array FPGA pass through self-defined signal communication.
The input and output port of SPI controller is made up of signals below, these signals respectively with AXI protocol parsing module and outside
The equipment communication of SPI interface standard group.Fig. 3 be the present embodiment arm processor and SPI0 controllers communication details block diagram, Fig. 4
It is the sequential of the spi bus agreement of SPI controller output with Fig. 5.
1：CLK input signals are the system clock input ports of SPI controller；
2：RST input signals are the reset signals of SPI controller；
3：WR input signals are the read-write enable signals of SPI controller, when WR level redirects from low to high, are touched
Send out SPI controller start-up operation read-write data；
4：LEN input signals configuration SPI controller once reads and writes the length of data；1 byte is once read and write during LEN=0,
2 bytes are once read and write during LEN=1；
5：The idle condition of the serial synchronization clock of CPOL input signals configuration SPI controller output；If CPOL=0,
The idle condition of serial synchronization clock is low level, if CPOL=1, the idle condition of serial synchronization clock is high level；
6：CPHA input signals configuration SPI controller is configured to one of two kinds of different host-host protocols of selection and carries out data
Transmission；CPHA=0, (rise or fall) data in first hopping edge of serial synchronization clock and be sampled；If CPHA=1,
Data (are risen or fallen) in second hopping edge of serial synchronization clock to be sampled；
7：MODE input signals control the priority of SPI controller output data, and MSB is preceding during MODE=0, during MODE=1
LSB preceding,
8：The CS signals of CS_ENABLE input signals control SPI controller output, CS outputs high electricity during CS_ENABLE=1
Flat, the state of CS output signals is low level during CS_ENABLE=0；
9：TRANSMIT_REG data signal input mouths, this signal are the data to be sent of SPI controller, data bit
Width is 16bit；
10：RECEIVER_REG data signal output mouths, this signal are the reception data of SPI controller, data bit
Width is 16bit；
11：STATUS_REG status signal output mouths, this signal are the status registers of SPI controller, data bit
Width is 2bit；
12：SDI is the spi bus data-in port of SPI controller；
13：SDO is the spi bus data-out port of SPI controller；
14：SCLK is the spi bus output terminal of clock mouth of SPI controller；
15：CS is the spi bus piece selected control output port of SPI controller；
Arm processor after power-up can be according to the SPI interface mark of 4 outsides of order parallel initialization in the present embodiment
Quasi- group equipment.This system and device after equipment initialization is completed, can also individually with one of SPI interface equipment
Communication, the data of write-in to external equipment or read data from external equipment.
Fig. 6 is the flow that arm processor writes data by AXI protocol parsing module and SPI controller to external equipment
Figure.Fig. 7 is the flow chart that arm processor reads data by AXI protocol parsing module and SPI controller from external equipment.ARM
Processor passes through the AXI protocol parsing module and SPI controller module and ancillary equipment inside field programmable gate array FPGA
Communication, the equipment of the SPI interface standard group of the algorithm parallel deployment periphery of arm processor operation, arm processor also possess utilization
The ability that AXI protocol parsing module and SPI controller individually communicate with an ancillary equipment.
It is flow of the arm processor to external equipment (SPI0) write-in data below.
Step 2.1：Arm processor configures the mode of operation of SPI0 controllers by AXI parsing modules, to control register
Middle write control signal, the interface signal of corresponding SPI0 controllers is LEN, CPOL, CPHA, MODE, CS_ENABLE.
Step 2.2：Arm processor writes data to be sent the TRANSMIT_REG FPDPs of SPI controller.
Step 2.3：Arm processor inquires about SPI controller output port STATUS_REG number by AXI parsing modules
Value, if STATUS_REG=2 ' b11, represent that SPI controller is now arranged in idle condition, if STATUS_REG=2 ' b00,
Represent that SPI controls are in running order.
When SPI0 controllers are in idle condition, WR_ of the arm processor by AXI protocol parsing module to SPI0
EABLE registers first write 1 ' b0 and write 1 ' b1 again, and this register controls the read-write enable signal WR of SPI0 controllers, enable SPI0
Controller writes data to external equipment；When SPI0 controllers are not at idle condition, wait 400ns, rejudge whether
In idle condition.
Step 2.4：Arm processor judges whether the write operation of external equipment is fully completed according to algorithm, if completed
Step 2.1 is jumped to, continues to write data to external equipment if not completing to jump to step 2.2.
It is the flow that arm processor reads data from external equipment below.
3.1：Arm processor configures the mode of operation of SPI controller by AXI parsing modules, is write into control register
Enter control signal, the interface signal of corresponding SPI controller is LEN, CPOL, CPHA, MODE, CS_ENABLE；
3.2：Arm processor writes data to be sent the TRANSMIT_REG FPDPs of SPI controller, and this is pending
It is that arm processor needs to read the address signal of data from external equipment to send data；
3.3：Arm processor inquires about whether SPI controller is in idle condition by AXI protocol parsing module, if SPI is controlled
Device processed is in idle condition, and arm processor writes data to SPI WR_EABLE registers by AXI protocol parsing module, made
Energy SPI controller writes data to external equipment；If SPI controller is not at idle condition, rejudged after waiting 100ns；
3.4：Arm processor inquires about STATUS_REG state, judges whether SPI controller completes data transmission, if
Complete, triggering read-write enable signal；If it is not complete, rejudged after waiting 100ns；
3.5：Arm processor writes data by AXI protocol parsing module to SPI WR_EABLE registers, enables SPI
Controller sends the clock signal of a cycle, and the data that external equipment is sent write SPI controller internal register,
3.6：Arm processor inquires about STATUS_REG state, judges whether SPI controller completes data receiver, if
Complete, arm processor reads the data of the RECEIVE_REG FPDPs of SPI controller by AXI protocol parsing module, such as
Fruit is not completed, and is rejudged after waiting 100ns；
3.7：Judge to read whether data are fully completed from external equipment, if completing to jump to step 3.1, if do not had
Completion jumps to step 3.2 and continues to write data to external equipment.
The technological thought of embodiment above only to illustrate the invention, it is impossible to protection scope of the present invention is limited with this, it is all
It is any change for being done on the basis of technical scheme according to technological thought proposed by the present invention, each falls within present invention protection model
Within enclosing.
Claims (6)
- A kind of 1. device that multiple SPI interface standard groups are supported based on SoC, it is characterised in that：At complete programmable SoC, ARM Device, field programmable gate array FPGA are managed, arm processor and field programmable gate array FPGA inside complete programmable SoC Between communicated by AXI bus communications, field programmable gate array FPGA and ancillary equipment by SPI interface standard group；Existing One AXI protocol parsing module of field programmable gate array FPGA indoor designs and 4 SPI controller modules, realize arm processor With the communication of peripheral SPI interface equipment, AXI protocol parsing module and each SPI controls inside field programmable gate array FPGA Device module processed is all independently transmitted control signal and receiving and transmitting data signals.
- 2. the device according to claim 1 that multiple SPI interface standard groups are supported based on SoC, it is characterised in that：AXI is assisted The view parsing module address that is sended over by AXI buses of parsing arm processor and data-signal, and corresponding to sending signal to Control register or the data for reading corresponding register.
- 3. the device according to claim 2 that multiple SPI interface standard groups are supported based on SoC, it is characterised in that：AXI protocol parsing module sets register to each SPI controller, is respectively：WR_EABLE, arm processor control SPI controller to send or receive number to external chip by WR_EABLE registers According to；It is WR that WR_EABLE registers, which connect signal name with SPI controller,；TRANSMIT_REG, arm processor are stored in advance in TRANSMIT_ the data-signal to external chip transmission is needed REG registers；TRANSMIT_CTRL, arm processor control the mode of operation of SPI controller by TRANSMIT_CTRL registers；RECEIVER_REG, arm processor read SPI controller by RECEIVER_REG registers and received from external equipment Data-signal；STATUS_REG, arm processor inquire about the working condition of SPI controller by STATUS_REG registers, to judge to work as It is preceding whether to trigger enabled SPI controller and send and receive data toward external equipment.
- 4. the device according to claim 3 that multiple SPI interface standard groups are supported based on SoC, it is characterised in that： TRANSMIT_CTRL registers include 5 control information, are LEN, CPOL, CPHA, MODE, CS_ENABLE respectively；LEN input signals configuration SPI controller once reads and writes the length of data；The idle condition of the serial synchronization clock of CPOL input signals configuration SPI controller output；CPHA input signals configuration SPI controller, which is configured to one of two kinds of different host-host protocols of selection, to carry out data transmission；MODE input signals control the priority of SPI controller output data；The CS signals of CS_ENABLE input signals control SPI controller output.
- 5. existed according to any described device that multiple SPI interface standard groups are supported based on SoC, its feature in Claims 1-4 In：The input port of SPI controller includes signals below, and these signals communicate with AXI protocol parsing module；1) CLK input signals are the system clock input ports of SPI controller；2) RST input signals are the reset signals of SPI controller；3) WR input signals are the read-write enable signals of SPI controller；4) LEN input signals configuration SPI controller once reads and writes the length of data；5) idle condition of the serial synchronization clock of CPOL input signals configuration SPI controller output；6) CPHA input signals configuration SPI controller is configured to one of two kinds of different host-host protocols of selection and carries out data biography It is defeated；7) priority of MODE input signals control SPI controller output data；8) the CS signals of CS_ENABLE input signals control SPI controller output；9) TRANSMIT_REG data signal inputs mouth；10) RECEIVER_REG data signal outputs mouth；11) STATUS_REG status signal outputs mouth；The output port of SPI controller includes signals below, and equipment of these signals respectively with the SPI interface standard group of outside is led to Letter：1) SDI is the spi bus data-in port of SPI controller；2) SDO is the spi bus data-out port of SPI controller；3) SCLK is the spi bus output terminal of clock mouth of SPI controller；4) CS is the spi bus piece selected control output port of SPI controller.
- 6. existed according to any described device that multiple SPI interface standard groups are supported based on SoC, its feature in Claims 1-4 In：Arm processor is by the AXI protocol parsing module inside field programmable gate array FPGA and SPI controller module and outside Peripheral equipment communicates, and the equipment of the SPI interface standard group of the algorithm parallel deployment periphery of arm processor operation, arm processor also has The standby function of individually being communicated with an ancillary equipment using AXI protocol parsing module and SPI controller.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110781117A (en) * | 2019-09-12 | 2020-02-11 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN110795382A (en) * | 2019-10-09 | 2020-02-14 | 广东高云半导体科技股份有限公司 | Universal asynchronous receiving and transmitting transmitter based on FPGA and system on chip |
| CN112765079A (en) * | 2021-01-20 | 2021-05-07 | 四川长虹电器股份有限公司 | SPI bus control method suitable for various different devices |
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2017
- 2017-05-24 CN CN201720583041.7U patent/CN206757602U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110781117A (en) * | 2019-09-12 | 2020-02-11 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN110781117B (en) * | 2019-09-12 | 2020-11-20 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN110795382A (en) * | 2019-10-09 | 2020-02-14 | 广东高云半导体科技股份有限公司 | Universal asynchronous receiving and transmitting transmitter based on FPGA and system on chip |
| CN112765079A (en) * | 2021-01-20 | 2021-05-07 | 四川长虹电器股份有限公司 | SPI bus control method suitable for various different devices |
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