CN108227814B - Source follower circuit - Google Patents
Source follower circuit Download PDFInfo
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- CN108227814B CN108227814B CN201711382679.5A CN201711382679A CN108227814B CN 108227814 B CN108227814 B CN 108227814B CN 201711382679 A CN201711382679 A CN 201711382679A CN 108227814 B CN108227814 B CN 108227814B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention relates to a source follower circuit.A cascode mirror image circuit and a cascode circuit are added, a threshold voltage is superposed on a reference voltage, the output voltage does not change along with the change of temperature and process angle, and the deviation is very small. The invention compensates the output voltage of the traditional source follower circuit, solves the defect that the output voltage of the traditional source follower circuit can change along with the changes of temperature and process angle, and improves the characteristic of the output voltage. The circuit of the invention is simple, and the area overhead is basically negligible.
Description
Technical Field
The invention relates to a source follower circuit.
Background
The conventional CMOS source follower circuit, as shown in fig. 1, includes an intrinsic MOS transistor M4 having a drain connected to a power supply voltage VDD, a gate connected to a reference voltage VREF, and a source corresponding to an output voltage VOUT and connected to a bias current source I3. The output voltage VOUT = VREF — Vth, and VOUT ≈ VREF because the threshold voltage Vth of the intrinsic MOS transistor ≈ 0. However, since Vth varies with temperature and process corner, VOUT also varies with temperature and process corner, and a large deviation is generated: the maximum deviation is +/-0.15V-0.2V when the temperature and the process angle are different.
Disclosure of Invention
The invention aims to provide a source follower circuit which can generate more accurate output voltage which does not change along with temperature and process angle.
In order to achieve the above object, the present invention provides a source follower circuit, which includes N-type MOS transistors M0 and M1, intrinsic MOS transistors M2, M3 and M4, bias current sources I0, I1, I2 and I3, and a resistor R0;
the drain electrode of the M2 tube, the input end of the bias current source I0 and the drain electrode of the M4 tube are respectively connected with a power supply voltage VDD;
the sources of the M0 tube and the M1 tube are connected with the input end of a bias current source I1, and the gate of the M0 tube is connected with a reference voltage VREF; the drain electrode of the M0 tube is connected with the source electrode of the M2 tube; the grid and the drain of the M1 tube are connected with the grid of the M2 tube and the source of the M3 tube;
the output end of the bias current source I0 is connected with the drain electrode of the M3 tube; the output end of the bias current source I0 is also connected with the grid of the M4 tube, the grid of the M3 tube and the input end of the bias current source I2 through a resistor R0; the output ends of the bias current sources I1, I2 and I3 are grounded;
the source of the M4 transistor is connected to the input terminal of the bias current source I3, and VOUT = VREF corresponding to the output voltage VOUT.
Preferably, the bias current sources I0, I1, I2 correspond to current values of I0、I1、I2，I1=(I0-I2)*2。
Preferably, the conduction currents of the M0 tube and the M1 tube are equal and are both equal to I1/2。
Preferably, the M0 tube and the M1 tube form a cascode structure through the M2 tube;
wherein VA = VREF; the voltage VA is the voltage of the node where the gate and the drain of the M1 transistor, the gate of the M2 transistor, and the source of the M3 transistor are connected.
Preferably, the M3 tube is operated in the saturation zone;
R0*I2>vth, and R0*I2<VDD-VB；
VB=VA+Vth；VOUT=VB-Vth=VA=VREF；
Wherein the resistance value of the resistor R0 is R0(ii) a The bias current source I2 has a current value of I2；
The voltage VB is the voltage of the node of the resistor connected with the gate of the M4 tube, the gate of the M3 tube and the input end of the bias current source I2.
Compared with the prior art, the invention has the advantages that:
aiming at the defect that the output voltage of the traditional source follower circuit changes along with the changes of temperature and process angle, the invention is optimized. The output voltage of the traditional source follower circuit is the reference voltage minus a threshold voltage, so that the temperature and process corner characteristics are not good.
According to the invention, a cascode mirror image circuit and a cascode circuit are added, and a threshold voltage is superposed on a reference voltage, so that the output voltage of the traditional source follower circuit is compensated. The output voltage is not changed along with the change of temperature and process angle, and the deviation is small.
The invention compensates the deviation of temperature and process angle, is hardly influenced by temperature and process angle, and only introduces a small deviation caused by mismatching of MOS devices: the deviation is about +/-0.03V. The invention has simple circuit and basically negligible area overhead.
Drawings
FIG. 1 is a schematic diagram of a conventional source follower circuit;
fig. 2 is a schematic diagram of a source follower circuit of the present invention.
Detailed Description
The invention provides a relatively accurate source follower circuit, and the output voltage of the source follower circuit does not change along with the change of temperature and process angle. In the source follower circuit shown in fig. 2, M0 and M1 are N-type MOS transistors; m2, M3 and M4 are intrinsic (native) MOS tubes, and the threshold voltage is close to 0V; i0, I1, I2 and I3 are bias current sources, and the corresponding current values are I0、I1、I2、I3(ii) a A resistor R0 with a resistance of R0。
The sources of M0 and M1 are connected with the input end of I1, and the output end of I1 is grounded; the gate of M0 is connected to reference voltage VREF; the drain of M0 is connected to the source of M2, corresponding to voltage VD; the grid electrode and the drain electrode of the M1 are connected with the grid electrode of the M2 and the source electrode of the M3 and correspond to a voltage VA; the drain of M2 is connected to supply voltage VDD.
The input end of the I0 is connected with a power supply voltage VDD, and the output end is connected with the drain electrode of the M3 and corresponds to a voltage VC; the output end of the I0 is also connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the grid of the M4, the grid of the M3 and the input end of the I2 and corresponds to a voltage VB; the output of I2 is connected to ground. The drain electrode of the M4 is connected with a power supply voltage VDD, and the source electrode of the M4 corresponds to the output voltage VOUT and is connected with the input end of the I3; the output of I3 is connected to ground.
Designing the value of the corresponding bias current source: i is1=(I0-I2) 2, make the conduction currents of M0 and M1 equal, both equal to I1/2. And adding a M2 tube to form a cascode structure of M0 and M1, and ensuring VA = VREF.
According to the value of I2, selecting proper R0 to make M3 work in saturation region, namely R0*I2>-Vth, and R0*I2<VDD-VB. Thus, VB = VA + Vth. And Vth is the threshold voltage of the intrinsic MOS tube.
It was deduced that VOUT = VB-Vth = VA = VREF. Therefore, the output voltage VOUT is not changed along with the temperature and the process angle, and is accurate.
In conclusion, the invention optimizes the traditional source follower circuit, overcomes the defect that the output voltage of the traditional source follower circuit can change along with the changes of temperature and process angle, and improves the characteristic of the output voltage. The circuit of the invention is simple and the area overhead is negligible.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (5)
1. A source follower circuit is characterized by comprising N-type MOS tubes M0 and M1, intrinsic MOS tubes M2, M3 and M4, bias current sources I0, I1, I2 and I3 and a resistor R0;
the drain electrode of the M2 tube, the input end of the bias current source I0 and the drain electrode of the M4 tube are respectively connected with a power supply voltage VDD;
the sources of the M0 tube and the M1 tube are connected with the input end of a bias current source I1, and the gate of the M0 tube is connected with a reference voltage VREF; the drain electrode of the M0 tube is connected with the source electrode of the M2 tube; the grid and the drain of the M1 tube are connected with the grid of the M2 tube and the source of the M3 tube;
the output end of the bias current source I0 is connected with the drain electrode of the M3 tube; the output end of the bias current source I0 is also connected with the grid of the M4 tube, the grid of the M3 tube and the input end of the bias current source I2 through a resistor R0; the output ends of the bias current sources I1, I2 and I3 are grounded;
the source of the M4 transistor is connected to the input terminal of the bias current source I3, and VOUT = VREF corresponding to the output voltage VOUT.
2. The source follower circuit of claim 1,
the bias current sources I0, I1 and I2 correspond to current values I0、I1、I2，I1=(I0-I2)*2。
3. The source follower circuit of claim 2,
the conduction currents of the M0 tube and the M1 tube are equal and are both equal to I1/2。
4. The source follower circuit of claim 1 or 3,
forming a cascode structure by using an M0 tube and an M1 tube through an M2 tube;
wherein VA = VREF; the voltage VA is the voltage of the node where the gate and the drain of the M1 transistor, the gate of the M2 transistor, and the source of the M3 transistor are connected.
5. The source follower circuit of claim 4,
the M3 tube was operated in the saturation region;
R0*I2>vth, and R0*I2<VDD-VB；
VB=VA+Vth；VOUT=VB-Vth=VA=VREF；
Wherein the resistance value of the resistor R0 is R0(ii) a The bias current source I2 has a current value of I2；
The voltage VB is the voltage of a node of the resistor connected with the grid electrode of the M4 tube, the grid electrode of the M3 tube and the input end of the bias current source I2; and Vth is the threshold voltage of the intrinsic MOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711382679.5A CN108227814B (en) | 2017-12-20 | 2017-12-20 | Source follower circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711382679.5A CN108227814B (en) | 2017-12-20 | 2017-12-20 | Source follower circuit |
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| Publication Number | Publication Date |
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| CN108227814A CN108227814A (en) | 2018-06-29 |
| CN108227814B true CN108227814B (en) | 2020-02-04 |
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| CN111766506A (en) * | 2020-07-03 | 2020-10-13 | 福建师范大学 | Sensor integrated circuit for detecting CMOS process deviation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100452647C (en) * | 2007-03-23 | 2009-01-14 | 清华大学 | Voltage follower of small output resistance, large output amplitude |
| JP2010178148A (en) * | 2009-01-30 | 2010-08-12 | Hitachi Kokusai Electric Inc | Buffer circuit |
| US7852154B2 (en) * | 2009-02-23 | 2010-12-14 | Analog Devices, Inc. | High precision follower device with zero power, zero noise slew enhancement circuit |
| CN203406849U (en) * | 2013-08-29 | 2014-01-22 | 苏州苏尔达信息科技有限公司 | Buffer circuit with high speed and high precision |
| CN104090626B (en) * | 2014-07-03 | 2016-04-27 | 电子科技大学 | A kind of high precision multi-output voltages impact damper |
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Address after: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Patentee after: Praran semiconductor (Shanghai) Co.,Ltd. Address before: 201210 No. 406, No. 560, midsummer Road, Shanghai Free Trade Zone, Shanghai, Pudong New Area Patentee before: PUYA SEMICONDUCTOR (SHANGHAI) Co.,Ltd. |