CN108197074A - Fast Fourier Transform (FFT) FFT data processing method and processing device - Google Patents
Fast Fourier Transform (FFT) FFT data processing method and processing device Download PDFInfo
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Abstract
The present invention provides a kind of Fast Fourier Transform (FFT) FFT data processing method and processing device, method includes：Sample points divided by baseline sample are counted, obtain scheduling factor M；If scheduling factor M is less than or equal to 1, at least one butterfly processing element is chosen in computing module, FFT butterfly computations are carried out to sample point simultaneously, obtain butterfly computation result；If scheduling factor M be more than 1 and sample points on the basis of sample points 2NTimes, it recycles whole butterfly processing elements in computing module and carries out FFT butterfly computations, until whole sample points are calculated and finished, obtain first order operation result；First order operation result is stored in corresponding memory respectively；Based on first order operation result, the whole butterfly processing elements recycled in computing module carry out FFT butterfly computations, until obtaining N+1 grades of butterfly computation results, alleviate the problem of data dispatch structure application environment of the prior art is single, flexibility is low, achieved the effect that improve the flexibility of data dispatch structure.
Description
Technical field
The present invention relates to technical field of data processing, more particularly, to a kind of Fast Fourier Transform (FFT) FFT data processing side
Method and device.
Background technology
Fast Fourier Transform (FFT) (Fast Fourier Transformation, FFT) is that the classical of Digital Signal Processing is calculated
Method can effectively reduce the operand of big points data.In current FFT is calculated, FFT, which calculates structure, mainly fortune in situ
Calculate structure and pipeline organization.It is preferential to use operating structure in situ in the case that but calculating speed few in computing resource requirement is low.
Pipeline organization is preferentially used in the case where calculating speed is required more than high but computing resource.In the prior art, sample is being calculated
During the more FFT of points, according to calculating speed requirement and computing resource constraints, pass through operating structure in situ and pipeline organization
To construct the ultra long FFT operating structure of a segmentation.But this posttectonic FFT operating structures are just for a certain kind
Calculating speed requires and computing resource constraints, if computing resource constraint condition change, this posttectonic FFT operations
Structure does not just apply to.Therefore, result in that data dispatch structure application environment in the prior art is single, flexibility is low
Problem.
Invention content
In view of this, the purpose of the present invention is to provide a kind of Fast Fourier Transform (FFT) FFT data processing method and processing device,
To alleviate the technical issues of data dispatch structure application environment in the prior art is single, flexibility is low.
In a first aspect, an embodiment of the present invention provides a kind of Fast Fourier Transform (FFT) FFT data processing method, including：
The sample points of the FFT divided by preset baseline sample are counted, obtain scheduling factor M, the M>0, it is described
Baseline sample points are determined according to the operand of preset computing module；
If the scheduling factor M is less than or equal to 1, at least one butterfly processing element is chosen in the computing module
FFT butterfly computations are carried out to the sample point of the FFT simultaneously, obtain butterfly computation as a result, the computing module includes multiple institutes
Butterfly processing element is stated, each butterfly processing element includes：One memory and two two butterfly operation modules of base；
If the scheduling factor M be more than 1 and the sample points be the baseline sample points 2NTimes, N is positive integer,
It recycles whole butterfly processing elements in the computing module and carries out FFT butterfly computations, until all samples of the FFT
This point is calculated and is finished, and obtains first order operation result, and the first order operation result is stored in the corresponding butterfly respectively
The memory of arithmetic element；
Based on the first order operation result, recycle the whole butterfly processing element in the computing module into
Row FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
With reference to first aspect, an embodiment of the present invention provides the first possible embodiment of first aspect, wherein, institute
If stating the scheduling factor M less than or equal to 1, it is right simultaneously that at least one butterfly processing element is chosen in the computing module
The sample point of the FFT carries out FFT butterfly computations, obtain butterfly computation as a result, including：
When the scheduling factor M is less than 1, memory capacity and the sample point of the FFT are chosen in the computing module
The matched butterfly processing element of number is carried out at the same time FFT butterfly computations, obtains the butterfly computation result；
When the scheduling factor M is equal to 1, using all the butterfly processing element is carried out at the same time in the computing module
FFT butterfly computations obtain the butterfly computation result.
With reference to first aspect, an embodiment of the present invention provides second of possible embodiment of first aspect, wherein, institute
It states when the scheduling factor M is less than 1, choose memory capacity in the computing module matches with the sample points of the FFT
Butterfly processing element be carried out at the same time FFT butterfly computations, obtain the butterfly computation as a result, including：
By the sample points of the FFT divided by the memory capacity, obtain for calculate the FFT sample point butterfly
The destination number of arithmetic element；
The destination number butterfly processing element is chosen in the computing module；
In the memory in the butterfly processing element that the sample point write-in of the FFT is chosen；
Read the sample of the FFT simultaneously from the first output port in the memory of selection and second output terminal mouth
Point；
FFT butterfly computations are carried out respectively to the sample point read from each memory, obtain the butterfly
Operation result.
With reference to first aspect, an embodiment of the present invention provides the third possible embodiment of first aspect, wherein, institute
It states when the scheduling factor M is equal to 1, using all the butterfly processing element is carried out at the same time FFT butterflies in the computing module
Shape operation, obtain the butterfly computation as a result, including：
The sample point of the FFT is written in the whole memory in the computing module；
The sample point of the FFT is read simultaneously from the first output port and second output terminal mouth of each memory,
Obtain output sample；
FFT butterfly computations are carried out to the output sample read from each memory, obtain the butterfly fortune
Calculate result.
With reference to first aspect, an embodiment of the present invention provides the 4th kind of possible embodiment of first aspect, wherein, institute
State and FFT butterfly computations carried out to the output sample that is read from each memory, obtain the butterfly computation as a result,
Including：
In two butterfly operation module of base corresponding with first output port, to it is described output sample and with it is described defeated
Go out corresponding preset first twiddle factor of sample and carry out two butterfly-unit of base, obtain first port operation result, described first
Twiddle factor is determined according to baseline sample points；
In two butterfly operation module of base corresponding with the second output terminal mouth, to it is described output sample and with it is described defeated
Go out corresponding first twiddle factor of sample and carry out two butterfly-unit of base, obtain second port operation result；
The first port operation result and the second port operation result of each memory form the butterfly
Shape operation result.
With reference to first aspect, an embodiment of the present invention provides the 5th kind of possible embodiment of first aspect, wherein, institute
It states the whole based on the first order operation result, recycled in the computing module butterfly processing element and carries out FFT
Butterfly computation, until obtain N+1 grades of butterfly computations as a result, including：
Sample points in the first order operation result are divided into 2NA operation group；
Using all two butterfly operation modules of base, by 2NL-th operation group and L+1 in a operation group
A operation group progress FFT butterfly computations, wherein L=1,3 ..., 2N- 1, second level operation result is obtained, until obtaining described
N+1 grades of butterfly computation results.
Second aspect, the embodiment of the present invention also provide a kind of Fast Fourier Transform (FFT) FFT data processing unit, including：It removes
With module, choose module, the first computing module and the second computing module；
Described divided by module, for by the sample points of the FFT divided by preset baseline sample points, obtain scheduling because
Sub- M, the M>0, the baseline sample points are determined according to the operand of preset computing module；
The selection module, if for the scheduling factor M be less than or equal to 1, chosen in the computing module to
A few butterfly processing element carries out FFT butterfly computations to the sample point of the FFT simultaneously, obtains butterfly computation as a result, described
Computing module includes multiple butterfly processing elements, and each butterfly processing element includes：One memory and two bases
Two butterfly operation modules；
First computing module, if for the scheduling factor M be more than 1 and the sample points be the baseline sample
The 2 of pointsNTimes, N is positive integer, recycles whole butterfly processing elements in the computing module and carries out FFT butterfly fortune
It calculates, until the sample point of whole FFT is calculated and finished, obtains first order operation result；By the first order operation result
It is stored in the memory of the corresponding butterfly processing element respectively；
Second computing module for being based on the first order operation result, is recycled in the computing module
All the butterfly processing element carries out FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
With reference to second aspect, an embodiment of the present invention provides the first possible embodiment of second aspect, wherein, institute
Selection module is stated to include：First selection unit and the first arithmetic element；
First selection unit, for when the scheduling factor M is less than 1, storage to be chosen in the computing module
The matched butterfly processing element of sample points of capacity and the FFT is carried out at the same time FFT butterfly computations, obtains the butterfly computation
As a result；
First arithmetic element, for when the scheduling factor M is equal to 1, utilizing institutes whole in the computing module
It states butterfly processing element and is carried out at the same time FFT butterfly computations, obtain the butterfly computation result.
With reference to second aspect, an embodiment of the present invention provides second of possible embodiment of second aspect, wherein, institute
The second computing module is stated to include：Division unit and the second arithmetic element；
The division unit, for the sample points in the first order operation result to be divided into 2NA operation group；
Second arithmetic element, for utilizing all two butterfly operation modules of base, by 2NA operation group
Middle l-th operation group and the L+1 operation group progress FFT butterfly computation, wherein L=1,3 ..., 2N- 1, obtain the second level
Operation result, until obtaining the N+1 grades of butterfly computation results.
The third aspect, the embodiment of the present invention also provide a kind of meter of non-volatile program code that can perform with processor
Calculation machine readable medium, said program code make the processor perform described any the method for first aspect.
The embodiment of the present invention brings following advantageous effect：The Fast Fourier Transform (FFT) provided in an embodiment of the present invention
FFT data processing method includes：The sample points of the FFT divided by preset baseline sample are counted, obtain scheduling factor M,
The M>0, the baseline sample points are determined according to the operand of preset computing module；If the scheduling factor M be less than or
Person is equal to 1, and at least one butterfly processing element is chosen in the computing module and carries out FFT to the sample point of the FFT simultaneously
Butterfly computation obtains butterfly computation as a result, the computing module includes multiple butterfly processing elements, each butterfly fortune
Unit is calculated to include：One memory and two two butterfly operation modules of base；If the scheduling factor M is more than 1 and the sample point
Number is the 2 of baseline sample pointsNTimes, N is positive integer, recycles whole butterfly computation lists in the computing module
Member carries out FFT butterfly computations, until the sample point of whole FFT is calculated and finished, obtains first order operation result；By described in
First order operation result is stored in the memory of the corresponding butterfly processing element respectively；Based on the first order operation result,
The whole butterfly processing element recycled in the computing module carries out FFT butterfly computations, until obtaining N+1 grades of butterflies
Shape operation result.
So after the sample point of FFT of FFT butterfly computations to be carried out is got, the Fast Fourier Transform (FFT) FFT numbers
The sample points of the FFT divided by preset baseline sample are counted according to processing method, scheduling factor M are obtained, then according to institute
It states the value range of scheduling factor M and carries out FFT butterfly computations to dispatch the sample point of the FFT, if the scheduling factor M is less than
Or equal to 1, at least one butterfly processing element is chosen in the computing module, the sample point of the FFT is carried out simultaneously
FFT butterfly computations obtain butterfly computation as a result, at this moment only carrying out primary whole FFT butterfly computations just foot on computing module
It is much of that.If the scheduling factor M be more than 1 and the sample points be the baseline sample points 2NTimes, it recycles described
All the butterfly processing element carries out FFT butterfly computations in computing module, until all the sample point of the FFT has been calculated
Finish, obtain first order operation result；The first order operation result is stored in depositing for the corresponding butterfly processing element respectively
Reservoir；The whole butterfly processing element recycled in the computing module carries out FFT butterfly computations, until obtaining N+
1 grade of butterfly computation result.So when the scheduling factor M be more than 1 and the sample points be the baseline sample points 2N
Times when, to recycle in the computing module all butterfly processing elements and carry out FFT butterfly computations, until described in whole
The sample point of FFT, which calculates, to be finished, and obtains first order operation result, then again using obtained first order operation result as input
Data, the whole butterfly processing element recycled in the computing module carries out FFT butterfly computations, until obtaining N+
1 grade of butterfly computation is as a result, the N+1 grades of butterfly computation results finally obtained are only FFT butterflies fortune corresponding with the sample point of FFT
Calculate result.So even if only providing a kind of computing module (data dispatch structure), method can be according to the sample points of FFT
With the computing resource (computing resource and baseline sample points are corresponding) of computing module, data are dispatched for FFT butterfly computations, no matter
The sample points of FFT are more or few, can use a kind of this computing module, while taken into account calculating speed problem and calculating
Resource constraint problem ensure that diversity and the flexibility of data dispatch structure application environment, avoid due to data dispatch structure
Can only meet data dispatch structure application environment caused by the requirement of a certain calculating speed and computing resource constraints it is single,
Therefore the problem of flexibility is low, alleviates that data dispatch structure application environment in the prior art is single, flexibility is low
Problem has reached the diversity for improving data dispatch structure application environment and the skill for the flexibility for improving data dispatch structure
Art effect.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that being understood by implementing the present invention.The purpose of the present invention and other advantages are in specification, claims
And specifically noted structure is realized and is obtained in attached drawing.
For the above objects, features and advantages of the present invention is enable to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution of the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in being described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is the flow chart of Fast Fourier Transform (FFT) FFT data processing method provided in an embodiment of the present invention；
Fig. 2 is the flow chart of step S102 in Fig. 1；
Fig. 3 is the flow chart of step S201 in Fig. 2；
Fig. 4 is the flow chart of step S202 in Fig. 2；
Fig. 5 is the structure diagram of computing module provided in an embodiment of the present invention.
Specific embodiment
Purpose, technical scheme and advantage to make the embodiment of the present invention are clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiment be part of the embodiment of the present invention rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Lower all other embodiments obtained, shall fall within the protection scope of the present invention.
At present, Fast Fourier Transform (FFT) (Fast Fourier Transformation, FFT) is Digital Signal Processing
Classic algorithm can effectively reduce the operand of big points data.In current FFT is calculated, FFT, which calculates structure, mainly to be had
Operating structure in situ and pipeline organization.It is preferential to use fortune in situ in the case that but calculating speed few in computing resource requirement is low
Calculate structure.Pipeline organization is preferentially used in the case where calculating speed is required more than high but computing resource.In the prior art, it is counting
When calculating the FFT more than sample points, according to calculating speed requirement and computing resource constraints, pass through operating structure in situ and flowing water
Cable architecture come construct one segmentation ultra long FFT operating structure.But this posttectonic FFT operating structures just for
A certain calculating speed requirement and computing resource constraints, it is this posttectonic if computing resource constraint condition change
FFT operating structures just do not apply to.Therefore, it is single, clever to result in data dispatch structure application environment in the prior art
The problem of activity is low, based on this, a kind of Fast Fourier Transform (FFT) FFT data processing method provided in an embodiment of the present invention and dress
It puts, the problem of data dispatch structure application environment in the prior art is single, flexibility is low can be alleviated, reached raising
The technique effect of the flexibility of data dispatch structure.
For ease of understanding the present embodiment, first to a kind of Fast Fourier Transform (FFT) disclosed in the embodiment of the present invention
FFT data processing method describes in detail, as shown in Figure 1, the Fast Fourier Transform (FFT) FFT data processing method can wrap
Include following steps.
Step S101 counts the sample points of the FFT divided by preset baseline sample, obtains scheduling factor M, described
M>0, the baseline sample points are determined according to the operand of preset computing module.
Illustratively, the baseline sample points can be 512.For example, when the sample points of the FFT are 256
When, then scheduling factor M is 0.5.When the sample points of the FFT are 512, then scheduling factor M is 1.When the sample of the FFT
It counts when being 1024, then scheduling factor M is 2.
Step S102 if the scheduling factor M is less than or equal to 1, chooses at least one butterfly in the computing module
Shape arithmetic element carries out FFT butterfly computations to the sample point of the FFT simultaneously, obtains butterfly computation as a result, the computing module
Including multiple butterfly processing elements, each butterfly processing element includes：One memory and two two butterfly of base fortune
Calculate module.
Illustratively, the computing module can include 4 butterfly processing elements, each butterfly processing element
It can include：One memory and two two butterfly operation modules of base, the memory can be dual-ported memories, described double
Port store includes：First output port and second output terminal mouth, first output port are correspondingly connected with two butterfly of base
Shape computing module, the second output terminal mouth are correspondingly connected with two butterfly operation module of base.Each butterfly processing element
All it is independent from each other.The memory capacity of each dual-ported memory can be the sample point of 128 FFT.
Illustratively, as shown in Fig. 2, step S102 may comprise steps of.
Step S201 when the scheduling factor M is less than 1, chooses memory capacity and the FFT in the computing module
The matched butterfly processing element of sample points be carried out at the same time FFT butterfly computations, obtain the butterfly computation result.
Illustratively, by taking the computing module includes 4 butterfly processing elements as an example, each butterfly computation
The memory capacity of memory in unit can be the sample point of 128 FFT, then can be at 4 when scheduling factor M is 0.5
2 butterfly processing elements are chosen in the butterfly processing element and are carried out at the same time FFT butterfly computations, obtain the butterfly computation knot
Fruit.2 butterfly processing elements being selected are exactly and 256 matched butterfly processing element of the sample points of FFT.Work as scheduling factor
When M is 0.75, then 3 butterfly processing elements can be chosen in 4 butterfly processing elements and are carried out at the same time FFT butterflies fortune
It calculates, obtains the butterfly computation result.3 butterfly processing elements being selected are exactly and 384 matched butterfly of the sample points of FFT
Shape arithmetic element.
Illustratively, as shown in figure 3, step S201 may comprise steps of.
Step S301 by the sample points of the FFT divided by the memory capacity, obtains the sample for calculating the FFT
The destination number of the butterfly processing element of this point.
Illustratively, it when the sample points of the FFT are 384, and the memory capacity is 128, is then available for
The destination number for calculating the butterfly processing element of the sample point of the FFT is 3.It is described when the sample points of the FFT is 256
When memory capacity is 128, then the destination number for being available for calculating the butterfly processing element of the sample point of the FFT is 2.
Step S302 chooses the destination number butterfly processing element in the computing module.
Illustratively, when destination number is 3, then destination number 3 can be chosen in 4 butterfly processing elements
Butterfly processing element.When destination number is 2, then 2 butterflies of destination number can be chosen in 4 butterfly processing elements
Arithmetic element.
Step S303, will be in the memory in the butterfly processing element of the sample point write-in selection of the FFT.
Illustratively, when the sample points of the FFT are 384, by 3 butterflies of the sample point write-in selection of the FFT
In the memory in shape arithmetic element.
Step S304, from described in the first output port in the memory of selection and the reading simultaneously of second output terminal mouth
The sample point of FFT.
Step S305 carries out FFT butterfly computations to the sample point read from each memory, obtains respectively
The butterfly computation result.
Illustratively, for each butterfly processing element, the butterfly computation result that butterfly processing element is obtained is former
In the storage to the memory of the butterfly processing element of position.
Step S202 when the scheduling factor M is equal to 1, utilizes the butterfly computation lists whole in the computing module
Member is carried out at the same time FFT butterfly computations, obtains the butterfly computation result.
Illustratively, as shown in figure 4, step S202 may comprise steps of.
The sample point of the FFT is written in the whole memory in the computing module step S401.
Illustratively, when the sample points of the FFT are 512, the computing module is written into the sample point of the FFT
In interior all 4 memories.
Step S402 reads the FFT simultaneously from the first output port and second output terminal mouth of each memory
Sample point, obtain output sample.
Step S403 carries out FFT butterfly computations to the output sample read from each memory, obtains institute
State butterfly computation result.
Illustratively, for each butterfly processing element, the butterfly computation result that butterfly processing element is obtained is former
In the storage to the memory of the butterfly processing element of position.
Illustratively, step S403 may comprise steps of.
Step S501, in two butterfly operation module of base corresponding with first output port, to the output sample
Preset first twiddle factor corresponding with the output sample carries out two butterfly-unit of base, obtains first port operation knot
Fruit, first twiddle factor are determined according to baseline sample points.
Step S502, in two butterfly operation module of base corresponding with the second output terminal mouth, to the output sample
First twiddle factor corresponding with the output sample carries out two butterfly-unit of base, obtains second port operation result.
Step S503, the first port operation result of each memory and the second port operation result group
Into the butterfly computation result.
Step S103, if the scheduling factor M be more than 1 and the sample points be the baseline sample points 2NTimes, N
For positive integer, recycle whole butterfly processing elements in the computing module and carry out FFT butterfly computations, until whole institutes
The sample point for stating FFT is calculated and is finished, and is obtained first order operation result, the first order operation result is stored in respectively corresponding
The memory of the butterfly processing element.
Illustratively, as N=2, then the sample points be the baseline sample points 4 times, the sample points
Be 2048,2048 sample points be divided into 4 parts, by first part in the computing module whole butterfly computation lists
Member is carried out at the same time FFT butterfly computations, obtains the first result；After first part's sample point FFT operations, second part is existed
All the butterfly processing element is carried out at the same time FFT butterfly computations in the computing module, obtains the second result；In second part
After sample point FFT operations, by Part III, all the butterfly processing element is carried out at the same time FFT in the computing module
Butterfly computation obtains third result；After Part III sample point FFT operations, by Part IV in the computing module
The middle whole butterfly processing element is carried out at the same time FFT butterfly computations, obtains the 4th as a result, the first result, the second result, third
As a result the first order operation result is formed with the 4th result.
Step S104 based on the first order operation result, recycles the whole butterfly in the computing module
Arithmetic element carries out FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
Illustratively, step S104 may comprise steps of.
Sample points in the first order operation result are divided into 2 by step S601NA operation group.
Illustratively, as N=2, the sample points in the first order operation result are divided into 4 operation groups.
First result is exactly first operation group, and second result is exactly second operation group, and the third result is just
It is third operation group, the 4th result is exactly the 4th operation group.
Step S602, using all two butterfly operation modules of base, by 2NL-th operation base in a operation group
Group and the L+1 operation group progress FFT butterfly computation, wherein L=1,3 ..., 2N- 1, second level operation result is obtained, until
Obtain the N+1 grades of butterfly computation results.
Illustratively, as N=2, the sample points in the first order operation result are divided into 4 operation groups, 4
A operation group includes：First operation group, second operation group, third operation group and the 4th operation group.
First operation group and second operation group are subjected to FFT butterfly computations, obtain the first result of the second level.Third is transported
It calculates group and the 4th operation group carries out FFT butterfly computations, obtain the second result of the second level.First result of the second level and
Second result of the second level forms the second level operation result.By first result of the second level and the second level second
As a result FFT butterfly computations are carried out, obtain the third level butterfly computation as a result, this described third level butterfly computation result is exactly
Last butterfly computation result corresponding with 2048 sample points.
Illustratively, by first operation group (including 512 sample points) and second operation group (including 512
A sample point) FFT butterfly computations are carried out, during obtaining the first result of the second level, first, first operation group is divided into
2 parts, first operation group forepart (including 256 sample points) and first operation group rear portion are (including 256 samples
Point), second operation group is divided into 2 parts, second operation group forepart (including 256 sample points) and second fortune
It calculates group rear portion (including 256 sample points).Using all two butterfly operation modules of base and preset second twiddle factor,
FFT butterfly computations are carried out to first operation group forepart and second operation group forepart, obtain the first forepart operation result,
First operation group rear portion and second operation group rear portion are subjected to FFT butterfly computations, obtain the first rear portion operation result.
First forepart operation result and first rear portion operation result form first result of the second level.Then, by third
A operation group is divided into 2 parts, third operation group forepart (including 256 sample points) and third operation group rear portion
4th operation group is divided into 2 parts by (including 256 sample points), and the 4th operation group forepart is (including 256 samples
This point) and the 4th operation group rear portion (including 256 sample points).Using all two butterfly operation modules of base and preset
The second twiddle factor, FFT butterfly computations are carried out to third operation group forepart and the 4th operation group forepart, obtain the
Third operation group rear portion and the 4th operation group rear portion are carried out FFT butterfly computations by two forepart operation results, obtain the
Two rear portion operation results.Second forepart operation result and second rear portion operation result form second knot of the second level
Fruit.Second twiddle factor is determined according to the sample points.
In the embodiment of the present invention, the Fast Fourier Transform (FFT) FFT data processing method includes：By the sample of the FFT
Points divided by preset baseline sample points, obtain scheduling factor M, the M>0, the baseline sample points are according to preset fortune
The operand for calculating module determines；If the scheduling factor M is less than or equal to 1, chosen in the computing module at least one
Butterfly processing element carries out FFT butterfly computations to the sample point of the FFT simultaneously, obtains butterfly computation as a result, the operation mould
Block includes multiple butterfly processing elements, and each butterfly processing element includes：One memory and two two butterflies of base
Computing module；If the scheduling factor M be more than 1 and the sample points be the baseline sample points 2NTimes, N is just whole
Number recycles whole butterfly processing elements in the computing module and carries out FFT butterfly computations, until all FFT
Sample point calculate and finish, obtain first order operation result；The first order operation result is stored in respectively corresponding described
The memory of butterfly processing element；Based on the first order operation result, recycle described in the whole in the computing module
Butterfly processing element carries out FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
So after the sample point of FFT of FFT butterfly computations to be carried out is got, the Fast Fourier Transform (FFT) FFT numbers
The sample points of the FFT divided by preset baseline sample are counted according to processing method, scheduling factor M are obtained, then according to institute
It states the value range of scheduling factor M and carries out FFT butterfly computations to dispatch the sample point of the FFT, if the scheduling factor M is less than
Or equal to 1, at least one butterfly processing element is chosen in the computing module, the sample point of the FFT is carried out simultaneously
FFT butterfly computations obtain butterfly computation as a result, at this moment only carrying out primary whole FFT butterfly computations just foot on computing module
It is much of that.If the scheduling factor M be more than 1 and the sample points be the baseline sample points 2NTimes, it recycles described
All the butterfly processing element carries out FFT butterfly computations in computing module, until all the sample point of the FFT has been calculated
Finish, obtain first order operation result；The first order operation result is stored in depositing for the corresponding butterfly processing element respectively
Reservoir；The whole butterfly processing element recycled in the computing module carries out FFT butterfly computations, until obtaining N+
1 grade of butterfly computation result.So when the scheduling factor M be more than 1 and the sample points be the baseline sample points 2N
Times when, to recycle in the computing module all butterfly processing elements and carry out FFT butterfly computations, until described in whole
The sample point of FFT, which calculates, to be finished, and obtains first order operation result, then again using obtained first order operation result as input
Data, the whole butterfly processing element recycled in the computing module carries out FFT butterfly computations, until obtaining N+
1 grade of butterfly computation is as a result, the N+1 grades of butterfly computation results finally obtained are only FFT butterflies fortune corresponding with the sample point of FFT
Calculate result.So even if only providing a kind of computing module (data dispatch structure), method can be according to the sample points of FFT
With the computing resource (computing resource and baseline sample points are corresponding) of computing module, data are dispatched for FFT butterfly computations, no matter
The sample points of FFT are more or few, can use a kind of this computing module, while taken into account calculating speed problem and calculating
Resource constraint problem ensure that diversity and the flexibility of data dispatch structure application environment, avoid due to data dispatch structure
Can only meet data dispatch structure application environment caused by the requirement of a certain calculating speed and computing resource constraints it is single,
Therefore the problem of flexibility is low, alleviates that data dispatch structure application environment in the prior art is single, flexibility is low
Problem has reached the diversity for improving data dispatch structure application environment and the skill for the flexibility for improving data dispatch structure
Art effect.
In another embodiment of the present invention, to a kind of Fast Fourier Transform (FFT) FFT numbers disclosed in the embodiment of the present invention
It describes in detail according to processing unit, the Fast Fourier Transform (FFT) FFT data processing unit includes：Divided by module, selection mould
Block, the first computing module and the second computing module；
Described divided by module, for by the sample points of the FFT divided by preset baseline sample points, obtain scheduling because
Sub- M, the M>0, the baseline sample points are determined according to the operand of preset computing module；
The selection module, if for the scheduling factor M be less than or equal to 1, chosen in the computing module to
A few butterfly processing element carries out FFT butterfly computations to the sample point of the FFT simultaneously, obtains butterfly computation as a result, described
Computing module includes multiple butterfly processing elements, and each butterfly processing element includes：One memory and two bases
Two butterfly operation modules.
Illustratively, as shown in figure 5, each butterfly processing element includes：One memory 51 and two two butterflies of base
Shape computing module.The memory 51 can be dual-ported memory, and the dual-ported memory includes：First output port and
Second output terminal mouth, first output port are correspondingly connected with two butterfly operation module 52 of base, the second output terminal mouth
It is correspondingly connected with two butterfly operation module 53 of base.In each butterfly processing element, can also include one rotation because
Submodule 54 includes in the twiddle factor module 54：First twiddle factor and the second twiddle factor.Each butterfly fortune
Unit is calculated all to be independent from each other.
Illustratively, the selection module includes：First selection unit and the first arithmetic element.
First selection unit, for when the scheduling factor M is less than 1, storage to be chosen in the computing module
The matched butterfly processing element of sample points of capacity and the FFT is carried out at the same time FFT butterfly computations, obtains the butterfly computation
As a result；
First arithmetic element, for when the scheduling factor M is equal to 1, utilizing institutes whole in the computing module
It states butterfly processing element and is carried out at the same time FFT butterfly computations, obtain the butterfly computation result.
First computing module, if for the scheduling factor M be more than 1 and the sample points be the baseline sample
The 2 of pointsNTimes, N is positive integer, recycles whole butterfly processing elements in the computing module and carries out FFT butterfly fortune
It calculates, until the sample point of whole FFT is calculated and finished, obtains first order operation result；By the first order operation result
It is stored in the memory of the corresponding butterfly processing element respectively；
Second computing module for being based on the first order operation result, is recycled in the computing module
All the butterfly processing element carries out FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
Illustratively, second computing module includes：Division unit and the second arithmetic element；
The division unit, for the sample points in the first order operation result to be divided into 2NA operation group；
Second arithmetic element, for utilizing all two butterfly operation modules of base, by 2NA operation group
Middle l-th operation group and the L+1 operation group progress FFT butterfly computation, wherein L=1,3 ..., 2N- 1, obtain the second level
Operation result, until obtaining the N+1 grades of butterfly computation results.
In another embodiment of the present invention, to disclosed in the embodiment of the present invention it is a kind of have processor can perform it is non-
The computer-readable medium of volatile program code describes in detail, and said program code makes the processor perform above-mentioned reality
Apply any the method for example.
Unless specifically stated otherwise, component and the opposite step of step, the digital table otherwise illustrated in these embodiments
It is not limit the scope of the invention up to formula and numerical value.
The technique effect of the device that the embodiment of the present invention is provided, realization principle and generation and preceding method embodiment phase
Together, to briefly describe, device embodiment part does not refer to part, can refer to corresponding contents in preceding method embodiment.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
With the specific work process of device, the corresponding process in preceding method embodiment can be referred to, details are not described herein.
In all examples being illustrated and described herein, any occurrence should be construed as merely illustrative, without
It is as limitation, therefore, other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter represents similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need to that it is further defined and explained in subsequent attached drawing.
Flow chart and block diagram in attached drawing show the system, method and computer journey of multiple embodiments according to the present invention
Architectural framework in the cards, function and the operation of sequence product.In this regard, each box in flow chart or block diagram can generation
The part of one module of table, program segment or code, a part for the module, program segment or code include one or more use
In the executable instruction of logic function as defined in realization.It should also be noted that it in some implementations as replacements, is marked in box
The function of note can also be occurred with being different from the sequence marked in attached drawing.For example, two continuous boxes can essentially base
Originally it is performed in parallel, they can also be performed in the opposite order sometimes, this is depended on the functions involved.It is also noted that
It is the combination of each box in block diagram and/or flow chart and the box in block diagram and/or flow chart, can uses and perform rule
The group of specialized hardware and computer instruction is realized or can be used to fixed function or the dedicated hardware based system of action
It closes to realize.
In addition, in the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or be integrally connected；It can
To be mechanical connection or be electrically connected；It can be directly connected, can also be indirectly connected by intermediary, Ke Yishi
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
In the description of the present invention, it should be noted that term " " center ", " on ", " under ", "left", "right", " vertical ",
The orientation or position relationship of the instructions such as " level ", " interior ", " outer " be based on orientation shown in the drawings or position relationship, merely to
Convenient for the description present invention and simplify description rather than instruction or imply signified device or element must have specific orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is only used for description purpose, and it is not intended that instruction or hint relative importance.
The computer program production for the progress Fast Fourier Transform (FFT) FFT data processing method that the embodiment of the present invention is provided
Product, the computer readable storage medium of non-volatile program code that can perform including storing processor, said program code
Including instruction can be used for perform previous methods embodiment described in method, specific implementation can be found in embodiment of the method, herein
It repeats no more.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit can refer to the corresponding process in preceding method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.The apparatus embodiments described above are merely exemplary, for example, the division of the unit,
Only a kind of division of logic function, can there is other dividing mode in actual implementation, in another example, multiple units or component can
To combine or be desirably integrated into another system or some features can be ignored or does not perform.Another point, it is shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be by some communication interfaces, device or unit it is indirect
Coupling or communication connection can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separate, be shown as unit
The component shown may or may not be physical unit, you can be located at a place or can also be distributed to multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
That each unit is individually physically present, can also two or more units integrate in a unit.
If the function is realized in the form of SFU software functional unit and is independent product sale or in use, can be with
It is stored in the non-volatile computer read/write memory medium that a processor can perform.Based on such understanding, the present invention
The part that substantially contributes in other words to the prior art of technical solution or the part of the technical solution can be with software
The form of product embodies, which is stored in a storage medium, including some instructions use so that
One computer equipment (can be personal computer, server or the network equipment etc.) performs each embodiment institute of the present invention
State all or part of step of method.And aforementioned storage medium includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-
Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can be with
Store the medium of program code.
Finally it should be noted that：Embodiment described above, only specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, protection scope of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, it will be understood by those of ordinary skill in the art that：Any one skilled in the art
In the technical scope disclosed by the present invention, it can still modify to the technical solution recorded in previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement is carried out to which part technical characteristic；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover the protection in the present invention
Within the scope of.Therefore, protection scope of the present invention described should be subject to the protection scope in claims.
Claims (10)
1. a kind of Fast Fourier Transform (FFT) FFT data processing method, which is characterized in that including：
The sample points of the FFT divided by preset baseline sample are counted, obtain scheduling factor M, the M>0, the benchmark
Sample points are determined according to the operand of preset computing module；
If the scheduling factor M is less than or equal to 1, at least one butterfly processing element is chosen in the computing module simultaneously
FFT butterfly computations are carried out to the sample point of the FFT, obtain butterfly computation as a result, the computing module includes multiple butterflies
Shape arithmetic element, each butterfly processing element include：One memory and two two butterfly operation modules of base；
If the scheduling factor M be more than 1 and the sample points be the baseline sample points 2NTimes, N is positive integer, repeatedly
Using all the butterfly processing element carries out FFT butterfly computations in the computing module, until all sample points of the FFT
It calculates and finishes, obtain first order operation result, the first order operation result is stored in the corresponding butterfly computation respectively
The memory of unit；
Based on the first order operation result, the whole butterfly processing element recycled in the computing module carries out
FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
2. Fast Fourier Transform (FFT) FFT data processing method according to claim 1, which is characterized in that if described
Scheduling factor M is less than or equal to 1, and at least one butterfly processing element is chosen in the computing module simultaneously to the FFT
Sample point carry out FFT butterfly computations, obtain butterfly computation as a result, including：
When the scheduling factor M is less than 1, memory capacity and the sample points of the FFT are chosen in the computing module
The butterfly processing element matched is carried out at the same time FFT butterfly computations, obtains the butterfly computation result；
When the scheduling factor M is equal to 1, using all the butterfly processing element is carried out at the same time FFT in the computing module
Butterfly computation obtains the butterfly computation result.
3. Fast Fourier Transform (FFT) FFT data processing method according to claim 2, which is characterized in that described when described
When scheduling factor M is less than 1, memory capacity is chosen in the computing module and the matched butterfly of sample points of the FFT is transported
Calculate unit be carried out at the same time FFT butterfly computations, obtain the butterfly computation as a result, including：
By the sample points of the FFT divided by the memory capacity, obtain for calculate the FFT sample point butterfly computation
The destination number of unit；
The destination number butterfly processing element is chosen in the computing module；
In the memory in the butterfly processing element that the sample point write-in of the FFT is chosen；
Read the sample point of the FFT simultaneously from the first output port in the memory of selection and second output terminal mouth；
FFT butterfly computations are carried out respectively to the sample point read from each memory, obtain the butterfly computation
As a result.
4. Fast Fourier Transform (FFT) FFT data processing method according to claim 2, which is characterized in that described when described
When scheduling factor M is equal to 1, using all the butterfly processing element is carried out at the same time FFT butterfly computations in the computing module, obtain
To the butterfly computation as a result, including：
The sample point of the FFT is written in the whole memory in the computing module；
The sample point of the FFT is read simultaneously from the first output port and second output terminal mouth of each memory, is obtained
Export sample；
FFT butterfly computations are carried out to the output sample read from each memory, obtain the butterfly computation knot
Fruit.
5. Fast Fourier Transform (FFT) FFT data processing method according to claim 4, which is characterized in that described to from every
The output sample that is read in a memory carries out FFT butterfly computations, obtain the butterfly computation as a result, including：
In two butterfly operation module of base corresponding with first output port, to it is described output sample and with the output sample
This corresponding preset first twiddle factor carries out two butterfly-unit of base, obtains first port operation result, first rotation
The factor is determined according to baseline sample points；
In two butterfly operation module of base corresponding with the second output terminal mouth, to it is described output sample and with the output sample
This corresponding described first twiddle factor carries out two butterfly-unit of base, obtains second port operation result；
The first port operation result and the second port operation result of each memory form the butterfly fortune
Calculate result.
6. Fast Fourier Transform (FFT) FFT data processing method according to claim 1, which is characterized in that described to be based on institute
First order operation result is stated, the whole butterfly processing element recycled in the computing module carries out FFT butterfly computations,
Until obtain N+1 grades of butterfly computations as a result, including：
Sample points in the first order operation result are divided into 2NA operation group；
Using all two butterfly operation modules of base, by 2NL-th operation group and the L+1 fortune in a operation group
Calculation group progress FFT butterfly computations, wherein L=1,3 ..., 2N- 1, second level operation result is obtained, until obtaining the N+1
Grade butterfly computation result.
7. a kind of Fast Fourier Transform (FFT) FFT data processing unit, which is characterized in that including：Divided by module, choose module, the
One computing module and the second computing module；
Described divided by module for the sample points of the FFT divided by preset baseline sample to be counted, obtains scheduling factor M,
The M>0, the baseline sample points are determined according to the operand of preset computing module；
The selection module if being less than or equal to 1 for the scheduling factor M, chooses at least one in the computing module
A butterfly processing element carries out FFT butterfly computations to the sample point of the FFT simultaneously, obtains butterfly computation as a result, the operation
Module includes multiple butterfly processing elements, and each butterfly processing element includes：One memory and two two butterflies of base
Shape computing module；
First computing module, if for the scheduling factor M be more than 1 and the sample points for the baseline sample points
2NTimes, N is positive integer, recycles whole butterfly processing elements in the computing module and carries out FFT butterfly computations, directly
It calculates and finishes to all sample points of the FFT, obtain first order operation result；The first order operation result is deposited respectively
Enter the memory of the corresponding butterfly processing element；
Second computing module for being based on the first order operation result, recycles the whole in the computing module
The butterfly processing element carries out FFT butterfly computations, until obtaining N+1 grades of butterfly computation results.
8. Fast Fourier Transform (FFT) FFT data processing unit according to claim 7, which is characterized in that the selection mould
Block includes：First selection unit and the first arithmetic element；
First selection unit, for when the scheduling factor M is less than 1, memory capacity to be chosen in the computing module
FFT butterfly computations are carried out at the same time with the matched butterfly processing element of sample points of the FFT, obtain the butterfly computation knot
Fruit；
First arithmetic element, for when the scheduling factor M is equal to 1, utilizing the butterflies whole in the computing module
Shape arithmetic element is carried out at the same time FFT butterfly computations, obtains the butterfly computation result.
9. Fast Fourier Transform (FFT) FFT data processing unit according to claim 8, which is characterized in that second fortune
Module is calculated to include：Division unit and the second arithmetic element；
The division unit, for the sample points in the first order operation result to be divided into 2NA operation group；
Second arithmetic element, for utilizing all two butterfly operation modules of base, by 2NL in a operation group
A operation group and the L+1 operation group progress FFT butterfly computation, wherein L=1,3 ..., 2N- 1, obtain second level operation
As a result, until obtain the N+1 grades of butterfly computation results.
10. a kind of computer-readable medium of non-volatile program code that can perform with processor, which is characterized in that described
Program code makes the processor perform described any the methods of claim 1-6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109543137A (en) * | 2018-11-20 | 2019-03-29 | 中国人民解放军国防科技大学 | Parallel fast Fourier transform data processing method and device in cloud |
| CN110941792A (en) * | 2018-09-24 | 2020-03-31 | 半导体元件工业有限责任公司 | Signal processor, system and method for performing in-situ fast fourier transforms |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101694648A (en) * | 2009-08-28 | 2010-04-14 | 曙光信息产业(北京)有限公司 | Fourier transform processing method and device |
| CN101794275A (en) * | 2010-03-22 | 2010-08-04 | 华为技术有限公司 | Equipment for quick Fourier transformation computation |
| CN103226543A (en) * | 2013-04-26 | 2013-07-31 | 中国科学院微电子研究所 | FFT processor with pipeline structure |
| CN105183701A (en) * | 2015-09-06 | 2015-12-23 | 北京北方烽火科技有限公司 | 1536-point FFT processing mode and related equipment |
| US20170277656A1 (en) * | 2016-03-22 | 2017-09-28 | Eugene Britto John | Method and apparatus for reducing power and cycle requirement for fft of ecg signals |
-
2018
- 2018-03-01 CN CN201810174203.0A patent/CN108197074B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101694648A (en) * | 2009-08-28 | 2010-04-14 | 曙光信息产业(北京)有限公司 | Fourier transform processing method and device |
| CN101794275A (en) * | 2010-03-22 | 2010-08-04 | 华为技术有限公司 | Equipment for quick Fourier transformation computation |
| CN103226543A (en) * | 2013-04-26 | 2013-07-31 | 中国科学院微电子研究所 | FFT processor with pipeline structure |
| CN105183701A (en) * | 2015-09-06 | 2015-12-23 | 北京北方烽火科技有限公司 | 1536-point FFT processing mode and related equipment |
| US20170277656A1 (en) * | 2016-03-22 | 2017-09-28 | Eugene Britto John | Method and apparatus for reducing power and cycle requirement for fft of ecg signals |
Non-Patent Citations (1)
| Title |
|---|
| 韩颖: "FPGA实现高速FFT处理器的设计", 《研究与开发》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110941792A (en) * | 2018-09-24 | 2020-03-31 | 半导体元件工业有限责任公司 | Signal processor, system and method for performing in-situ fast fourier transforms |
| CN109543137A (en) * | 2018-11-20 | 2019-03-29 | 中国人民解放军国防科技大学 | Parallel fast Fourier transform data processing method and device in cloud |
| CN109543137B (en) * | 2018-11-20 | 2022-11-11 | 中国人民解放军国防科技大学 | Parallel fast Fourier transform data processing method and device in cloud |
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