CN103034621B - The address mapping method of base 2 × K parallel FFT framework and system - Google Patents

Abstract

The invention discloses a kind of address mapping method and system of base 2 × K parallel FFT framework, it is characterized in that the base 2FFT computing flow graph adopting permanent structure; Comprise K base 2 dish and calculate unit, K is the integer power of 2; With 2K dual port data memory for shared storage, form two memory set with two groups of 2K single port data storeies respectively; K base 2 dish calculates unit by FFT arithmetic operation number from a memory set parallel read-out, and operation result operand parallel is write another memory set; Twiddle factor leaves in K twiddle factor ROM; FFT arithmetic operation number deposits algorithm, determines to input the address of FFT arithmetic operation number in memory set; Parallel read/write address produces algorithm, determines FFT arithmetic operation number read/write address.Parallel FFT processor framework designed according to this invention, avoids and use multi-level lookup table circuit in operand replacement part, simplifies operand parallel read/write address production part circuit simultaneously.

Description

The address mapping method of base 2 × K parallel FFT framework and system

Technical field

The present invention relates to fft processor, more particularly relate to a kind of address mapping method and system of parallel FFT processor.

Background technology

Discrete Fourier transformation DFT is the important mathematical tool describing discrete signal time domain and frequency domain relation, along with the appearance of quick computing technique FFT, it is widely used in digital signal processing and picture signal process etc., is its main operational of many systems.FFT operating structure is special, in the application scenario that some have higher requirements to FFT arithmetic speed, needs to adopt fft processor.

The target of fft processor is the flowing water execution of butterfly processing element, and this just requires that multiple operands of butterfly processing element can walk abreast and reads in or write out.Parallel FFT processor makes multiple butterfly processing element parallel pipelining process perform, and arithmetic speed is faster, requires that numerous operand parallels that multiple butterfly calculates unit read in or write out simultaneously, therefore there is the storage arrangement of FFT arithmetic operation number and parallel conflict-free access problem.Until 2008, the problems referred to above just obtain system and solve.D.Reisis and N.Vlassopoulos (is published in IEEE Transactions on circuits and systems I at article " Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures ", Vol.55, No.11, p3438-3447) in adopt the fft algorithm of former address computing to propose a kind of parallel FFT processor framework.This framework uses multi-level lookup table circuit to calculate the input and output data sorting of unit to butterfly, forms described FFT arithmetic operation number replacement part, to realize the parallel conflict-free access of FFT arithmetic operation number storer.Although the program solves the storage arrangement of FFT arithmetic operation number and parallel conflict-free access problem, and the data storage capacity needed is minimum, owing to using multi-level lookup table circuit, causes operand replacement part circuit complicated.In addition, program extendability is poor, if desired increases the dish comprised in parallel FFT processor and calculates element number, just need to redesign lut circuits.

Summary of the invention

The present invention is for avoiding the weak point existing for above-mentioned prior art, a kind of address mapping method and system of base 2 × K parallel FFT framework are provided, adopt the base 2FFT computing flow graph of permanent structure, FFT arithmetic operation number is utilized to deposit algorithm and parallel read/write address generation algorithm, avoid using multi-level lookup table circuit in operand replacement part, make operand parallel read/write address production part circuit simpler simultaneously.

The present invention is that technical solution problem adopts following technical scheme:

The feature of the address mapping method of base 2 × K parallel FFT framework of the present invention is:

Adopt the base 2FFT computing flow graph of permanent structure, parallel FFT framework comprises K base 2 dish and calculates unit, and K is the integer power of 2;

With 2K dual port data memory for shared storage, a described 2K dual port data memory and first group of 2K single port data storer form a memory set, and are formed another memory set with a described 2K dual port data memory and second group of 2K single port data storer;

K base 2 dish calculates unit by FFT arithmetic operation number from a memory set parallel read-out, and FFT operation result operand parallel is write another memory set;

Twiddle factor leaves in K twiddle factor ROM;

The address mapping method of described base 2 × K parallel FFT framework carries out as follows:

A, determine the deposit method of described FFT arithmetic operation number in memory set:

If N is the quantity of described FFT arithmetic operation number; K is the label of operand, k=0,1 ..., N-1; It is B (k) that operand k leaves body label in, and inner address is in the memory set of A (k);

When time, operand k leaves in the dual port data memory of memory set, and has:

When operand k leaves in the single port data storer of memory set, and has:

Wherein $p\left(k\right)=\left\{\begin{array}{cc}0,& k\mathrm{mod}2=1\\ 2,& k\mathrm{mod}2=0\end{array}\right.,$ for downward round numbers, mod is remainder number;

B, determine described FFT arithmetic operation number read address;

If m is described base 2 dish calculate element numerals, m=0,1 ..., K-1; Base 2 dish is calculated unit m and is comprised two read port BFI (m, 0) and BFI (m, 1); The FFT arithmetic operation number that read port BFI (m, 0) and BFI (m, 1) reads in is represented respectively with MBFI (m, 0) and MBFI (m, 1); The parallel read operation number of times of one deck FFT computing needs has been represented with cntr,

$\mathrm{cntr}=\mathrm{0,1},\·\·\·,\frac{N}{2K}-1;$

Described FFT arithmetic operation number MBFI (m, 0) is from the dual port data memory of memory set, and reading address is

Described FFT arithmetic operation number MBFI (m, 1) is from the single port data storer of memory set, and reading address is

C, determine the write address of described FFT arithmetic operation number;

Base 2 dish is calculated unit m and is comprised two write port BFO (m, 0) and BFO (m, 1); The FFT arithmetic operation number that write port BFO (m, 0) and BFO (m, 1) writes is represented respectively with MBFO (m, 0) and MBFO (m, 1); The concurrent write number of operations of one deck FFT computing needs has been represented with cntw,

When described FFT arithmetic operation number MBFO (m, 0) and MBFO (m, 1) all write in the dual port data memory of memory set, and write address is:

$\left\{\begin{array}{c}B\left(\mathrm{MBFO}(m,0)\right)=2m\\ B\left(\mathrm{MBFO}(m,1)\right)=2m+1\\ A\left(\mathrm{MBFO}(m,0)\right)=A\left(\mathrm{MBFO}(m,1)\right)=\mathrm{cntw}\end{array}\right.---\left(4\right);$

When described FFT arithmetic operation number MBFO (m, 0) and MBFO (m, 1) all write in the single port data storer of memory set, and write address is:

$\left\{\begin{array}{c}B\left(\mathrm{MBFO}(m,0)\right)=2K-2-2m\\ B\left(\mathrm{MBFO}(m,1)\right)=2K-1-2m\\ A\left(\mathrm{MBFO}(m,0)\right)=A\left(\mathrm{MBFO}(m,1)\right)=\mathrm{cntw}-\frac{N}{4K}\end{array}\right.---\left(5\right);$

D, determine the deposit method of twiddle factor in described twiddle factor ROM:

The storage content of a described K twiddle factor ROM is identical, all deposits by address increment order the twiddle factor that index is w, and w span is [0, N-1];

E, determine that twiddle factor reads address:

Represent that one deck FFT computing walks abreast with cnt and read the number of times of twiddle factor, n=2 ^lfor the quantity of described FFT arithmetic operation number; N is FFT computing progression, n=1,2 ..., L; Then butterfly calculation unit m when n-th grade of FFT computing address P (m, n) of reading of twiddle factor is:

$P(m,n)=\left\{\begin{array}{cc}0,& n=1\\ \mathrm{rev}\left((m+K\×\mathrm{cnt})\mathrm{mod}{2}^{n-1}\right),& n\≠1\end{array}\right.---\left(6\right)$

Wherein rev (), represents bit-reversed operation.

The feature of the address mapping system of base 2 × K parallel FFT framework of the present invention is that described System's composition comprises:

System control component, for Systematical control with synchronous;

Base 2 butterfly computation parts, complete base 2 butterfly computation within each cycle, and described base 2 butterfly computation parts are K;

2K dual port data memory, for storing described FFT arithmetic operation number and supporting that concurrent reading and concurrent writing operates;

4K single port data storer, for storing described FFT arithmetic operation number and supporting write or read operation;

Twiddle factor ROM, for storing twiddle factor and only supporting read operation, described twiddle factor ROM is K independently ROM (read-only memory);

Operand parallel read/write address production part, for producing the address of FFT arithmetic operation number in memory set in FFT calculating process;

Operand replacement part, exchanges described FFT arithmetic operation number for dual port data memory and between single port data storer and a described K base 2 butterfly computation parts;

Operand initial address production part, at the described FFT arithmetic operation number inputted outside stored in described memory set process, produces memory pool address;

Twiddle factor address generating component, for generating the address of twiddle factor ROM.

Compared with the prior art, beneficial effect of the present invention is embodied in:

1, the present invention is by adopting the base 2FFT computing flow graph of permanent structure, FFT arithmetic operation number is utilized to deposit algorithm and parallel read/write address generation algorithm, make the operand replacement part circuit of parallel FFT processor simple, avoid the use of multi-level lookup table circuit, simplify FFT arithmetic operation number simultaneously and to walk abreast read/write address production part;

2, the present invention comprises different base 2 dish and calculates the parallel FFT processor of element number, its FFT arithmetic operation number walk abreast read/write address produce and replacement part structure identical, therefore increase base 2 dish and calculate unit and do not need to redesign circuit, extensibility is good.

Accompanying drawing explanation

Fig. 1 is base 2 × K parallel FFT processor structured flowchart in the present invention;

Fig. 2 is permanent structure FFT computing flow graph (N=16) in the present invention;

Fig. 3 is the organizational form of memory set described in the present invention;

Fig. 4 is that in the present invention, in memory set, operand sends into the operand replacement part that unit process calculated by K base 2 dish;

Fig. 5 is the operand replacement part of the operand feeding memory set process of K base 2 dish calculation unit generation in the present invention;

Fig. 6 is that in the present invention, operand parallel reads address generating component;

Fig. 7 is operand parallel write address production part in the present invention.

Embodiment

In the present embodiment, the address mapping method of base 2 × K parallel FFT framework is:

Adopt the base 2FFT computing flow graph of permanent structure, parallel FFT framework comprises K base 2 dish and calculates unit, and K is the integer power of 2;

With 2K dual port data memory for shared storage, a described 2K dual port data memory and first group of 2K single port data storer form a memory set, and are formed another memory set with a described 2K dual port data memory and second group of 2K single port data storer;

K base 2 dish calculates unit by FFT arithmetic operation number from a memory set parallel read-out, and FFT operation result operand parallel is write another memory set;

Twiddle factor leaves in K twiddle factor ROM;

The address mapping method of described base 2 × K parallel FFT framework carries out as follows:

A, determine the deposit method of described FFT arithmetic operation number in memory set:

If N is the quantity of described FFT arithmetic operation number; K is the label of described FFT operand, k=0,1 ..., N-1; It is B (k) that operand k leaves body label in, and inner address is in the described memory set of A (k).

When time, operand k leaves in the dual port data memory of described memory set, and has:

When operand k leaves in the single port data storer of described memory set, and has:

Wherein $p\left(k\right)=\left\{\begin{array}{cc}0,& k\mathrm{mod}2=1\\ 2,& k\mathrm{mod}2=0\end{array}\right.,$ for downward round numbers, mod is remainder number.

B, determine described FFT arithmetic operation number read address;

If m is described base 2 dish calculate element numerals, m=0,1 ..., K-1; Base 2 dish is calculated unit m and is comprised two read port BFI (m, 0) and BFI (m, 1); The FFT arithmetic operation number that read port BFI (m, 0) and BFI (m, 1) reads in is represented respectively with MBFI (m, 0) and MBFI (m, 1); The parallel read operation number of times of one deck FFT computing needs has been represented with cntr,

$\mathrm{cntr}=\mathrm{0,1},\·\·\·,\frac{N}{2K}-1;$

Described FFT arithmetic operation number MBFI (m, 0) is from the dual port data memory of described memory set, and reading address is

Described FFT arithmetic operation number MBFI (m, 1) is from the single port data storer of described memory set, and reading address is

C, determine the write address of described FFT arithmetic operation number;

Base 2 dish is calculated unit m and is comprised two write port BFO (m, 0) and BFO (m, 1); The FFT arithmetic operation number that write port BFO (m, 0) and BFO (m, 1) writes is represented respectively with MBFO (m, 0) and MBFO (m, 1); The concurrent write number of operations of one deck FFT computing needs has been represented with cntw,

When described FFT arithmetic operation number MBFO (m, 0) and MBFO (m, 1) all write in the dual port data memory of described memory set, and write address is:

$\left\{\begin{array}{c}B\left(\mathrm{MBFO}(m,0)\right)=2m\\ B\left(\mathrm{MBFO}(m,1)\right)=2m+1\\ A\left(\mathrm{MBFO}(m,0)\right)=A\left(\mathrm{MBFO}(m,1)\right)=\mathrm{cntw}\end{array}\right.---\left(4\right);$

When described FFT arithmetic operation number MBFO (m, 0) and MBFO (m, 1) all write in the single port data storer of described memory set, and write address is:

$\left\{\begin{array}{c}B\left(\mathrm{MBFO}(m,0)\right)=2K-2-2m\\ B\left(\mathrm{MBFO}(m,1)\right)=2K-1-2m\\ A\left(\mathrm{MBFO}(m,0)\right)=A\left(\mathrm{MBFO}(m,1)\right)=\mathrm{cntw}-\frac{N}{4K}\end{array}\right.---\left(5\right);$

D, determine the deposit method of twiddle factor in described twiddle factor ROM:

The storage content of a described K twiddle factor ROM is identical, all deposits by address increment order the twiddle factor that index is w, and w span is [0, N-1];

E, determine that twiddle factor reads address:

Represent that one deck FFT computing walks abreast with cnt and read the number of times of twiddle factor, n=2 ^lfor the quantity of described FFT arithmetic operation number; N is FFT computing progression, n=1,2 ..., L; Then butterfly calculation unit m when n-th grade of FFT computing address P (m, n) of reading of twiddle factor is:

$P(m,n)=\left\{\begin{array}{cc}0,& n=1\\ \mathrm{rev}\left((m+K\×\mathrm{cnt})\mathrm{mod}{2}^{n-1}\right),& n\≠1\end{array}\right.---\left(6\right)$

Wherein rev (), represents bit-reversed operation.

In the present embodiment, the formation of the address mapping system of base 2 × K parallel FFT framework comprises:

System control component, for the control of system and synchronous;

Base 2 butterfly computation parts, complete base 2 butterfly computation within each cycle, and base 2 butterfly computation parts are K;

2K dual port data memory, for storing FFT arithmetic operation number and supporting that concurrent reading and concurrent writing operates;

4K single port data storer, for storing FFT arithmetic operation number and supporting write or read operation;

Twiddle factor ROM, for storing twiddle factor and only supporting read operation, twiddle factor ROM is K independently ROM (read-only memory);

Operand parallel read/write address production part, in FFT calculating process, produces the address of FFT arithmetic operation number in memory set;

Operand replacement part, for dual port data memory and the exchange described FFT arithmetic operation number between single port data storer and a described K base 2 butterfly computation parts.

Operand initial address production part, at the described FFT arithmetic operation number inputted outside stored in described memory set process, produces memory pool address;

Twiddle factor address generating component, for generating the address of twiddle factor ROM;

Fig. 1 shows base 2 × K parallel FFT processor structured flowchart, and chief component is: system control component, for the treatment of the control of device and synchronous; Butterfly computation parts, complete base 2 butterfly computation within each cycle, K altogether; Dual port data memory, for storing FFT arithmetic operation number and supporting that concurrent reading and concurrent writing operates, 2K altogether; Single port data storer, for storing FFT arithmetic operation number and supporting write or read operation, 4K altogether; 4K single port data storer is divided into two parts, and every part comprises 2K single port data storer; Be shared with 2K dual port data memory; 2K single port data storer and 2K dual port data memory form memory set, can form altogether two memory set; Twiddle factor ROM, for storing twiddle factor and only supporting read operation, K altogether; Operand parallel read/write address production part, for generating the described address of FFT arithmetic operation number in described memory set; Operand replacement part, for dual port data memory and the exchange described FFT arithmetic operation number between single port data storer and a described K base 2 butterfly computation parts; Operand initial address production part, at the described FFT arithmetic operation number inputted outside stored in described memory set process, produces memory pool address; Twiddle factor address generating component, for generating the address of twiddle factor ROM; Operand communication interface parts, for pending FFT arithmetic operation number is read in parallel FFT processor, or send the operand that parallel FFT processor computing obtains.

After parallel FFT processor starts, a memory set described in N number of FFT arithmetic operation number feeding of computing is treated in outside by operand communication interface parts, and determines the address of peripheral operation number in memory set by operand initial address production part.After outside FFT to be calculated operand all writes above-mentioned memory set, each parts of system control component cooperation control parallel FFT processor start computing.The address of address generating component (see figure 4) generation is read according to operand parallel, 2K described FFT arithmetic operation number reads from above-mentioned memory set, sends into K base 2 dish calculation unit through the operand replacement part (see figure 6) calculating unit to described base 2 dish by described memory set.Twiddle factor address generating component produces the address of described twiddle factor ROM simultaneously, and K twiddle factor reads from described twiddle factor ROM, is also admitted to K base 2 dish and calculates unit.K base 2 dish is calculated unit and is started computing, and next cycle by 2K operand result calculating after by described base 2 dish calculation unit to the operand replacement part (see figure 7) of described memory set, the another one memory set described in write.The above-mentioned address of the 2K a calculated operand in this memory set, is produced by operand parallel write address production part (see figure 5).Described step repeats above after secondary, N number of FFT operand is all read by initial memory group altogether, and is written with another memory set after base 2 dish calculation unitary operation.So far, processor completes an individual layer computing of FFT.For the FFT computing of N number of operand, need repetition log altogether ₂the computing of N above-mentioned FFT individual layer.The control of all operation times completes by system control component.

Illustrate successively below the base 2FFT computing flow graph of permanent structure, the organizational form of described memory set, described FFT operand address composition, operand parallel reads address generating component, operand parallel write address production part and operand replacement part.Remaining part in base 2 × K parallel FFT processor structured flowchart easily designs, and does not explain.

Base 2 × K parallel FFT processor of the present invention adopts permanent structure FFT computing flow graph (for N=16) as shown in Figure 2, and for N=2 ^lthe permanent structure FFT computing flow graph of individual operand is just like drawing a conclusion: operand k and progression n has nothing to do, namely in FFT flow graph every grade there is identical structure; Any one-level FFT computing comprises individual dish-style computing, two input end operand labels of dish-style computing be collectively expressed as u and two output terminal operand labels are collectively expressed as 2u and 2u+1, wherein if be m dish-style computing at the twiddle factor of n-th grade, then have

$P_{(m,n)}=\left\{\begin{array}{cc}0,& n=1\\ \mathrm{rev}\left(m\mathrm{mod}{2}^{n-1}\right),& n\≠1\end{array}\right.---\left(7\right)$

Wherein n=1,2 ..., L; M=0,1 ..., 2 ^l-1; Rev () represents bit-reversed operation, and the binary representation of routine A is A=1011b, then rev (A)=1101b.

The organizational form of described memory set is shown in Fig. 3.Described fft processor has 2 memory set, and each memory set comprises a described 2K dual-ported memory and a described 2K one-port memory.2 memory set share a described 2K dual-ported memory.

The described address of FFT operand k in memory set is made up of three parts: type of memory, body label B (k) and inner address A (k).Described type of memory represents that operand k place storer is dual-ported memory or one-port memory.Body label B (k) represents operand k place storer label, and span is B (k)=0,1 ..., 2K-1.Inner address A (k) represents memory inside access unit address, and span is A (k)=0,1 ..., H, wherein fig. 3 intuitively describes body label B (k) and the implication represented by inner address A (k).

The design that operand parallel reads address generating component is determined by A (MBFI (m, 0)) and A (MBFI (m, 1)) in formula (2) (3) in right 1.b, and to calculate the label of unit irrelevant with described base 2 dish.Because described FFT operand quantity N and described base 2 butterfly calculate the power that unit number K is 2, L=log can be obtained ₂n and r=log ₂k.Parallel read address generating component structure and see Fig. 4, wherein AddrGen_R represents the address sending into memory set, gets the high L-r-2 position of L-r-1 digit counter Count_0.

The design of operand parallel write address production part is determined by A (MBFO (m, 0)) and A (MBFO (m, 1)) in formula (4) (5) in right 1.c, and to calculate the label of unit irrelevant with described base 2 dish.Because described FFT operand quantity N and described base 2 butterfly calculate the power that unit number K is 2, L=log can be obtained ₂n and r=log ₂k.Parallel write address production part structure is shown in Fig. 5, and wherein AddrGen_W represents the address sending into memory set, gets the low L-r-2 position of L-r-1 digit counter Count_1.Calculate unit due to a described K base 2 dish to complete and once calculate 1 cycle of needs, therefore counter Count_1 deposits one-period by described counter Count_0 and obtains.

Operand replacement part completes the exchanges data that a described K base 2 dish calculates unit and described memory set, therefore different according to data direction, divide for by memory set to the replacement part of dish calculation unit process with by the replacement part of dish calculation unit to memory set process, two parts altogether.

The design of being calculated the replacement part of unit process by memory set to dish is determined by the B (MBFI (m, 0)) in formula (2) (3) in right 1.b and B (MBFI (m, 1)).And B (MBFI (m, 0)) and B (MBFI (m, 1)) fixedly gets one in two values, and only relevant with the label m that unit calculated by described base 2 dish.Therefore, the described structure being calculated the replacement part of unit process by memory set to dish is shown in Fig. 6, utilize alternative MUX to realize, and the selecting side of these MUX is identical, is the lowest order B of Fig. 4 Counter Count_0 by 2K ₀.

Calculate unit by dish to be determined to the design of the replacement part of memory set process by the B (MBFO (m, 0)) in formula (4) (5) in right 1.c and B (MBFO (m, 1)).And B (MBFO (m, 0)) and B (MBFO (m, 1)) fixedly gets one in two values, and only relevant with the label m that unit calculated by described base 2 dish.Therefore, describedly calculate unit by dish and see Fig. 7 to the replacement part of memory set process, utilize alternative MUX to realize by 2K is individual, and the selecting side of these MUX is identical, is the most significant digit B of Fig. 5 Counter Count_1 _l-r-2.

Claims (2)

1. an address mapping method for base 2 × K parallel FFT framework, is characterized in that:

Adopt the base 2FFT computing flow graph of permanent structure, parallel FFT framework comprises K base 2 dish and calculates unit, and K is the integer power of 2;

With 2K dual port data memory for shared storage, a described 2K dual port data memory and first group of 2K single port data storer form a memory set, and are formed another memory set with a described 2K dual port data memory and second group of 2K single port data storer;

K base 2 dish calculates unit by FFT arithmetic operation number from a memory set parallel read-out, and FFT operation result operand parallel is write another memory set;

Twiddle factor leaves in K twiddle factor ROM;

The address mapping method of described base 2 × K parallel FFT framework carries out as follows:

A, determine the deposit method of described FFT arithmetic operation number in memory set:

If N is the quantity of described FFT arithmetic operation number; K is the label of operand, k=0,1 ..., N-1; It is B (k) that operand k leaves body label in, and inner address is in the memory set of A (k);

When time, operand k leaves in the dual port data memory of memory set, and has:

When operand k leaves in the single port data storer of memory set, and has:

Wherein $p\left(k\right)=\left\{\begin{array}{cc}0,& k\mathrm{mod}2=1\\ 2,& k\mathrm{mod}2=0\end{array}\right.,$ for downward round numbers, mod is remainder number;

B, determine described FFT arithmetic operation number read address;

If m is described base 2 dish calculate element numerals, m=0,1 ..., K-1; Base 2 dish is calculated unit m and is comprised two read port BFI (m, 0) and BFI (m, 1); The FFT arithmetic operation number that read port BFI (m, 0) and BFI (m, 1) reads in is represented respectively with MBFI (m, 0) and MBFI (m, 1); The parallel read operation number of times of one deck FFT computing needs has been represented with cntr, $\mathrm{cntr}=\mathrm{0,1},...,\frac{N}{2K}-1;$

Described FFT arithmetic operation number MBFI (m, 0) is from the dual port data memory of memory set, and reading address is

Described FFT arithmetic operation number MBFI (m, 1) is from the single port data storer of memory set, and reading address is

C, determine the write address of described FFT arithmetic operation number;

Base 2 dish is calculated unit m and is comprised two write port BFO (m, 0) and BFO (m, 1); The FFT arithmetic operation number that write port BFO (m, 0) and BFO (m, 1) writes is represented respectively with MBFO (m, 0) and MBFO (m, 1); The concurrent write number of operations of one deck FFT computing needs has been represented with cntw,

When described FFT arithmetic operation number MBFO (m, 0) and MBFO (m, 1) all write in the dual port data memory of memory set, and write address is:

$\left\{\begin{array}{c}B\left(\mathrm{MBFO}(m,0)\right)=2m\\ B\left(\mathrm{MBFO}(m,1)\right)=2m+1\\ A\left(\mathrm{MBFO}(m,0)\right)=A\left(\mathrm{MBFO}(B,1)\right)=\mathrm{cntw}\end{array}\right.---\left(4\right);$

When described FFT arithmetic operation number MBFO (m, 0) and MBFO (m, 1) all write in the single port data storer of memory set, and write address is:

$\left\{\begin{array}{c}B\left(\mathrm{MBFO}(m,0)\right)=2K-2-2m\\ B\left(\mathrm{MBFO}(m,1)\right)=2K-1-2m\\ A\left(\mathrm{MBFO}(m,0)\right)=A\left(\mathrm{MBFO}(m,1)\right)=\mathrm{cntw}-\frac{N}{4K}\end{array}\right.---\left(5\right);$

D, determine the deposit method of twiddle factor in described twiddle factor ROM:

The storage content of a described K twiddle factor ROM is identical, all deposits by address increment order the twiddle factor that index is w, and w span is [0, N-1];

E, determine that twiddle factor reads address:

Represent that one deck FFT computing walks abreast with cnt and read the number of times of twiddle factor, n=2 ^lfor the quantity of described FFT arithmetic operation number; N is FFT computing progression, n=1,2 ..., L; Then butterfly calculation unit m when n-th grade of FFT computing address P (m, n) of reading of twiddle factor is:

$P(m,n)=\left\{\begin{array}{cc}0,& n=1\\ \mathrm{rev}\left((m+K\×\mathrm{cnt})\mathrm{mod}{2}^{n-1}\right),& n\≠1\end{array}\right.---\left(6\right)$

Wherein rev (), represents bit-reversed operation.

2., based on an address mapping system for the address mapping method of base 2 × K parallel FFT framework according to claim 1, it is characterized in that described System's composition comprises:

System control component, for Systematical control with synchronous;

Base 2 butterfly computation parts, complete base 2 butterfly computation within each cycle, and described base 2 butterfly computation parts are K;

2K dual port data memory, for storing FFT arithmetic operation number and supporting that concurrent reading and concurrent writing operates;

4K single port data storer, for storing described FFT arithmetic operation number and supporting write or read operation;

Twiddle factor ROM, for storing twiddle factor and only supporting read operation, described twiddle factor ROM is K independently ROM (read-only memory);

Operand parallel read/write address production part, for producing the memory address of FFT arithmetic operation number in FFT calculating process;

Operand replacement part, exchanges described FFT arithmetic operation number for dual port data memory and between single port data storer and a described K base 2 butterfly computation parts;

Operand initial address production part, at the described FFT arithmetic operation number inputted outside stored in described memory set process, produces memory pool address;

Twiddle factor address generating component, for generating the address of twiddle factor ROM.