CN108173617B

CN108173617B - Method for acquiring full-network clock topology and clock path

Info

Publication number: CN108173617B
Application number: CN201711168425.3A
Authority: CN
Inventors: 张春慧
Original assignee: Beijing Lan Yun Technology Co Ltd
Current assignee: Beijing Lan Yun Technology Co Ltd
Priority date: 2017-11-21
Filing date: 2017-11-21
Publication date: 2020-02-11
Anticipated expiration: 2037-11-21
Also published as: CN108173617A

Abstract

The invention discloses a full-network clock topology and a clock path acquisition method. The invention relates to a method for acquiring a whole network clock topology, which extracts all links of the whole network clock topology according to the whole network clock information, namely input 2; according to the link and the network element topology of the whole network, namely input 1, extracting the detailed information of all clock topology links, namely input 3; the full network clock topology is obtained from input 3. The method for acquiring the clock path of the whole network judges the role of each network element through the input 2; then deleting the ASG sink nodes, traversing all nodes and links of the remaining network through DFS, and finding out ASG directly connected with the remaining network through input 3; and (4) calculating the shortest paths from all CSGs to the ASG by using a Dijkstra algorithm, and obtaining the hop count of each shortest path. The invention has no limit to the number of the network elements and the paths and the protocol, the message and the packet sending mechanism supported by the network elements, can be suitable for networks of any scale, and has wider application scenes.

Description

Method for acquiring full-network clock topology and clock path

Technical Field

The invention relates to the technical field of wireless communication, in particular to a method for acquiring a whole network clock topology and a clock path.

Background

The Backhaul network is a network connecting a base station to a base station controller or an IP CORE, and originally mainly uses SDH, and most of the SDH is replaced by IP equipment at present. Due to the rapid development of mobile services, the number of devices in a wireless backhaul network is increasing. Mobile services require clock synchronization technology, 2G and 3G require frequency synchronization, 4G requires time synchronization, network construction requires that each base station supports a GPS clock source, which results in high network construction cost and security (GPS is the american global positioning system), so that Backhaul devices are required to support clock synchronization technology, and the base stations can extract clocks from transmission signals, thereby achieving clock synchronization of the whole network, and most of the existing network devices support clock synchronization technologies such as 1588v2, ACR, and synchronous ethernet.

5000-6000 thousand transmission devices in a RAN network of a large city exist, so that a plurality of clock sources exist in the network, especially most clock synchronization technologies such as synchronous ethernet, 1588v2 and the like have hop limit, and the longer the hop, the larger the error is, and the quality of mobile services is further influenced. Therefore, the network operation and maintenance personnel must know the clock topology of the whole network in time, include the clock path of each network element, and determine the hop count of each network element to the clock source, so as to find whether the threshold is exceeded or not, which is a bottleneck point affecting the mobile service. The network structure of Backhaul is shown in FIG. 1.

The number of network elements of the Bckhaul network is large, if the clock path of each network element needs to be known, one method is manual query, but thousands of devices are queried manually, the workload is huge, and the devices cannot be updated in real time.

Regarding clock topology discovery, the following techniques are mainly used in the industry:

technique 1: the network element acquires the position information of the network element through a 1588 protocol; and the network element sends the position information to the management equipment so that the management equipment generates a clock topological structure of the network according to the position information. The technology obtains the position information of the network element through 1588, and the network element supports the 1588 protocol, so that the technology has good compatibility. The management equipment generates a clock topological structure according to the position information, does not depend on a physical topological structure of the network element, and is easy to operate.

Technique 2: the ring network topology structure with the common clock comprises a central controller and a plurality of sub-nodes, wherein the central controller serving as a main node and the plurality of sub-nodes are internally provided with an FPGA (field programmable gate array), a first transceiver module and a second transceiver module; the FPGA is electrically connected with the corresponding first transceiver module and the second transceiver module; the first transceiver module is used as a clock signal transceiver interface, and the second transceiver module is used as a data signal transceiver interface; the first transceiver modules are connected in sequence to form a clock ring network; the clock ring network transmits a common clock for the whole network, the common clock is sent by the main node, and each sub-node receives the clock and sends the clock to the next node; the plurality of second transceiving modules are sequentially connected to form a data signal ring network; the data signal ring network is used for transmitting serial data signals. The technology can greatly save the network communication time and improve the ring network communication efficiency.

Technique 3: the method for updating the clock synchronization topology and determining the clock synchronization path comprises the steps of receiving a first message from a first network element, wherein the first message comprises information of the clock synchronization capability of the first network element, the first network element is a network element in a first network, and the first network element has the clock synchronization capability; and updating the clock synchronization topology of the first network according to the information of the clock synchronization capability of the first network element. Further, the method comprises determining a first clock synchronization path from a clock injection node of the first network to the first network element according to the clock synchronization topology of the first network, according to the request of the first network element. The clock synchronization topology is automatically updated according to the information of the network element clock synchronization capability, the clock synchronization path is determined, and the cost of clock synchronization path deployment is reduced.

Disadvantages of technique 1: all devices in the network are required to support the 1588 protocol, but for the Backhaul network, due to the huge number, the transmission device of the base station has a low specification, and the types of the transmission devices are various (including microwave, SDH, switches and the like), and do not necessarily support the 1588 protocol, or the 1588 protocols of different types and different manufacturers cannot be docked, so that the application scenario of the technology 1 is limited.

Disadvantages of technique 2: the method is only aimed at a ring topology and cannot be applied to a tree or network topology, and the technology is a ring clock topology, and is not a clock topology discovery technology.

Disadvantages of technique 3: the method is a topology updating technology, and determines a clock path by sending an updating message. This requires that devices of different types and manufacturers in the Backhaul network support the message and packet sending mechanism, the application scenarios are limited, and frequent packet sending may affect the device performance, which in turn affects the mobile service quality.

Disclosure of Invention

In order to solve the technical problems, the invention provides a full-network clock topology and a clock path acquisition method, so as to solve the problem of finding the clock topology in a wireless Backhaul network.

In a first aspect, the present invention provides a method for acquiring a full-network clock topology, including:

extracting all links of the whole network clock topology according to the whole network clock information, namely input 2;

extracting detailed information of all clock topology links according to the links and the topology of the network elements in the whole network, namely input 1, wherein the detailed information is input 3;

the full network clock topology is obtained from input 3.

Preferably, the input 1 includes a name of each network element in the whole network and interface information of each network element connected with other network elements.

Preferably, the input 2 includes a name of each network element in the whole network and clock source interface information.

Preferably, the input 1 is derived through a network management system.

Preferably, the input 2 is derived by a clock management server.

Preferably, extracting detailed information of all clock topology links according to the links and the input 1 includes:

and searching opposite-end network elements and interface information of corresponding links in the input 1 according to the network element names and the clock interface information in the input 2 to generate detailed information of the whole network clock topology.

In a second aspect, the present invention further provides a clock path obtaining method based on the above full-network clock topology obtaining method, including:

and judging the role of each network element through the input 2, wherein the judgment rule is as follows: the network element connected with the clock server is an aggregation node ASG, and other network elements are access nodes CSG;

deleting ASG sink nodes in the whole network clock topology, and traversing all nodes and links of the remaining network through DFS, wherein the remaining network is called a subnet 1;

finding out ASG directly connected with the subnet 1 through an input 3;

and calculating the shortest paths from all CSG to the ASG by using a Dijkstra algorithm, and obtaining the hop count of the shortest path from each CSG to the ASG.

In a third aspect, the present invention further provides a device for acquiring a full-network clock topology, including:

the link module is arranged to extract all links of the whole network clock topology according to the whole network clock information;

the information module is arranged to extract detailed information of all clock topology links according to the links and the network element topology of the whole network;

and the topology module is arranged to obtain the whole network clock topology according to the detailed information.

The invention reversely calculates the clock topology and the clock path of the whole network through the dynamic clock information, applies a shortest path algorithm (Dijkstra) in an IP routing protocol to the discovery of the clock topology, analyzes the clock topology and the clock path of the whole network at one time according to the static configuration information (topology) of a network management system by using the simulation principle of Flow Analysis, and saves a large amount of manpower and material resources. Meanwhile, the analysis result completely accords with the real path of the clock service because of the service configuration information. The network elements and paths of the whole network and the protocols, messages and packet sending mechanisms supported by the network elements are not limited, the method can be suitable for networks of any scale, and the application scene is wider.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a schematic diagram of a Backhaul network structure in the background art;

fig. 2 is a flowchart of a method for acquiring a full-network clock topology according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a networking topology according to an embodiment of the present invention;

FIG. 4 is two equal cost paths for RouterA according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a clock topology according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a topology corresponding to input 3 according to an embodiment of the present invention;

fig. 7 is a flowchart of a clock path acquisition method based on a full-network clock topology acquisition method according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a clock topology corresponding to the subnet 1 according to the embodiment of the present invention;

FIG. 9 is the TopN path information displayed by the HTML Canvas plug-in according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a full-network clock topology acquisition apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The technical solution of the present invention will be described in detail by specific examples.

Example one

Fig. 2 is a flowchart of a method for acquiring a full-network clock topology according to an embodiment of the present invention. As shown in fig. 2, the method for acquiring a full-network clock topology according to an embodiment of the present invention may include the following steps:

s101, extracting all links of a whole network clock topology according to the whole network clock information, namely input 2;

s102, extracting detailed information of all clock topology links according to the links and the topology of the network elements of the whole network, namely input 1, wherein the detailed information is input 3;

and S103, acquiring the full-network clock topology according to the input 3.

Optionally, on the basis of the foregoing embodiment, the input 1 in S102 in the embodiment of the present invention may include a name of each network element in the entire network and interface information that each network element is connected to other network elements.

Optionally, on the basis of the foregoing embodiment, the input 2 in S101 in the embodiment of the present invention may include a name of each network element in the entire network and clock source interface information.

Optionally, on the basis of the foregoing embodiment, the input 1 in S102 in the embodiment of the present invention may be derived through a network management system.

Alternatively, on the basis of the above embodiment, the input 2 in S101 in the embodiment of the present invention may be derived by the clock management server.

Optionally, an implementation manner of S102 in the embodiment of the present invention may include:

The embodiment of the present invention takes the networking topology shown in fig. 3 as an example to describe the method for acquiring the full-network clock topology according to the embodiment of the present invention.

First, a full-network router topology is derived through a network management system, as shown in table 1.

Table 1: input 1

Node 1	Node 1-interface	Node	2	Node 2-interface
					RouterA	GE0/0/1	RouterB	GE0/0/1
RouterB	GE0/0/2	RouterC	GE0/0/2
				RouterC	GE0/0/1	RouterD	GE0/0/1
RouterC	GE0/0/3	RouterG	GE0/0/1
				RouterD	GE0/0/2	RouterE	GE0/0/2
RouterE	GE0/0/1	RouterF	GE0/0/1
				RouterF	GE0/0/2	RouterG	GE0/0/2
RouterH	GE0/0/1	RouterC	GE0/0/4
				RouterH	GE0/0/2	RouterE	GE0/0/2

It should be noted that, because the network manager of the router device manufacturer may not automatically discover the link from the router to the clock server, the end point of the clock topology path is RouterE, i.e. the first hop directly connecting the router to the clock server.

In the embodiment of the present invention, the table 2 shows how the clock management server derives the clock information of the whole network. Table 2 gives the interface number used by each router to obtain the clock signal.

Table 2: input 2

All links of the clock topology are then extracted from input 2. The clock topology is a subset of the true physical topology. In real networks, redundant links or equivalent paths are typically present for increased reliability. As shown in fig. 4, the two dotted paths in the figure are equivalent paths for RouterA (assuming that the time consumption of each link is the same). For RouterA, the two paths consume the same time, only one path is randomly selected from the two shortest paths when the clock signal is acquired, and the dynamic clock signal acquisition information of the input 2 is generated. In the embodiment of the present invention, when calculating the clock topology, according to the node name and the clock interface in the input 2, the opposite-end network element and the interface information of the link are searched in the input 1, and the detailed information of the clock topology of the whole network, that is, the input 3, is generated, as shown in table 3, and the clock topology drawn according to the input 3 is shown in fig. 5.

Table 3: input 3:

node 1	Node 1-interface	Node	2	Node 2-interface
					RouterA	GE0/0/1	RouterB	GE0/0/1
RouterB	GE0/0/2	RouterC	GE0/0/2
				RouterC	GE0/0/1	RouterD	GE0/0/1
RouterC	GE0/0/3	RouterG	GE0/0/1
				RouterD	GE0/0/2	RouterE	GE0/0/2
RouterE	GE0/0/1	RouterF	GE0/0/1
				RouterF	GE0/0/2	RouterG	GE0/0/2

According to the dynamic clock signal acquisition information of the input 2, two links of the RouterH are not included in the clock topology (assuming that the RouterH is only a transmission node and does not access a service), so that it can be ensured that the clock path calculated by the embodiment of the present invention is completely consistent with the real clock path information of the current network, and the finally obtained clock topology of the whole network is as shown in fig. 6.

The method for acquiring the clock topology of the whole network in the embodiment of the invention is an off-line analysis method, namely the clock topology of the whole network is calculated through the whole network topology (input 1) and the clock signal acquisition information (input 2), so that the network elements and the path number of the whole network and the protocols, messages and packet sending mechanisms supported by the network elements are not limited, the method can be suitable for networks of any scale, and the application scene is wider.

Example two

Fig. 7 is a flowchart of a clock path acquisition method based on a full-network clock topology acquisition method according to an embodiment of the present invention. As shown in fig. 7, the clock path obtaining method based on the full-network clock topology obtaining method of this embodiment includes:

s201, judging the role of each network element through input 2, wherein the judgment rule is as follows: the network element connected to the clock server is an ASG (aggregation node), the other network elements are CSG (access nodes), and the determination results are shown in table 4.

Table 4: network element role judgment result

Device name	Network element roles
		RouterA	CSG
RouterB	CSG
		RouterC	CSG
RouterD	CSG
		RouterE	ASG
RouterF	CSG
		RouterG	CSG

S202, delete ASG aggregation nodes in the full-network clock topology, traverse all nodes and links of the remaining network through DFS, where the remaining network is called subnet 1, as shown in table 5, and the corresponding clock topology is shown in fig. 8.

Table 5: subnet 1

Subnet ID	CSG
			1	RouterA,RouterB,RouterC,RouterD,RouterF,RouterG

S203, find out the ASG directly connected to the subnet 1 through the input 3, i.e. traverse all CSGs in the subnet 1 to see if there is a direct link with the ASG, and output the following table.

Table 6: ASG directly connected to subnet 1

S204, calculating the shortest paths from all CSG to ASG by using Dijkstra algorithm, and obtaining the hop count of the shortest path from each CSG to the ASG, wherein the obtained result is shown in a table 7.

Table 7: shortest path and corresponding hop count from all CSG to ASG

Route of travel	Hop count
		RouterA->RouterB->RouterC->RouterD->RouterE	4
RouterB->RouterC->RouterD->RouterE	3
		RouterC->RouterD->RouterE	2
RouterD->RouterE	1
		RouterF->RouterE	1
RouterG->RouterF->RouterE	2

It should be noted that the TopN (length of path hop count) path information in the embodiment of the present invention may be displayed on an html canvas (topology presentation) plug-in, and more vividly presented in an SOC or a network management control center, as shown in fig. 9.

In the embodiment of the invention, when the clock path is calculated, in order to avoid inconsistency of shortest paths selected by two calculation results of the Dijkstra algorithm, the opposite-end network element and the interface information of the link are searched in the input 1 according to the node name and the clock interface in the input 2, and the detailed information of the clock topology of the whole network is generated.

The method for acquiring the clock path of the whole network in the embodiment of the invention is an off-line analysis method, namely the clock path of the whole network is calculated through the topology (input 1) of the whole network and the clock signal acquisition information (input 2), so that the network elements and the number of the paths of the whole network and the protocols, messages and packet sending mechanisms supported by the network elements are not limited, the method can be suitable for networks of any scale, and the application scene is wider.

EXAMPLE III

Fig. 10 is a schematic structural diagram of a full-network clock topology obtaining apparatus provided in an embodiment of the present invention, including:

the link module is set to extract all links of the whole network clock topology according to the whole network clock information, namely input 2;

the information module is arranged to extract detailed information of all clock topology links according to the links and the topology of the network elements in the whole network, namely input 1, wherein the detailed information is input 3;

a topology module arranged to obtain a full network clock topology from the input 3.

Preferably, the input 1 is derived through a network management system.

Preferably, the input 2 is derived by a clock management server.

Preferably, the information module extracts detailed information of all clock topology links according to the links and the input 1, including:

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by a program instructing associated hardware (e.g., a processor) which may be stored in a computer readable storage medium such as a read only memory, a magnetic or optical disk, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. For example, by means of an integrated circuit, or in the form of a software functional module, for example, by means of a processor executing programs/instructions stored in a memory. Embodiments of the invention are not limited to any specific form of hardware or software combination.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A clock path acquisition method, comprising:

extracting all links of the whole network clock topology according to the whole network clock information;

extracting detailed information of all clock topology links according to the links and the network element topology of the whole network;

acquiring a whole network clock topology according to the detailed information;

the role of each network element is judged through the whole network clock information, and the judgment rule is as follows: the network element connected with the clock server is an aggregation node ASG, and other network elements are access nodes CSG;

deleting ASG sink nodes in the whole network clock topology, traversing all nodes and links of the remaining network through a depth-first search DFS, wherein the remaining network is called a subnet 1;

finding out ASG directly connected with the subnet 1 according to the detailed information;