CN108173617A - A kind of the whole network clock topology and clock method for obtaining path - Google Patents
A kind of the whole network clock topology and clock method for obtaining path Download PDFInfo
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- CN108173617A CN108173617A CN201711168425.3A CN201711168425A CN108173617A CN 108173617 A CN108173617 A CN 108173617A CN 201711168425 A CN201711168425 A CN 201711168425A CN 108173617 A CN108173617 A CN 108173617A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/08—Intermediate station arrangements, e.g. for branching, for tapping-off
- H04J3/085—Intermediate station arrangements, e.g. for branching, for tapping-off for ring networks, e.g. SDH/SONET rings, self-healing rings, meashed SDH/SONET networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W40/00—Communication routing or communication path finding
- H04W40/02—Communication route or path selection, e.g. power-based or shortest path routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W40/00—Communication routing or communication path finding
- H04W40/02—Communication route or path selection, e.g. power-based or shortest path routing
- H04W40/18—Communication route or path selection, e.g. power-based or shortest path routing based on predicted events
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W40/00—Communication routing or communication path finding
- H04W40/24—Connectivity information management, e.g. connectivity discovery or connectivity update
- H04W40/246—Connectivity information discovery
Abstract
The invention discloses a kind of the whole network clock topology and clock method for obtaining path.The whole network clock topology acquisition methods of the present invention input 2, extract all links of the whole network clock topology according to the whole network clock information；According to the link and the whole network network element topology, that is, 1 is inputted, extract the details of all clock topology links, that is, input 3；The whole network clock topology is obtained according to input 3.The whole network clock path acquisition methods of the present invention judge the role of each network element by input 2；Then ASG aggregation nodes are deleted, is come out all nodes and link traversal of rest network by DFS, the direct-connected ASG of rest network is found out by input 3；The shortest path of all CSG to ASG is calculated with dijkstra's algorithm, and obtains the hop count of every shortest path.Agreement that the present invention supports network element and number of paths and network element, message, mechanism of giving out a contract for a project are unlimited, can be adapted for the network of any scale, application scenarios are more extensive.
Description
Technical field
The present invention relates to wireless communication technology field more particularly to the acquisition sides of a kind of the whole network clock topology and clock path
Method.
Background technology
Wireless backhaul net Backhaul nets are to connect base station to base station controller or the network of IP CORE, originally main
It is SDH, it is most of at present to have been substituted by IP device.Due to the fast development of mobile service, in wireless backhaul net
Number of devices is more and more.And mobile service requirement Clock Synchronization Technology, 2,3G requirement Frequency Synchronization, 4G requirement time synchronization,
And network construction period requires each base station to support that GPS clock source can cause networking with high costs, while have safety to ask again
It inscribes (GPS is the global positioning system in the U.S.), this requires the equipment of Backhaul all supports Clock Synchronization Technology, base station can be with
From transmission signal in extract clock, and then reach the whole network clock synchronize, the current network equipment can support mostly 1588v2,
ACR, synchronous ether isochronon simultaneous techniques.
Transmission device in the RAN networks of one large size city will reach 5000,6,000,000, therefore can exist in network
Multiple clock sources, especially most Clock Synchronization Technology, such as synchronous ether, 1588v2 have hop count limitation, and hop count is longer
Error is bigger, and then influences the quality of mobile service.Therefore, network O＆M personnel have in time understand the whole network clock open up
It flutters, includes the clock path of every network element, determine every network element to the hop count of clock source, so as to discover whether beyond threshold
Value, if be the bottleneck point for influencing mobile service.The network structure of Backhaul is as shown in Figure 1.
The NE quantity of Bckhaul networks is numerous, if it is to be understood that the clock path of every network element, one of method are
Artificial enquiry, but thousands of equipment are manually inquired, and workload is huge, and can not real-time update.
It is found about clock topology, industry mainly has following technology：
Technology 1：Network element obtains the location information of the network element by 1588 agreements；The network element sends out the location information
The management equipment is given, so that the management equipment generates the clock topology of the network according to the location information.
The location information that the technology obtains network element by 1588, since network element all supports 1588 agreements, has good compatibility.Management
Equipment generates clock topology according to location information, does not depend on the physical topological structure of network element, is easier to operate.
Technology 2：Ring network topology structure with common clock, including central controller and multiple child nodes, center
Controller in host node and multiple child nodes as being both provided with FPGA, the first transceiver module and the second transceiver module；FPGA with
Its corresponding first transceiver module and the electrical connection of the second transceiver module；First transceiver module is as clock signal transceiver interface, and
Two transceiver modules are as data-signal transceiver interface；Multiple first transceiver modules are in turn connected to form clock looped network；Clock looped network
Common clock is transmitted for whole network, common clock is sent out by host node, while each child node receives clock, sent out
It is sent to next lower node；Multiple second transceiver modules are in turn connected to form data-signal looped network；Data-signal looped network is used for transmitting
Serial data signal.The technology can substantially save the network communication time, improve the efficiency of looped network communication.
Technology 3：The method of refresh clock synchronous topology and determining clock synchronous path, including receiving from the first network element
The first message, the information of the clock synchronizing capacity of first message including first network element, first network element is the
Network element in one network, first network element have clock synchronizing capacity；According to the clock synchronizing capacity of first network element
Information updates the clock synchronous topology of the first network.Further, this method further includes asking according to first network element
It asks, is determined to inject node to first network element from the clock of the first network according to the clock synchronous topology of first network
First clock synchronous path.By the information automatically according to network element clock synchronizing capacity, refresh clock synchronous topology determines clock
Synchronous path reduces the cost of clock synchronous path deployment.
The shortcomings that technology 1：It is required that all devices all support 1588 agreements in network, but for Backhaul networks due to number
Measure huge, therefore the transmission device specification for hanging base station is relatively low, and type is various (including microwave, SDH, interchanger etc.), not necessarily
Support 1588 agreements or different type, 1588 agreement of the equipment of different vendor that cannot dock, the scene that technology 1 is caused to be applied
It is limited.
The shortcomings that technology 2：Only in ring topology, it is impossible to which applied to tree-like or net dress topology, and this technology is
A kind of annular clock topology is invented, is not clock topology discovery technique.
The shortcomings that technology 3：It is a kind of topological update method, message is updated by hair to determine clock path.This requirement
The equipment of different type, different vendor in Backhaul networks all supports this message and mechanism of giving out a contract for a project, application scenarios are limited,
And frequently give out a contract for a project and equipment performance may be impacted, and then influence mobile service quality.
Invention content
In order to solve the above technical problem, the present invention provides a kind of the whole network clock topology and clock method for obtaining path,
It is pinpointed the problems with solving the clock topology in wireless backhaul Backhaul networks.
In a first aspect, the present invention provides a kind of the whole network clock topology acquisition methods, including：
According to the whole network clock information, that is, 2 are inputted, extract all links of the whole network clock topology；
According to the link and the whole network network element topology, that is, 1 is inputted, extract the details of all clock topology links, institute
Details are stated as input 3；
The whole network clock topology is obtained according to input 3.
Preferably, title and each network element of the input 1 including network element each in the whole network are connected with other network elements
Interface message.
Preferably, the input 2 includes each title of network element and clock source interface message in the whole network.
Preferably, the input 1 is exported by network management system.
Preferably, the input 2 is exported by Clock management server.
Preferably, the details of all clock topology links are extracted according to the link and input 1, including：
According to input 2 in element name and clock interface information, to input 1 in search respective links opposite end network element and
Interface message generates the details of the whole network clock topology.
Second aspect, the present invention also provides a kind of clock path acquisition sides based on above-mentioned the whole network clock topology acquisition methods
Method, including：
The role of each network element is judged by input 2, judgment rule is：The network element for connecting clock server is aggregation node
ASG, other network elements are access node CSG；
ASG aggregation nodes in the whole network clock topology are deleted, by DFS by all nodes and link time of rest network
It goes through out, the rest network is known as subnet 1；
The direct-connected ASG of subnet 1 is found out by input 3；
The shortest path of all CSG to ASG is calculated with dijkstra's algorithm, and obtains the shortest path of each CSG to ASG
Hop count.
The third aspect, the present invention also provides a kind of the whole network clock topology acquisition device, including：
Link module is set as extracting all links of the whole network clock topology according to the whole network clock information；
Information module is set as, according to the link and the whole network network element topology, extracting the detailed of all clock topology links
Information；
Topography module is set as obtaining the whole network clock topology according to the details.
The present invention reversely calculates the whole network clock topology and clock path by dynamic clock information, will be in IP routing protocol
Shortest path first (Dijkstra) is applied in clock topology discovery, with the principle of simulation of Flow Analysis, according to network
The static configuration information (topology) of management system, disposably analyzes the clock topology and clock path of the whole network, saves a large amount of people
Power material resources.Simultaneously because based on service configuration information, therefore analysis result complies fully with the true path of clock business.To the whole network
Network element and number of paths and network element agreement, message, the mechanism of giving out a contract for a project supported it is unlimited, can be adapted for any scale
Network, application scenarios are more extensive.
Description of the drawings
Attached drawing is used for providing further understanding technical solution of the present invention, and a part for constitution instruction, with this
The embodiment of application technical solution for explaining the present invention together, does not form the limitation to technical solution of the present invention.
Fig. 1 is the Backhaul schematic network structures mentioned in background technology；
Fig. 2 is a kind of flow chart of the whole network clock topology acquisition methods of the embodiment of the present invention；
Fig. 3 is the group network topological structure schematic diagram of the embodiment of the present invention；
Fig. 4 is two equative routes of the RouterA of the embodiment of the present invention；
Fig. 5 is the clock topology schematic diagram of the embodiment of the present invention；
Fig. 6 is the 3 corresponding topological structure schematic diagram of input of the embodiment of the present invention；
Fig. 7 is the flow of the clock path acquisition methods based on the whole network clock topology acquisition methods of the embodiment of the present invention
Figure；
Fig. 8 is the 1 corresponding clock topology schematic diagram of subnet of the embodiment of the present invention；
Fig. 9 is the TopN routing informations shown by HTML Canvas plug-in units of the embodiment of the present invention；
Figure 10 is a kind of structure diagram of the whole network clock topology acquisition device of the embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature mutually can arbitrarily combine.
Technical scheme of the present invention is described in detail below by specific embodiment.
Embodiment one
Fig. 2 is a kind of flow chart of the whole network clock topology acquisition methods provided in an embodiment of the present invention.As shown in Fig. 2, this
The whole network clock topology acquisition methods of inventive embodiments may include steps of：
S101, according to the whole network clock information, that is, input 2, extract all links of the whole network clock topology；
S102, according to the link and the whole network network element topology, that is, input 1, extract the detailed letter of all clock topology links
Breath, the details are input 3；
S103, the whole network clock topology is obtained according to input 3.
Optionally, on the basis of above-described embodiment, the input 1 in the embodiment of the present invention in S102 can include in the whole network
The interface message that the title of each network element and each network element are connected with other network elements.
Optionally, on the basis of above-described embodiment, the input 2 in the embodiment of the present invention in S101 can include in the whole network
Each title of network element and clock source interface message.
Optionally, on the basis of above-described embodiment, the input 1 in the embodiment of the present invention in S102 can pass through webmaster system
System export.
Optionally, on the basis of above-described embodiment, the input 2 in the embodiment of the present invention in S101 can pass through clock pipe
Manage server export.
Optionally, in the embodiment of the present invention S102 realization method, can include：
According to input 2 in element name and clock interface information, to input 1 in search respective links opposite end network element and
Interface message generates the details of the whole network clock topology.
The present embodiment illustrates the whole network clock topology acquisition side of the embodiment of the present invention by taking networking topology shown in Fig. 3 as an example
Method.
The whole network router topology is exported by network management system first, as shown in table 1.
Table 1：Input 1
| Node 1 | Node 1- interfaces | Node 2 | Node 2- interfaces |
| RouterA | GE0/0/1 | RouterB | GE0/0/1 |
| RouterB | GE0/0/2 | RouterC | GE0/0/2 |
| RouterC | GE0/0/1 | RouterD | GE0/0/1 |
| RouterC | GE0/0/3 | RouterG | GE0/0/1 |
| RouterD | GE0/0/2 | RouterE | GE0/0/2 |
| RouterE | GE0/0/1 | RouterF | GE0/0/1 |
| RouterF | GE0/0/2 | RouterG | GE0/0/2 |
| RouterH | GE0/0/1 | RouterC | GE0/0/4 |
| RouterH | GE0/0/2 | RouterE | GE0/0/2 |
It should be noted that the webmaster due to router device manufacturer possibly can not find router to clock service automatically
The link of device, the terminal in such clock topology path is exactly RouterE, i.e., the first of clock server jumps direct-connected router.
In the embodiment of the present invention, the clock information that the whole network is exported by Clock management server is as shown in table 2.Table 2 provides
Every router is used to obtain the interface index of clock signal.
Table 2：Input 2
Then according to all links of 2 extraction clock topology of input.Clock topology is a subset of actual physical topology.
It, generally can there are redundant link or equative routes in order to increase reliability in live network.As shown in figure 4, two void in figure
Thread path is exactly equative route (assuming that taking for every section of link is identical) for RouterA.For RouterA, this
Two paths take it is identical, when clock signal is obtained only can at random from two shortest paths choose one, generation it is defeated
Enter 2 dynamic clock signal acquisition information.The present embodiment of the present invention is when calculating clock topology, according to the node name in input 2
Claim and clock interface, then to the opposite end network element and interface message of this link is searched in input 1, generate the clock topology of the whole network
Details input 3, as shown in table 3, as shown in Figure 5 according to the clock topology that the input 3 is drawn.
Table 3：Input 3：
| Node 1 | Node 1- interfaces | Node 2 | Node 2- interfaces |
| RouterA | GE0/0/1 | RouterB | GE0/0/1 |
| RouterB | GE0/0/2 | RouterC | GE0/0/2 |
| RouterC | GE0/0/1 | RouterD | GE0/0/1 |
| RouterC | GE0/0/3 | RouterG | GE0/0/1 |
| RouterD | GE0/0/2 | RouterE | GE0/0/2 |
| RouterE | GE0/0/1 | RouterF | GE0/0/1 |
| RouterF | GE0/0/2 | RouterG | GE0/0/2 |
From the point of view of the dynamic clock signal acquisition information of input 2, the both links of RouterH are not included in clock topology
In (assuming that RouterH is only transmission node, not access service), therefore can ensure that the present embodiment of the present invention calculates when
Clock path is completely the same with the true clock path information of existing net, and the whole network clock topology finally obtained is as shown in Figure 6.
The whole network clock topology acquisition methods of the embodiment of the present invention are off-line analysis method --- pass through full mesh topology (input
1) and clock signal obtains information (input 2) to calculate the clock topology of the whole network --- therefore to the network element and number of paths of the whole network
And agreement, message, the mechanism of giving out a contract for a project that network element is supported are unlimited, can be adapted for the network of any scale, application scenarios
More extensively.
Embodiment two
Fig. 7 is a kind of clock path acquisition methods based on the whole network clock topology acquisition methods provided in an embodiment of the present invention
Flow chart.As shown in fig. 7, the clock path acquisition methods based on the whole network clock topology acquisition methods of the present embodiment, including：
S201, the role that each network element is judged by input 2, judgment rule are：The network element of clock server is connected to converge
Poly- node ASG, other network elements are access node CSG, and judging result is as shown in table 4.
Table 4：Network element role judging result
| Device name | Network element role |
| RouterA | CSG |
| RouterB | CSG |
| RouterC | CSG |
| RouterD | CSG |
| RouterE | ASG |
| RouterF | CSG |
| RouterG | CSG |
S202, the ASG aggregation nodes in the whole network clock topology are deleted, by DFS by all nodes of rest network and
Link traversal comes out, and the rest network is known as subnet 1, and as shown in table 5, corresponding clock topology is as shown in Figure 8.
Table 5：Subnet 1
| Subnet ID | CSG |
| 1 | RouterA,RouterB,RouterC,RouterD,RouterF,RouterG |
S203, the direct-connected ASG of subnet 1 is found out by input 3, that is, traverses all CSG in subnet 1, see its whether have with
The direct connected link of ASG exports following table.
Table 6：The direct-connected ASG with subnet 1
S204, the shortest path that all CSG to ASG are calculated with dijkstra's algorithm, and obtain each CSG to ASG most
The hop count of short path, obtains that the results are shown in Table 7.
Table 7：The shortest path of all CSG to ASG and corresponding hop count
| Path | Hop count |
| RouterA->RouterB->RouterC->RouterD->RouterE | 4 |
| RouterB->RouterC->RouterD->RouterE | 3 |
| RouterC->RouterD->RouterE | 2 |
| RouterD->RouterE | 1 |
| RouterF->RouterE | 1 |
| RouterG->RouterF->RouterE | 2 |
It should be noted that TopN (route jumping figure length) routing information in the embodiment of the present invention can be in HTML
It is shown on Canvas (topology is presented) plug-in unit, more vivid presentation is carried out in SOC or network management control center, such as Fig. 9 institutes
Show.
The present embodiment of the present invention is when calculating clock path, in order to avoid dijkstra's algorithm result of calculation selection twice
Shortest path is inconsistent, so nodename and clock interface in input 2, then search this link to inputting in 1
Opposite end network element and interface message generate the details of the clock topology of the whole network.
The whole network clock path acquisition methods of the embodiment of the present invention are off-line analysis method --- pass through full mesh topology (input
1) and clock signal obtains information (input 2) to calculate the clock path of the whole network --- therefore to the network element and number of paths of the whole network
And agreement, message, the mechanism of giving out a contract for a project that network element is supported are unlimited, can be adapted for the network of any scale, application scenarios
More extensively.
Embodiment three
Figure 10 is a kind of structure diagram of the whole network clock topology acquisition device provided in an embodiment of the present invention, including：
Link module is set as according to the whole network clock information, that is, inputs 2, extracts all links of the whole network clock topology；
Information module is set as according to the link and the whole network network element topology, that is, inputting 1, extracts all clock topology chains
The details on road, the details are input 3；
Topography module is set as obtaining the whole network clock topology according to input 3.
Preferably, title and each network element of the input 1 including network element each in the whole network are connected with other network elements
Interface message.
Preferably, the input 2 includes each title of network element and clock source interface message in the whole network.
Preferably, the input 1 is exported by network management system.
Preferably, the input 2 is exported by Clock management server.
Preferably, described information module extracts the details of all clock topology links according to the link and input 1,
Including：
According to input 2 in element name and clock interface information, to input 1 in search respective links opposite end network element and
Interface message generates the details of the whole network clock topology.
One of ordinary skill in the art will appreciate that all or part of step in the above method can be referred to by program
Related hardware (such as processor) is enabled to complete, described program can be stored in computer readable storage medium, such as read-only storage
Device, disk or CD etc..Optionally, all or part of step of above-described embodiment can also use one or more integrated circuits
To realize.Such as its corresponding function is realized by integrated circuit, it can also be realized in the form of software function module, such as
The program/instruction being stored in memory is performed by processor to realize its corresponding function.The embodiment of the present invention is not limited to
The combination of the hardware and software of any particular form.
Although disclosed herein embodiment as above, the content only for ease of understanding the present invention and use
Embodiment is not limited to the present invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (8)
1. a kind of the whole network clock topology acquisition methods, which is characterized in that including：
According to the whole network clock information, all links of the whole network clock topology are extracted；
According to the link and the whole network network element topology, the details of all clock topology links are extracted；
The whole network clock topology is obtained according to the details.
2. the whole network clock topology acquisition methods according to claim 1, which is characterized in that the whole network network element topology includes
The interface message that the title of each network element and each network element are connected with other network elements in the whole network.
3. the whole network clock topology acquisition methods according to claim 2, which is characterized in that the whole network clock information includes
The title and clock source interface message of each network element in the whole network.
4. the whole network clock topology acquisition methods according to claim 2, which is characterized in that the whole network network element topology passes through
Network management system exports.
5. the whole network clock topology acquisition methods according to claim 3, which is characterized in that the whole network clock information passes through
Clock management server exports.
6. the whole network clock topology acquisition methods according to claim 3, which is characterized in that according to the link and the whole network net
First topology extracts the details of all clock topology links, including：
Element name and clock interface information in the whole network clock information, the lookup pair into the whole network network element topology
The opposite end network element and interface message of link are answered, generates the details of the whole network clock topology.
7. the clock path acquisition methods based on the whole network clock topology acquisition methods described in claim 1, which is characterized in that packet
It includes：
The role of each network element is judged by the whole network clock information, judgment rule is：The network element for connecting clock server is convergence
Node ASG, other network elements are access node CSG；
ASG aggregation nodes in the whole network clock topology are deleted, are gone out all nodes and link traversal of rest network by DFS
Come, the rest network is known as subnet 1；
The direct-connected ASG of the subnet 1 is found out by the details；
The shortest path of all CSG to ASG is calculated with dijkstra's algorithm, and obtains the jump of the shortest path of each CSG to ASG
Number.
8. a kind of the whole network clock topology acquisition device, which is characterized in that including：
Link module is set as extracting all links of the whole network clock topology according to the whole network clock information；
Information module is set as, according to the link and the whole network network element topology, extracting the details of all clock topology links；
Topography module is set as obtaining the whole network clock topology according to the details.
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| RU2801116C2 (en) * | 2019-03-29 | 2023-08-02 | Хуавэй Текнолоджиз Ко., Лтд. | Communication device and communication method |
| CN110865962A (en) * | 2019-10-09 | 2020-03-06 | 北京空间机电研究所 | Dynamically configurable high-precision and high-reliability clock network |
| CN113542127A (en) * | 2021-06-10 | 2021-10-22 | 新华三大数据技术有限公司 | Method and device for searching topology of single VXLAN of non-role VTEP node |
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