CN108170317B

CN108170317B - Array substrate

Info

Publication number: CN108170317B
Application number: CN201810013936.6A
Authority: CN
Inventors: 王智勇; 徐帅; 王阔海; 朱红
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2018-01-05
Filing date: 2018-01-05
Publication date: 2021-01-26
Anticipated expiration: 2038-01-05
Also published as: CN108170317A

Abstract

The embodiment of the invention provides an array substrate, relates to the technical field of display, and can improve touch performance. An array substrate, comprising: the display device comprises a display area and a peripheral wiring area positioned on the periphery of the display area; the display area is provided with a touch electrode; the peripheral wiring area is provided with an anti-static wiring, the anti-static wiring is arranged around the display area and is used for being electrically connected with the static discharge electrode; the anti-static routing wire is provided with at least one disconnected part; the anti-static protection circuits are in one-to-one correspondence with the disconnected parts, and the anti-static protection circuits in one-to-one correspondence are electrically connected with two ends of the disconnected parts; the anti-static protection circuit is used for electrically connecting two ends of the disconnection part when static electricity occurs so as to lead the static electricity out to the static electricity discharge electrode; when no static electricity occurs, both ends of the breaking portion are broken.

Description

Array substrate

Technical Field

The invention relates to the technical field of display, in particular to an array substrate.

Background

With the rapid development of display technology, the birth of Touch Panel (TP) makes the life of people more convenient.

The embedded capacitive touch screen integrates a touch electrode structure in a display panel, has the advantages of simple structure, light weight, thinness and low cost, and is increasingly becoming the mainstream technology of the touch screen, for example, the embedded capacitive touch screen is increasingly widely applied to various portable intelligent terminals (such as mobile phones).

Disclosure of Invention

Embodiments of the present invention provide an array substrate, which can improve touch performance.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, an array substrate is provided, including: the display device comprises a display area and a peripheral wiring area positioned on the periphery of the display area; the display area is provided with a touch electrode; the peripheral wiring area is provided with an anti-static wiring, the anti-static wiring is arranged around the display area and is used for being electrically connected with the static discharge electrode; the anti-static routing wire is provided with at least one disconnected part; the anti-static protection circuits are in one-to-one correspondence with the disconnected parts, and the anti-static protection circuits in one-to-one correspondence are electrically connected with two ends of the disconnected parts; the anti-static protection circuit is used for electrically connecting two ends of the disconnection part when static electricity occurs so as to lead the static electricity out to the static electricity discharge electrode; when no static electricity occurs, both ends of the breaking portion are broken.

The anti-static protection circuits which are in one-to-one correspondence are arranged on the disconnection parts of the anti-static wiring, and two signal ends of each anti-static protection circuit are electrically connected with two ends, namely the first end and the second end, of the corresponding disconnection part, so that when static electricity occurs, the first end and the second end are electrically connected through the anti-static protection circuits, and static electricity can be led out to the static electricity release electrode to be released; when no static electricity occurs, the first end and the second end are disconnected through the anti-static protection circuit, and the anti-static wiring disconnected with the static electricity release electrode is suspended, so that the suspended anti-static wiring can be synchronously changed along with signals on the touch electrode in a touch control stage, interference on the signals on the touch electrode is avoided, and the touch performance can be improved.

Preferably, the anti-static wire has two disconnected portions; the two disconnection parts are oppositely arranged and are close to the connection end of the anti-static routing wire, which is used for being connected with the static discharge electrode.

Preferably, the anti-static protection circuit includes a first transistor and a second transistor; a gate and a source of the first transistor are electrically connected to a drain of the second transistor; the gate and source of the second transistor are electrically connected to the drain of the first transistor.

Further preferably, the gate of the first transistor and the gate of the second transistor are disposed in the same layer; the source and the drain of the first transistor are arranged on the same layer as the source and the drain of the second transistor.

Preferably, the touch electrodes located in the display area are arranged in an array, and the display area further includes a first signal line electrically connected to the touch electrodes; the peripheral wiring area is also provided with a dummy touch electrode and a second signal line electrically connected with the dummy touch electrode; the dummy touch electrode is disposed adjacent to the display area.

Further preferably, the number of the dummy touch electrodes is multiple, and the multiple dummy touch electrodes and the touch electrodes are arranged in an array; along a first direction, the lengths of the dummy touch electrodes and the touch electrodes in the same row along a second direction are the same; along the second direction, the widths of the dummy touch electrodes and the touch electrodes in the same column along the first direction are the same; the first direction and the second direction are perpendicular.

In another aspect, an array substrate is provided, including: the display device comprises a display area and a peripheral wiring area positioned on the periphery of the display area; the display area is provided with a plurality of touch electrodes arranged in an array manner and a first signal wire electrically connected with the touch electrodes; the peripheral wiring area is also provided with a dummy touch electrode and a second signal line electrically connected with the dummy touch electrode; the dummy touch electrode is disposed adjacent to the display area.

When the touch electrodes are only arranged in the display area, the touch electrodes at the edge of the display area have certain difference from the touch electrodes at the non-edge area of the display area in terms of electrical characteristics under the influence of the boundary effect, and the difference is more obvious under the influence of the external environment and other components. In the embodiment of the invention, the dummy touch electrode and the second signal line electrically connected with the dummy touch electrode are arranged in the peripheral wiring area, so that signals can be respectively applied to the touch electrode and the dummy touch electrode through the first signal line and the second signal line, and the influence on the boundary of the touch electrode is shielded by the dummy touch electrode positioned on the edge; in addition, the dummy touch electrode can also shield the influence of circuits and wires below the dummy touch electrode on the touch electrode, so that the working environments of the touch electrodes are the same, and the touch precision of the product is improved.

Preferably, the number of the dummy touch electrodes is multiple, and the multiple dummy touch electrodes and the touch electrodes are arranged in an array; along a first direction, the lengths of the dummy touch electrodes and the touch electrodes in the same row along a second direction are the same; along the second direction, the widths of the dummy touch electrodes and the touch electrodes in the same column along the first direction are the same; the first direction and the second direction are perpendicular.

Preferably, the dummy touch electrode and the touch electrode are disposed in the same layer.

Preferably, the first signal line includes a first sub-signal line and a second sub-signal line that are stacked and electrically connected; the second signal line includes a third sub-signal line and a fourth sub-signal line that are stacked and electrically connected; the first sub-signal line and the third sub-signal line are arranged in the same layer; the second sub-signal line and the fourth sub-signal line are arranged in the same layer.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1a is a first schematic top view of an array substrate according to the present invention;

fig. 1b is a schematic top view of an array substrate according to the present invention;

fig. 1c is a schematic top view of an array substrate according to the present invention;

fig. 2 is a schematic circuit structure diagram of an anti-static protection circuit according to the present invention;

FIG. 3a is a first schematic diagram illustrating an electrostatic discharge path of the ESD protection circuit of FIG. 2;

FIG. 3b is a schematic diagram of a second electrostatic discharge path of the ESD protection circuit in FIG. 2;

FIGS. 4a to 4c are schematic diagrams illustrating a process of fabricating an anti-static protection circuit;

fig. 5 is a schematic top view of an array substrate according to the present invention;

fig. 6 is a schematic top view of an array substrate according to a fifth embodiment of the present invention;

fig. 7 is a schematic top view illustrating a sixth exemplary embodiment of an array substrate according to the present invention;

fig. 8 is a schematic top view illustrating an array substrate according to a seventh embodiment of the present invention;

fig. 9 is a schematic cross-sectional view of an array substrate according to the present invention;

fig. 10 is a schematic view of a display panel according to the present invention.

Reference numerals:

10-a display area; 20-a peripheral wiring region; 11-touch electrodes; 12-a first signal line; 21-antistatic routing; 22-an anti-static protection circuit; 23-a dummy touch electrode; 24-a second signal line; 121-first sub-signal line; 122-a second sub-signal line; 211-a connection end; 212-a first end; 213-a second end; 221-a first gate; 222-a second gate; 223 — a first semiconductor layer; 224-a second semiconductor layer; 225-first source; 226-a first drain; 227-a second source; 228-a second drain; 241-a third sub-signal line; 242-a fourth sub-signal line; t1 — first transistor; t2 — second transistor.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides an array substrate, as shown in fig. 1a, 1b, and 1c, including: a display area 10 and a peripheral wiring area 20 located at the periphery of the display area 10; the display area 10 is provided with touch electrodes (not shown in fig. 1); the peripheral wiring region 20 is provided with an anti-static wiring 21, the anti-static wiring 21 is arranged around the display region 10, and the anti-static wiring 21 is used for being electrically connected with the electrostatic discharge electrode; the anti-static wire 21 has at least one disconnected portion; the anti-static protection circuits 22 are in one-to-one correspondence with the disconnected portions, and the anti-static protection circuits 22 in one-to-one correspondence are electrically connected with two ends of the disconnected portions; the anti-static protection circuit 22 is used for electrically connecting two ends of the disconnection part when static electricity occurs so as to lead the static electricity to the static electricity discharge electrode; when no static electricity occurs, both ends of the breaking portion are broken.

As shown in fig. 1a to 1c, the anti-static trace 21 can be electrically connected to the electrostatic discharge electrode through at least one connection end 211 located at one side of the display region 10.

First, the electrostatic discharge electrode may be a ground where copper is laid on a large area of an FPC (Flexible Printed Circuit); alternatively, the electrostatic discharge electrode is a metal back plate of the backlight, and the anti-static trace 21 may be connected to the metal back plate through a conductive tape.

Secondly, the anti-static wire 21 is disposed around the display area 10, and may be entirely closed except for the open portion formed for disposing the anti-static protection circuit 22 as shown in fig. 1 b. In this case, only one connection end 211 may be provided.

As shown in fig. 1a and 1c, the whole of the anti-static wiring 21 may not be completely closed except for the open portion formed for disposing the anti-static protection circuit 22. That is, the shape of the anti-static trace 21 is similar to a "C" shape. In this case, as shown in fig. 1a, only one connection end 211 may be provided; alternatively, as shown in fig. 1c, two connection ends 211 may be provided.

In the case shown in fig. 1a, except for the disconnected portion formed by disposing the anti-static protection circuit 22, the anti-static trace 21 has an open end without being closed, and one end is a connection end 211, and the other end is suspended. Whereas for the situation shown in fig. 1c, at the non-closed opening both ends are connection ends 211.

Second, both ends of any one of the disconnected portions are a first end 212 and a second end 213, respectively. The electrostatic protection circuits 22 in one-to-one correspondence are electrically connected to both ends of the disconnection portion, that is, the electrostatic protection circuits 22 have two signal terminals electrically connected to the first terminal 212 and the second terminal 213 of the disconnection portion, respectively, to ensure non-electrical connection of the first terminal 212 and the second terminal 213 when no static electricity occurs.

For example, in the case that the anti-static wiring 21 has two disconnected portions, which may be referred to as a first disconnected portion and a second disconnected portion, one anti-static protection circuit 22 is electrically connected to the first end 212 and the second end 213 of the first disconnected portion, and the other anti-static protection circuit 22 is electrically connected to the first end 212 and the second end 213 of the second disconnected portion.

The embodiment of the invention provides an array substrate, wherein the anti-static protection circuits 22 corresponding to each other one by one are arranged at the disconnected part of the anti-static wiring 21, and two signal ends of the anti-static protection circuit 22 are electrically connected with two ends of the corresponding disconnected part, namely the first end 212 and the second end 213, so that when static electricity occurs, the first end 212 and the second end 213 are electrically connected through the anti-static protection circuit 22, and the static electricity can be led out to a static electricity discharge electrode to be released; when no static electricity occurs, the first end 212 and the second end 213 are disconnected by the anti-static protection circuit 22, and the anti-static trace 21 disconnected from the static electricity discharge electrode is suspended, so that the suspended anti-static trace 21 can change synchronously with the signal on the touch electrode in the touch stage, thereby avoiding interference on the signal on the touch electrode and improving the touch performance.

Compared with the IC controlling the anti-static wire 21 to be suspended or grounded, the embodiment of the invention can avoid the problem that the overall anti-static capability is greatly reduced.

Preferably, as shown in fig. 1b and 1c, the anti-static wire 21 has two disconnected portions; the two disconnected portions are disposed opposite to each other and close to the connection end 211 of the anti-static wire 21 for connecting with the electrostatic discharge electrode.

Wherein, when there are two connection terminals 211, one disconnection portion is disposed adjacent to one connection terminal 211, and the other disconnection portion is disposed adjacent to the other connection terminal 211.

It should be noted that the two disconnected portions are oppositely disposed, and the two disconnected portions may be disposed on two sides of the opening that is not closed except the disconnected portion formed by disposing the anti-static protection circuit 22 on the anti-static trace 21.

On one hand, when no static electricity occurs, the anti-static wiring 21 with most length can be suspended, and the anti-static wiring changes synchronously with the signal on the touch electrode in the touch control stage, so that the whole touch control performance can be greatly improved; on the other hand, the electrostatic discharge effect can be made better.

Preferably, as shown in fig. 2, the electrostatic protection circuit 22 includes a first transistor T1 and a second transistor T2; the gate and source of the first transistor T1 are electrically connected to the drain of the second transistor T2; the gate and source of the second transistor T2 are electrically connected to the drain of the first transistor T1.

When the first transistor T1 and the second transistor T2 are both N-type transistors, when the array substrate is interfered by static electricity, the first transistor T1 can be turned on by the static electricity in the forward direction, and as shown in fig. 3a, the static electricity is led out to the static electricity discharge electrode through the first transistor T1 to discharge the static electricity; the negative static electricity can turn on the second transistor T2, and is led out to the static electricity discharging electrode through the second transistor T2 to discharge the static electricity, as shown in fig. 3 b.

Of course, it is understood that when the first transistor T1 and the second transistor T2 are both P-type transistors, the situation is reversed.

In addition, in the transistor, two poles other than the gate are referred to as a source and a drain, respectively.

Further preferably, the gate of the first transistor T1 is disposed at the same level as the gate of the second transistor T2; the source and drain of the first transistor T1 are disposed at the same level as the source and drain of the second transistor T2. This can avoid an increase in the number of patterning processes.

Taking the first transistor T1 and the second transistor T2 as transistors of a bottom gate type structure as an example, forming the first transistor T1 and the second transistor T2 may include the steps of: first, a first metal film layer is formed, and two opposite gates as shown in fig. 4a, namely a first gate 221 and a second gate 222, are formed through a one-step patterning process; then, sequentially forming a gate insulating layer and a semiconductor film layer, forming a first semiconductor layer 223 and a second semiconductor layer 224 as shown in fig. 4b through one or two patterning processes, wherein the first semiconductor layer 223 and the second semiconductor layer 224 are respectively located above the first gate 221 and the second gate 222, and forming via holes above the first gate 221 and the second gate 222 of the gate insulating layer; then, a second metal film layer is formed, and through a one-step patterning process, a first source 225, a first drain 226, a second source 227, and a second drain 228 as shown in fig. 4c are formed, such that the first source 225 is electrically connected to the first gate 221 through a via, the second drain 228 is electrically connected to the first gate 221 through a via, the second source 227 is electrically connected to the second gate 222 through a via, and the first drain 226 is electrically connected to the second gate 222 through a via. On this basis, a protective layer may also be formed over the first source 225, the first drain 226, the second source 227, and the second drain 228.

Here, it is understood that the first gate electrode 221, the gate insulating layer, the first semiconductor layer 223, the first source electrode 225, and the first drain electrode 226 constitute a first transistor T1; the second gate electrode 222, the gate insulating layer, the second semiconductor layer 224, the second source electrode 227, and the second drain electrode 228 constitute a first transistor T2.

It should be noted that the gate of the first transistor T1 and the gate of the second transistor T2 may also be disposed on the same layer as the gate metal layer of the display region 10; the source and drain electrodes of the first transistor T1 and the source and drain electrodes of the second transistor T2 may also be disposed at the same level as the source and drain metal layers of the display region 10.

On the basis, as shown in fig. 5 and fig. 6, preferably, the touch electrodes 11 located in the display area 10 are arranged in an array, and the display area 10 further includes a first signal line 12 electrically connected to the touch electrodes 11; the peripheral wiring region 20 is further provided with a dummy touch electrode 23 and a second signal line 24 electrically connected to the dummy touch electrode 23; the dummy touch electrode 23 is disposed adjacent to the display area 10.

The first signal line 12 and the second signal line 24 are electrically connected to an IC (Integrated Circuit) through which signals are supplied. The dummy touch electrode 23 and the touch electrode 11 are preferably disposed in the same layer.

Based on the arrangement of the touch electrode 11 and the first signal line 12, it can be understood that the array substrate of the embodiment of the invention performs touch recognition based on a self-contained method.

When the touch electrodes 11 are disposed only in the display area 10, the touch electrodes 11 located at the edge of the display area 10 have a certain difference in electrical characteristics from the touch electrodes 11 located at the non-edge area of the display area 10 due to the influence of the boundary effect, and the difference is made more obvious by the influence of the external environment and other components. In the invention, the dummy touch electrode 23 and the second signal line 24 electrically connected with the dummy touch electrode 23 are arranged in the peripheral wiring area 20, signals can be respectively applied to the touch electrode 11 and the dummy touch electrode 23 through the first signal line 12 and the second signal line 24, so that the influence on the boundary of the touch electrode 11 is shielded by the dummy touch electrode 23 positioned at the more edge; in addition, the dummy touch electrode 23 can also shield the circuit and trace under the dummy touch electrode from affecting the touch electrode 11, so that the working environment of the touch electrode 11 can be the same, which is beneficial to improving the touch accuracy of the product.

On this basis, the common electrode and the touch electrode 11 are preferably shared.

The self-contained touch structure is adopted, so that the matching with the original process flow on the array substrate is facilitated, and the manufacturing cost is lower; moreover, one chip can be used for display and touch control, so that the cost is further reduced.

More preferably, as shown in fig. 6, there are a plurality of dummy touch electrodes 23, and the plurality of dummy touch electrodes 23 and the touch electrode 11 are arranged in an array; along the first direction, the lengths of the dummy touch electrodes 23 and the touch electrodes 11 in the same row along the second direction are the same; in the second direction, the widths of the dummy touch electrodes 23 and the touch electrodes 11 in the same column in the first direction are the same; the first direction and the second direction are perpendicular.

The number of the dummy touch electrodes 23 is multiple, and the multiple dummy touch electrodes 23 and the touch electrodes 11 are arranged in an array, which may specifically be: arranging a dummy touch electrode 23 on each side of each row of touch electrodes 11 along the first direction; arranging a dummy touch electrode 23 on the side of each row of touch electrodes 11 far away from the IC binding area along the second direction; on the basis, the dummy touch electrode 23 can be arranged at other positions according to actual conditions.

The width of the dummy touch electrodes 23 in the same row along the first direction may be smaller than the width of the touch electrodes 11. The length of the dummy touch electrodes 23 in the same column along the second direction may be smaller than the length of the touch electrodes 11.

When the dummy touch electrodes 23 and the touch electrodes 11 are arranged in an array, the dummy touch electrodes 23 can be used for detecting the peripheral touch of the product when the interference of the external environment is small and the design optimization of the peripheral circuit is good.

The embodiment of the invention also provides a display panel which comprises the array substrate.

An embodiment of the present invention further provides an array substrate, as shown in fig. 7 and 8, including a display area 10 and a peripheral wiring area 20 located at the periphery of the display area 10; the display area 10 is provided with a plurality of touch electrodes 11 arranged in an array, and a first signal line 12 electrically connected with the touch electrodes 11; the peripheral wiring region 20 is further provided with a dummy touch electrode 23 and a second signal line 24 electrically connected to the dummy touch electrode 23; the dummy touch electrode 23 is disposed adjacent to the display area 10.

Based on the arrangement of the touch electrode 11 and the first signal line 12, it can be understood that the array substrate of the present invention performs touch recognition based on a self-contained method.

When the touch electrodes 11 are disposed only in the display area 10, the touch electrodes 11 located at the edge of the display area 10 have a certain difference in electrical characteristics from the touch electrodes 11 located at the non-edge area of the display area 10 due to the influence of the boundary effect, and the difference is made more obvious by the influence of the external environment and other components. In the embodiment of the invention, by disposing the dummy touch electrode 23 in the peripheral wiring area 20 and the second signal line 24 electrically connected to the dummy touch electrode 23, signals can be applied to the touch electrode 11 and the dummy touch electrode 23 through the first signal line 12 and the second signal line 24, respectively, so that the influence on the boundary of the touch electrode 11 is shielded by the dummy touch electrode 23 located at a more peripheral edge; in addition, the dummy touch electrode 23 can also shield the circuit and trace under the dummy touch electrode from affecting the touch electrode 11, so that the working environment of the touch electrode 11 can be the same, which is beneficial to improving the touch precision of the product.

The self-contained touch structure is adopted, so that the matching with the original process flow on the array substrate is facilitated, and the manufacturing cost is lower; moreover, one chip can be used for display and touch control, so that the cost can be further reduced.

Preferably, as shown in fig. 8, there are a plurality of dummy touch electrodes 23, and the dummy touch electrodes 23 and the touch electrodes 11 are arranged in an array; along the first direction, the lengths of the dummy touch electrodes 23 and the touch electrodes 11 in the same row along the second direction are the same; in the second direction, the widths of the dummy touch electrodes 23 and the touch electrodes 11 in the same column in the first direction are the same; the first direction and the second direction are perpendicular.

Preferably, the dummy touch electrode 23 is disposed on the same layer as the touch electrode 11. This can avoid an increase in the number of patterning processes.

Preferably, as shown in fig. 9, the first signal line 12 includes a first sub-signal line 121 and a second sub-signal line 122 that are stacked and electrically connected. The first and second sub-signal lines 121 and 122 may be electrically connected through vias. The second signal line 24 includes a third sub-signal line 241 and a fourth sub-signal line 242 that are stacked and electrically connected. The third sub-signal line 241 and the fourth sub-signal line 242 may be electrically connected through a via hole.

The first sub-signal line 121 and the third sub-signal line 241 are disposed in the same layer; the second sub-signal line 122 and the fourth sub-signal line 242 are disposed in the same layer. Thus, the resistances of the first signal line 12 and the second signal line 24 can be reduced.

An embodiment of the present invention further provides a display panel, as shown in fig. 10, including the array substrate; wherein the IC is electrically connected to the first signal line 12 and the second signal line 24 after the IC is bound at the binding region.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. An array substrate, comprising: the display device comprises a display area and a peripheral wiring area positioned on the periphery of the display area; the display area is provided with a touch electrode; the peripheral wiring area is provided with an anti-static wiring, the anti-static wiring is arranged around the display area and is used for being electrically connected with the static discharge electrode; the anti-static routing wire is provided with at least one disconnected part; the anti-static protection circuits are in one-to-one correspondence with the disconnected parts, and the anti-static protection circuits in one-to-one correspondence are electrically connected with two ends of the disconnected parts;

the anti-static protection circuit is used for electrically connecting two ends of the disconnection part when static electricity occurs so as to lead the static electricity out to the static electricity discharge electrode; when no static electricity occurs, both ends of the breaking portion are broken.

2. The array substrate of claim 1, wherein the anti-static trace has two disconnected portions;

the two disconnection parts are oppositely arranged and are close to the connection end of the anti-static routing wire, which is used for being connected with the static discharge electrode.

3. The array substrate of claim 1 or 2, wherein the anti-static protection circuit comprises a first transistor and a second transistor;

a gate and a source of the first transistor are electrically connected to a drain of the second transistor; the gate and source of the second transistor are electrically connected to the drain of the first transistor.

4. The array substrate of claim 3, wherein the gate of the first transistor is disposed on the same layer as the gate of the second transistor;

the source and the drain of the first transistor are arranged on the same layer as the source and the drain of the second transistor.

5. The array substrate of claim 1, wherein the touch electrodes in the display area are arranged in an array, and the display area further comprises a first signal line electrically connected to the touch electrodes;

the peripheral wiring area is also provided with a dummy touch electrode and a second signal line electrically connected with the dummy touch electrode; the dummy touch electrode is disposed adjacent to the display area.

6. The array substrate of claim 5, wherein the number of the dummy touch electrodes is multiple, and the multiple dummy touch electrodes and the touch electrodes are arranged in an array;

along a first direction, the lengths of the dummy touch electrodes and the touch electrodes in the same row along a second direction are the same; along the second direction, the widths of the dummy touch electrodes and the touch electrodes in the same column along the first direction are the same;

the first direction and the second direction are perpendicular.

7. The array substrate of claim 5, wherein the dummy touch electrode is disposed on the same layer as the touch electrode.

8. The array substrate of any one of claims 5 to 6, wherein the first signal line comprises a first sub-signal line and a second sub-signal line that are stacked and electrically connected;

the second signal line includes a third sub-signal line and a fourth sub-signal line that are stacked and electrically connected;

the first sub-signal line and the third sub-signal line are arranged in the same layer; the second sub-signal line and the fourth sub-signal line are arranged in the same layer.