CN108155911B - Non-uniform ultra-wideband sparse signal sampling method based on FPGA - Google Patents
Non-uniform ultra-wideband sparse signal sampling method based on FPGA Download PDFInfo
- Publication number
- CN108155911B CN108155911B CN201711258042.5A CN201711258042A CN108155911B CN 108155911 B CN108155911 B CN 108155911B CN 201711258042 A CN201711258042 A CN 201711258042A CN 108155911 B CN108155911 B CN 108155911B
- Authority
- CN
- China
- Prior art keywords
- sampling
- signal
- fpga
- signals
- pseudo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 201
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004422 calculation algorithm Methods 0.000 claims abstract description 19
- 238000011084 recovery Methods 0.000 claims abstract description 11
- 239000013598 vector Substances 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 230000006835 compression Effects 0.000 abstract description 31
- 238000007906 compression Methods 0.000 abstract description 31
- 238000001228 spectrum Methods 0.000 description 24
- 230000000694 effects Effects 0.000 description 11
- 230000006870 function Effects 0.000 description 11
- 239000011159 matrix material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000011161 development Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000002474 experimental method Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3059—Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression
- H03M7/3062—Compressive sampling or sensing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention discloses a non-uniform ultra-wideband sparse signal sampling method based on an FPGA (field programmable gate array), which solves the problems that the hardware of the conventional compression sampling method is difficult to realize and the traditional uniform sampling method is limited by the Nyquist theorem. The implementation steps are as follows: building a hardware platform; determining a sampling rate parameter; setting an AD sampling rate according to a required compression ratio; determining a pseudo-random symbol formula; generating a pseudo-random sequence; storing the pseudo-random sequence into an RAM of the FPGA; the non-uniform sampling of the sparse signals is completed by sending the signals through a gigabit transceiver in the FPGA and using the signals as a working clock of a sampling holder; the signal is reconstructed by a recovery algorithm. The invention can realize 10 times compression of the maximum 4GHz Nyquist sampling rate, and the rear end completes compression sampling of sparse signals in the 2GHz bandwidth range through the AD with the sampling rate of 400 MHz. The invention greatly reduces the complexity and the expense of the whole compression sampling system, is easy to realize in engineering, is applied to electronic reconnaissance and collects frequency domain sparse radar signals.
Description
Technical Field
The invention belongs to the technical field of signal sampling, mainly relates to a special compression sampling technology, and particularly relates to a non-uniform ultra wide band sparse signal sampling method based on an FPGA (field programmable gate array), which can be used for ultra wide band sparse signal acquisition.
Background
With the continuous development of electronic technology, nowadays, electromagnetic environments become increasingly complex and diversified, and the frequency bandwidth of signals needing to be processed by radar and electronic warfare systems is increased sharply. In the face of radio frequency signals with frequencies up to several GHz and even up to dozens of GHz, the digital receiver needs to use a plurality of ADC chips with extremely high sampling rates to acquire useful information from such a large frequency band range, which not only greatly increases the cost of research and development, data storage and transmission, but also in the ultra-wideband field, the performance of the existing chip can not meet the requirement of Nyquist sampling theorem at all.
The appearance of the compressed sensing theory (CS) brings great challenges to the conventional nyquist sampling theorem, and simultaneously brings a new solution to the difficulty of nyquist sampling. CS theory states that for sparse signals, all the information of the original signal can be acquired even if the signal is sampled at a sampling rate lower than the nyquist rate. So that the signal reconstruction can be done with great probability accurately on the original signal with limited observation data. Since the compressive sensing theory is applied to discrete signals, the problem to be solved first is how to perform compressive sampling on continuous analog signals to realize matrix multiplication of an observation matrix and original signals, which needs to be designed in combination with actual hardware, and the existing schemes based on Analog Information Converters (AIC), such as modulation broadband converters (MWC), random modulation pre-integration (RMPI) need to acquire signals through multiple channels simultaneously and multiple paths of ADs, which not only consumes large resources and is high in cost, but also makes clock synchronization between multiple paths of ADCs extremely difficult, and realizes that relatively simple Random Demodulation (RD) can only be used for acquiring Multitone (multi-tone) signals containing a limited number of discrete frequency components.
Non-uniform sampling, also known as pseudo-random sampling, is the focus of signal sampling technology development in recent years. The basic principle is to randomly delay or advance the sampling time based on uniform sampling. The non-uniform sampling can reduce quantization bit errors and increase dynamic range, and has the characteristic of resisting spectrum aliasing. And by combining with a compressive sensing theory, the non-uniform sampling can break through the limitation of a sampling theorem under the condition of uniform sampling, and a low-speed ADC is used for acquiring the information of the ultra-wideband sparse signal. Compared with other existing AIC schemes, the method has the advantages that non-uniform sampling is more convenient to realize, hardware cost is lower, and meanwhile, the type of sparse signals is not limited. The method for generating the pseudo-random sequence and controlling the ADC to perform the pseudo-random sampling on the signal is a difficult point for realizing the scheme, and foreign teams apply the principle of non-uniform sampling to design and realize an AIC.
Disclosure of Invention
The invention aims to provide a non-uniform ultra-wideband sparse signal sampling method based on an FPGA (field programmable gate array), which is simple to implement and easy to engineer and apply, aiming at the defects of the conventional compressed sampling implementation scheme.
The invention relates to a non-uniform ultra-wideband sparse signal sampling method based on an FPGA (field programmable gate array), which is characterized by comprising the following steps of:
1) the method comprises the steps that a hardware platform for signal sampling is built, the platform mainly comprises an FPGA, an ADC, a DSP and a high-speed sampling holder, wherein the sampling holder is used for holding analog signals, the low-speed ADC is used for digitizing the analog signals output by the sampling holder, the FPGA is used for receiving the digital signals output by the ADC and generating pseudo-random clock signals for controlling the working state of the sampling holder, and the DSP is used for configuring working parameters of related devices;
2) acquiring a signal frequency range according to actual needs to obtain a Nyquist sampling frequency Fs which is 2 times greater than the maximum frequency of the signal;
3) assuming that the nyquist rate needs to be compressed by K times, and the sampling rate of the low-speed analog-to-digital converter AD is F, F is Fs/K, where K is a positive integer.
4) Generating a pseudo-random sequence for controlling a high-speed sampling holder to accept or reject an input discrete signal, and if the total number of code elements is N, N is nK, and N is a positive integer, generating K bit code elements each time by using a pseudo-random code element generation formula, and generating N times in a circulating manner;
5) sequentially connecting the N groups of K bit code elements end to obtain a finally required N bit pseudo-random sequence P;
6) storing the pseudo-random sequence P into RAM in FPGA, and setting the user clock frequency of the FPGA gigabit transceiver to be FuserIf the data width of the RAM is width and the depth is depth, then:
7) and sending out the pseudo-random sequence P at the Nyquist rate Fs by using a gigabit transceiver GTH of the FPGA to control the high-speed sampling holder to hold and pass the signal, and digitizing the analog signal output by the sampling holder by using a low-speed ADC at the rear end to obtain a discrete signal, wherein the signal contains complete information of the original sparse signal.
8) And recovering a sparse representation vector of the original signal in a sparse domain by a signal recovery algorithm in compressed sensing.
The invention is based on the compressive sensing theory, can use FPGA as the core through the existing device, and completes the compressive sampling of the ultra-wideband sparse signal by using the non-uniform sampling technology, the actual sampling rate is far lower than the Nyquist sampling rate, and the invention is an innovation combining the non-uniform sampling and the compressive sensing theory.
Compared with the prior art, the invention has the following advantages:
1) compared with the existing scheme based on an AIC compression sampling model, such as a modulation broadband converter (MWC) and random modulation pre-integration (RMPI), the scheme of non-uniform sampling needs fewer devices and is lower in cost.
2) Compared with the traditional uniform sampling based on the Nyquist theorem, the ultra-wideband sparse signal acquisition method based on the Nyquist sampling has the advantages that the observation matrix form corresponding to the non-uniform sampling accords with the requirement of the compressed sensing theory on the observation matrix, and the observation matrix meets the requirement of uniformly distributed random matrixes, so that the ultra-wideband sparse signal acquisition method based on the Nyquist sampling rate can acquire ultra-wideband sparse signals at a sampling rate far lower than the Nyquist rate, the acquired signals contain all information of original sparse signals, and the burden of signal transmission and storage in the signal processing process is reduced.
Drawings
FIG. 1 is a flow chart of an implementation of the present invention;
FIG. 2 is a functional block diagram of the present invention;
FIG. 3 is a block diagram of the hardware architecture of the present invention;
FIG. 4 is a graph of the non-uniform sampling function and ADC sampling function of the present invention;
FIG. 5a is a waveform of an analog signal input to the sample-and-hold device, FIG. 5b is a waveform of a pseudo-random clock input to the sample-and-hold device, and FIG. 5c is a waveform of a sample-and-hold device output signal;
FIG. 6 is a spectrum diagram of a pseudorandom sequence used in the present invention;
fig. 7a is the original input signal spectrum and fig. 7b is the spectrum after the compressed sample signal has been reconstructed by the OMP algorithm;
FIGS. 8a-8c are graphs of experimental recovered signal spectra of the present invention;
FIG. 9 is a pictorial diagram of the main hardware platform of the present invention;
fig. 10 is a pictorial view of a sample holder used in the present invention.
Detailed Description
The technical solution and effects of the present invention will be described in detail below with reference to the accompanying drawings
Example 1
The invention discloses a non-uniform ultra-wideband sparse signal sampling method based on an FPGA (field programmable gate array), which is shown in figure 1 and comprises the following steps:
1) designing and building a hardware platform for signal sampling, wherein the platform mainly comprises an FPGA, an ADC, a DSP and a high-speed sampling holder, the sampling holder is used for holding an analog signal, and the maximum sampling frequency of the sampling holder can meet the Nyquist sampling rate of a signal to be acquired; the low-speed ADC is used for digitizing the signal held by the sampling holder, and the method provided by the invention adopts the ADC with uniform sampling rate, wherein the specific sampling rate, the compression ratio and the Nyquist sampling rate of the signal are related; the FPGA is used for receiving digital signals output by the ADC and generating pseudo-random clock signals for controlling the working state of the sampling holder, the selected FPGA chip needs to be provided with a gigabit transceiver, and the maximum linear speed of the FPGA chip can reach the Nyquist sampling rate of the signals; the DSP is used for configuring the working parameters of the relevant devices.
2) The invention is mainly applied to the field of electronic reconnaissance, in the electronic reconnaissance, the bandwidth of a radar signal is generally sparse relative to the bandwidth of the whole reconnaissance frequency band, and a Nyquist sampling frequency Fs which is 2 times greater than the maximum frequency of a signal to be reconnaissance is obtained according to the required reconnaissance frequency band range, namely the actual signal frequency band range required to be acquired. The frequency range of the detected signals is 0-FcIf the Nyquist sampling rate Fs is more than or equal to 2Fc。
3) The signal can be sampled at a rate far lower than the Nyquist rate by applying a compressed sensing theory, the Nyquist rate needs to be compressed by K times, the AD sampling rate of the low-speed analog-to-digital converter is F, the sampling rate of the low-speed analog-to-digital converter needs to meet F & ltFs/K & gt, wherein K is a positive integer, AD used by the existing non-uniform sampling method is usually non-uniform, thus a circuit for controlling the low-speed analog-to-digital converter needs to be specially designed during implementation, and the implementation complexity is increased.
4) Generating a pseudo-random sequence for controlling a high-speed sampling holder to accept or reject an input discrete signal, and if the total number of code elements is N, N is nK, and N is a positive integer, generating K bit code elements each time by using a pseudo-random code element generation formula, and generating N times in a circulating manner. Because the method of the present invention employs fixed rate AD, only one bit of the K-bit symbols generated at a time actually realizes sampling of discrete Nyquist rate signals.
5) Operating the code element generating formula in the step 4) N times, and connecting the obtained N groups of K bit code elements end to end according to the generating sequence to obtain the finally needed N bit pseudo-random sequence P. The pseudo-random sequence actually corresponds to a random observation matrix in the compressed sensing theory.
6) Storing the pseudo-random sequence P into RAM in FPGA, and setting the user clock frequency of the FPGA gigabit transceiver to be FuserIf the data width of the RAM is width and the depth is depth, then:
the relative parameters of the above gigabit transceiver are set in an IP core provided by an FPGA development tool, a binary pseudorandom sequence is stored in RAM in the FPGA according to groups, the sending code element rate of the gigabit transceiver is equal to Fs, and an internal logic circuit works in FuserNext, writing the group of width pseudorandom sequences into the gigabit transceiver module at the rising edge of each clock cycle from the RAM, modifying the bit width of each group of pseudorandom codes, and obtaining corresponding FuserAnd the depth of the RAM are changed, and on the premise of meeting the relation of the formula, F is ensureduserThe maximum operating frequency of the chip cannot be exceeded.
7) And sending out the pseudo-random sequence P at the Nyquist rate Fs by using a gigabit transceiver GTH of the FPGA to control the high-speed sampling holder to hold and pass the signal, and digitizing an output analog signal of the holder by using a low-speed ADC at the rear end to obtain a discrete signal, wherein the discrete signal contains complete information of the original sparse signal.
8) And recovering a sparse representation vector of the original signal in a sparse domain by a signal recovery algorithm in compressed sensing.
In electronic investigation, a conventional digital channelized receiver based on uniform sampling generally performs analog filtering and frequency mixing on a radio frequency signal received by an antenna to output an intermediate frequency signal, then digitizes the input intermediate frequency signal through a high-speed ADC, and finally performs subchannel division and digital down-conversion on the digitized intermediate frequency signal. However, when the instantaneous reconnaissance range is expanded to the ultra-wideband, the higher sampling rate ADC is needed to satisfy the nyquist sampling law, which greatly increases the research and development cost, and secondly, even if there is a high-speed ADC that satisfies the requirements, the high-speed ADC often faces the problems of low bit width and high price, and is difficult to be practical. The invention is based on the compressive sensing theory, adopts the non-uniform sampling technology to collect the ultra-wideband sparse signals, and is easier to realize and lower in cost compared with the traditional digital channelized receiver. Meanwhile, the method provided by the invention is used for completing the compressed observation of the observation matrix in the compressed sensing theory on the original signal, and is more convenient for practical realization and engineering application compared with the traditional compressed sampling scheme.
Example 2
The non-uniform ultra-wideband sparse signal sampling method based on the FPGA is the same as the pseudo-random code element generation formula in the embodiment 1 and the step 4, and the specific steps are as follows
Wherein P isiDenotes the symbol sequence generated at the i-th time, where K denotes a symbol number K ═ 1,2,3.. K; u. ofiIs a random number that takes on a range of values from 1 to (K-2) and is updated each time before a symbol is generated.
According to the method provided by the invention, n groups of finally generated code elements form a pseudo-random clock sequence for controlling the sampling holder, the sequence corresponds to a random observation matrix in a compressed sensing theory and is multiplied by an original discrete signal at a Nyquist rate, the compressed observation of the ultra-wideband sparse signal is realized, and the original signal can be recovered by applying a compressed sensing signal reconstruction algorithm to an observation result.
Example 3
The non-uniform ultra-wideband sparse signal sampling method based on the FPGA is the same as that of the embodiment 1-2, the embodiment is an implementation scheme of the hardware platform for ultra-wideband sparse signal sampling in the step 1, and referring to fig. 3, the hardware platform in the embodiment takes the FPGA as a core, is connected with a crystal oscillator, provides a reference input clock for the hardware platform, is connected with a clock chip, provides a working reference clock for a gigabit transceiver in the hardware platform, is connected with a Digital Signal Processor (DSP), configures parameters for the ADC and the clock chip, and is connected with the ADC for receiving a digitized compressed sampling signal; the gigabit transceiver of the FPGA is used for sending out a pre-stored pseudo-random sequence of an internal RAM at a nyquist rate to control the sample holder to hold and pass an input analog signal, and the clock chip simultaneously provides a working reference clock for the ADC; and the ADC digitizes the analog signal output by the sampling holder and transmits the digitized analog signal to the FPGA.
In this example, the FPGA chip as the core uses the high-end V-series chip of Xilink company, in practice, the method is applied to complete sampling of the ultra-wideband sparse signal, and different series of chips of different companies can be used according to actual requirements, as long as the adopted FPGA chip is integrated with the gigabit transceiver and the maximum line rate supported by the gigabit transceiver is greater than or equal to the nyquist sampling rate required to be achieved. The choice of the sample holder is critical, and the performance of the sample holder directly affects the final sampling effect, so in this example, the HMC760 fully differential sample-and-hold chip of ADI corporation is selected, which can provide a larger bandwidth and good dynamic characteristics for the signal acquisition system. The chip can provide accurate signal sampling in a bandwidth exceeding 5GHz, and the output in the 5GHz range keeps 9-10 bits of linear characteristic, only 0.9mV of noise is introduced, and random aperture jitter is lower than 70 fs. In addition, the use of the TI TMS320c6678 eight-core DSP in this example allows for the possibility of analyzing the sampling result, otherwise it actually only functions as a configuration parameter, and if only the sampling of the signal is considered, the DSP can be replaced by a simpler device, such as a single chip, which can minimize the overhead.
The invention combines software and hardware design, is mutually associated and supported in a fusion way, and can quickly build a hardware platform of the analog information converter AIC in the compressed sensing.
Example 4
The non-uniform ultra-wideband sparse signal sampling method based on FPGA is the same as embodiments 1-3, in this example
Step 1: and building a hardware platform for compression sampling.
Step 2: a nyquist sampling rate Fs is determined.
Assuming that a sparse signal of 0-2GHz needs to be acquired, the nyquist sampling rate Fs is 2x2GHz 4 GHz.
And step 3: and selecting the ADC with the corresponding rate according to the compression sampling proportion required to be achieved.
For example, assuming Fs is 3GHz and the compressed sampling ratio K is 5, the sampling rate of the ADC:
for another example, assuming that Fs is 8GHz and the compressed sampling ratio K is 20, the sampling rate of the ADC:
and 4, step 4: a pseudo-random clock sequence for driving the sample-and-hold device is generated.
Assuming that K is 20, the formula for actually generating the pseudo-random binary sequence is as follows:
the symbol generation formula can generate a K-bit random code for each execution, and the execution is performed n times in total.
Wherein P isiThe symbol sequence generated at the ith time is represented, n represents the number of times of cycle generation, and K represents a symbol number K which is 1,2,3.. K; u. ofiIs a random number with a value ranging from 1 to (20-2), and is updated before each symbol generation, which indicates that the actual sampling time interval ranges from 3Tnyq～37Tnyq。
For another example, if K is 5, the pseudo random symbol formula is as follows:
the symbol generation formula can generate a K-bit random code for each execution, and the execution is performed n times in total.
Wherein P isiThe symbol sequence generated at the ith time is represented, n represents the number of times of cycle generation, and K represents a symbol number K which is 1,2,3.. K; u. ofiIs a random number with a value ranging from 1 to (5-2), and is updated before each symbol generation, which indicates that the actual sampling time interval ranges from 3Tnyq～7Tnyq。
And 5: connecting the N groups of K bit code elements obtained in the step 4 end to obtain a final N bit pseudo-random clock sequence
The stronger the randomness of the pseudo-random sequence, the better the signal acquisition effect, which can be generally judged by its spectrum characteristics, and the better pseudo-random sequence should have the spectrum characteristics of approximate white gaussian noise, i.e. it is distributed smoothly in the range of nyquist sampling frequency.
Repeatedly executing the step 4 to obtain a plurality of groups of pseudorandom sequences with the length of N, performing Fourier transform on the generated pseudorandom sequences in Matlab to obtain frequency spectrums of the pseudorandom sequences, and selecting the pseudorandom sequences with the best effect as the finally used pseudorandom sequences, wherein the longer the length of the pseudorandom sequences is, the higher the frequency resolution of the signals is, but when the signals are finally recovered, the higher the time complexity of calculation is, and the relationship among the sequences is represented by the following formula:
wherein f isrIndicating the frequency resolution of the sampled signal, for example, when Fs is 4GHz, if the frequency resolution is to reach 1MHz, the length N of the pseudorandom sequence is:
for another example, when Fs is 8GHz and the required frequency resolution is 0.5MHz, the length N of the pseudo-random sequence is:
step 6: and storing the pseudo-random sequence P into a RAM in the FPGA.
Suppose that the internal user clock frequency of the gigabit transceiver is FuserThe line rate is equal to Fs, so the data bit width and depth of the RAM:
dividing each width bit of a pseudorandom sequence P into a binary number by utilizing Matlab, dividing depth group binary numbers in total, exporting the binary numbers from Matlab in a COE file format, using an FPGA development tool, loading the COE file into an RAM through a configuration interface of the development tool before circuit codes are synthesized, then realizing design, and generating a corresponding binary bit stream file capable of programming the FPGA.
And 7: programming the FPGA, sending out a pseudorandom sequence stored in the RAM by using a gigabit transceiver of the FPGA at a line rate Fs for controlling a sampling holder to hold and pass signals, and finally obtaining discrete compressed observation signals through a rear-end ADC.
The high-speed pseudo-random sequence is used as the working clock of the sampling holder, the sampling holder can complete random access of signals, and the symbol rate is Fs, so that the process is equivalent to sampling the input signal at the Nyquist rate firstly, and then non-uniformly sampling discrete signals at the Nyquist rate on the basis of the sampling.
If the input original signal is a sparse signal, the signal obtained by the compressive sampling of the invention contains all the information of the original sparse signal.
And 8: the original signal is recovered by an orthogonal matching pursuit OMP algorithm.
Compared with the traditional uniform sampling based on the Nyquist theorem, the ultra-wideband sparse signal acquisition method can acquire the ultra-wideband sparse signal at the sampling rate far lower than the Nyquist rate, and the acquired signal contains all information of the original sparse signal, so that the burden of signal transmission and storage in the signal processing process is reduced.
A more detailed example is given below to further illustrate the technical solution of the present invention
Example 5
The non-uniform ultra-wideband sparse signal sampling method based on the FPGA is the same as the embodiment 1-3, and referring to FIG. 1, the implementation steps of the invention are as follows:
step 1: and building a hardware platform for compression sampling.
As shown in fig. 2, the entire sampling platform is primarily comprised of a non-uniform clock generation module, a data sampling module, and a sample and hold module.
As shown in fig. 3, in the actual hardware implementation of the present invention, the function of the clock generation module is completed by the gigabit transceiver of the FPGA and the clock chip, the sample-and-hold module is composed of a sample-and-hold device with high input bandwidth, and the data sampling module is composed of a piece of low-speed ADC chip.
Step 2: a nyquist sampling rate Fs is determined.
The invention has the advantages that the maximum achievable sampling rate is 4GHz, the higher the compression ratio K is, the lower the required sampling rate of an ADC is, but the poorer the signal recovery effect is, and through tests, when the better signal recovery effect is achieved, namely the suppression on stray signals is more than or equal to 15dB, the maximum achievable compression ratio is K which is 10, namely, the 10-time compression on the Nyquist rate is achieved. In this example, Fs is 4GHz and K is 10.
And step 3: and selecting the ADC with the corresponding rate according to the compression sampling proportion required to be achieved.
Obtaining the sampling rate of the ADC by setting Fs to 4GHz and setting the compression sampling proportion K to 10:
in the hardware implementation of the present invention, the ADC chip EV10AQ190 is a 4-channel ADC, and the reference clock frequency inputted from the external is changed to make the ADC operate at different sampling rates and satisfy different compression ratios.
And 4, step 4: a pseudo-random clock sequence for driving the sample-and-hold device is generated.
Referring to FIG. 4, FIG. 4 is a graph of the non-uniform sampling function and ADC sampling function of the present invention, wherein the function p is aboveNU(t) is the non-uniform sampling function, the following function pADC(t) is the ADC sampling function,
K＝10，{unis a group of random variables with the value range of 0-9, TnyqIs the potential Nyquist sampling interval, Tnyq＝1/Fs。pNU(t) and pADCThe relationship of (t) can be expressed as follows:
pNU(t)＝pADC(t-un)
in order to accurately control the relation between the sampling time of the non-uniform clock and the ADC sampling time, the non-uniform clock is generated by performing level conversion on the pseudorandom binary code. Fig. 5a is a waveform diagram of an analog signal input to the sample-and-hold device, fig. 5b is a waveform diagram of a pseudo-random clock input to the sample-and-hold device, fig. 5c is a waveform diagram of an output signal of the sample-and-hold device, and fig. 5a, 5b, and 5c correspond to the same time coordinate axis. As can be seen from the three figures, the sample-and-hold device of the present invention samples a signal at the falling edge of the clock and outputs a signal whose amplitude is the sampled value in the interval of the low level of the clock. For falling edges, with a "10" sequence implementation, the low level is then obtained by letting the symbols be '0', thus converting the design of a non-uniform clock into a design for a pseudo-random binary sequence.
Let the code element width T of the pseudo-random binary codeb＝TnyqN is the length of the pseudorandom sequence, since the sampling clock f of the ADCADCIs fixed and constant, so that the sum ADC sampling clock f can be usedADCThe clocks of the same frequency and source drive the pseudo-random binary code element generator, so that the starting time of the 10N +1 th code element is the same as the sampling time of the ADC clock. Randomly controlling the position of the '10' sequence in the interval 10N +1 to 10(N +1) +1 can make the sampling function p of the non-uniform clockNU(t) satisfies the formula. Considering that the gigabit transceiver has equalization compensation during positive and negative level conversion and the ADC sampling has delay, the formula for actually generating the pseudo-random binary sequence is as follows:
the symbol generation formula can generate a K-bit random code for each execution, and the execution is performed n times in total.
Wherein P isiThe symbol sequence generated at the ith time is represented, n represents the number of times of cycle generation, and K represents a symbol number K which is 1,2,3.. K; u. ofiIs a random number with a value ranging from 1 to (10-2), and is updated before each symbol generation, which indicates that the actual sampling time interval ranges from 3Tnyq～17Tnyq。
And 5: connecting the N groups of K bit code elements obtained in the step 4 end to obtain a final N bit pseudo-random clock sequence
The stronger the randomness of the pseudo-random sequence, the better the signal acquisition effect, which can be generally judged by its spectrum characteristics, and the better pseudo-random sequence should have the spectrum characteristics of approximate white gaussian noise, i.e. it is distributed smoothly in the range of nyquist sampling frequency.
Repeatedly executing the step 4 to obtain a plurality of groups of pseudorandom sequences with the length of N, performing Fourier transform on the generated pseudorandom sequences in Matlab to obtain frequency spectrums of the pseudorandom sequences, and selecting the pseudorandom sequences with the best effect as the finally used pseudorandom sequences, wherein the longer the length of the pseudorandom sequences is, the higher the frequency resolution of the signals is, but when the signals are finally recovered, the higher the time complexity of calculation is, and the relationship among the sequences is represented by the following formula:
wherein f isrIn this example, if Fs is 4GHz and the frequency resolution is 0.5MHz, the length N of the pseudo-random sequence is:
it is therefore necessary to perform the symbol generation formula in step 4
Step 6: and storing the pseudo-random sequence P into a RAM in the FPGA.
Setting internal user clock frequency of gigabit transceiver to Fuser200MHz, its line rate is equal to Fs, so the data bit width and depth of the RAM:
dividing each width bit of a pseudorandom sequence P into a group of single binary numbers by utilizing Matlab, dividing depth group binary numbers in total, exporting the binary numbers from Matlab in a COE file format, using an FPGA development tool, loading the COE file into an RAM through a configuration interface of the development tool before circuit codes are synthesized, then realizing design, and generating a corresponding binary bit stream file capable of programming the FPGA.
And 7: programming the FPGA, sending out a pseudorandom sequence stored in the RAM by using a gigabit transceiver of the FPGA at a line rate Fs for controlling a sampling holder to hold and pass signals, and finally obtaining discrete compressed observation signals through a rear-end ADC.
The high-speed pseudo-random sequence is used as the working clock of the sampling holder, the sampling holder can complete random access of signals, and the symbol rate is Fs, so that the process is equivalent to sampling the input signal at the Nyquist rate firstly, and then non-uniformly sampling discrete signals at the Nyquist rate on the basis of the sampling.
In a hardware implementation of the invention, the pseudo-random clock rate reaches 4GHz, and the back-end digitizes the sample holder signal using a 400MHz fixed rate ADC, achieving 10 times the nyquist sampling rate.
If the input original signal is a sparse signal, the signal obtained by the compressive sampling of the invention contains all the information of the original sparse signal.
And 8: the original signal is recovered by an orthogonal matching pursuit OMP algorithm.
Let EN×NThe method is an N-order identity matrix, the signal sparsity is L, and the compression sampling process is described as follows by a formula:
Y＝ΦX
wherein
The result of the compressed observation is represented,
phi denotes a pseudo-random observation matrix, denoted by EN×NWherein M row vectors are randomly extracted to form the vector,
M＝N/K；
x denotes a discrete original input signal,
the sampling rate is Fs.
The recovery algorithm flow is as follows:
(1) respectively for residual errorsεThe index set S and the number of iterations t are initialized as follows:
R＝y，
t＝1。
(2) finding residual errorsεAnd the maximum value phi in the column vector inner product of the observation matrix phijCorresponding subscript StThen solving the optimization problem
(3) And updating the index set.
(4) An estimate of x can be obtained from the least squares method
(5) UpdatingResidual error
(6) And (3) enabling t to be added by 1, judging whether t is larger than L or not, if t is larger than L, finishing iteration, and otherwise, returning to the step (2) to continue execution.
The invention completes the compression sampling of the ultra-wideband sparse signal, reconstructs the main component of the signal in the sparse domain through a recovery algorithm, and shows that the information contained in the signal is not damaged in the sampling process.
The technical effects of the present invention can be further illustrated by the following simulations and experiments:
example 6
The non-uniform ultra-wideband sparse signal sampling method based on the FPGA is the same as the embodiment 1-5,
1 simulation Condition
The nyquist sampling rate is set to Fs 4GHz, the pseudorandom sequence length is 8000N, and the compression ratio K is 10.
2. Emulated content
Simulation one: and (4) carrying out Fourier transform on the pseudo-random sequence generated by using the pseudo-random code element formula in the step (4) to obtain a spectrogram, as shown in figure 6.
As can be seen from fig. 6, the frequency spectrum of the pseudo-random sequence generated by the present invention is uniformly distributed in the whole frequency domain, and in the whole normalized frequency domain, the envelopes of the frequency spectrum components are smooth and consistent, there is no large fluctuation, and there is no frequency spectrum component with amplitude exceeding 50dB, which indicates that it has better randomness, and is used as the clock of the sample-and-hold device, and has better sampling effect.
Example 7
The non-uniform ultra-wideband sparse signal sampling method based on FPGA is the same as that of the embodiments 1-5, the simulation condition is the same as that of the embodiment 6,
simulation II: setting the input signal to x (t) 100sin (2 π f)1t)+100sin(2πf2t) wherein f1＝500MHz， f2This signal is sampled with the generated pseudo-random sequence at 1300MHz, with 800 sample points. Since we achieve ten times compression of the nyquist rate, the number of points of the reconstructed signal is 8000, while adding white gaussian noise, setting SNR to 0dB, and recovering sparsity L to 4, fig. 7a is the original input signal spectrum, and fig. 7b is the spectrum after the compressed sampled signal is reconstructed by the OMP algorithm.
As can be seen from fig. 7a and 7b, the spectrum of the signal recovered by the present invention is consistent with the spectrum of the original signal x (t), and since the sparsity of the signal is known, the noise component in the spectrum of the original signal is removed when the OMP algorithm is applied.
Example 8
The non-uniform ultra-wideband sparse signal sampling method based on the FPGA is the same as the embodiment 1-5,
conditions of the experiment
Main hardware chip type selection:
FPGA chip Virtex7-690T-1 from Xilink corporation
An ADC chip: EV10AQ190A from E2V
A clock chip: ADF4350 from ADI
Sample holder chip: HMC760LC4B of ADI
A DSP chip: TMS320C6678 Co., Ltd
A signal source: SMA100A, Rohde & Schwarz, Inc
The line rate of the FPGA gigabit transceiver is set to be 4GHz, and the length N of the pseudorandom sequence is 8000; the clock chip outputs the frequency of 800M and is used as a reference clock to be provided for the ADC and the gigabit transceiver, after the equipment is powered on, a configuration program prepared in advance in the DSP runs, the ADC is initialized, and the sampling rate of the ADC is set to be 400 MHz.
Fig. 9 and 10 are hardware platform diagrams of the present invention, the PCB circuit board in fig. 9 mainly includes an ADC, an FPGA, a DSP, and a clock chip, and fig. 10 is a sample holder object diagram for experiment.
Contents and results of the experiments
(a) The input frequency of a signal source is set to be 1.35GHz sinusoidal signals, the signal level is set to be 200mv, collected signals are recovered by applying an OMP algorithm, and the sparsity L is set to be 20.
(b) Setting the input frequency of a signal source to be 800MHz sinusoidal signals, setting the signal level to be 200mv, recovering the acquired signals by applying an OMP algorithm, and setting the sparsity L to be 20.
(c) The method comprises the steps of setting a signal source to input a pulse signal with a carrier frequency of 1.4GHz, setting the pulse width to be 5us, setting the pulse repetition period to be 10us, setting the signal level to be 200mv, recovering the acquired signal by applying an OMP algorithm, and setting the sparsity L to be 100.
Under the condition of online programming of the FPGA, the input signals under the test conditions of (a), (b) and (c) are subjected to compression sampling by using the invention, the obtained compression sampling signals are exported to Matlab by using an online logic analysis core Chipscope provided by a development tool ISE, and are recovered by using an OMP algorithm, and the experimental results are shown in FIGS. 8a, 8b and 8 c.
Referring to fig. 8a and 8b, the original sparse signal spectrum is obtained from the signal after compression sampling by the OMP recovery algorithm, and it can be seen that the largest two spectral components are both consistent with the original input signal, and since the actual input signal necessarily contains noise, there are many spurious components in the spectrum, but this does not affect the estimation of the original signal spectrum, and the suppression of the spurious signals by the largest two components is about 20 dB.
Referring to fig. 8c, an input signal of the experiment is a pulse signal, and the pulse signal has a spectrum leakage phenomenon in a frequency domain due to a truncation effect of a time domain. It can be seen that the maximum component of the recovered signal spectrum is consistent with the original signal, and in electronic reconnaissance, only some parameters of the received signal are often interested, for example, in this example, the sparsity of the input signal in the frequency domain is utilized, and the larger component of the signal in the limited part of the frequency domain is recovered, so that the estimation of the signal frequency can be obtained.
The experimental results are integrated, so that the compression sampling of the ultra-wideband sparse signals is completed, the main components of the signals in the sparse domain can be reconstructed through a recovery algorithm, the information contained in the signals is not damaged in the sampling process, the sparse signal sampling in the 2G bandwidth range is completed by using the AD of 400MHz, the limitation of the Nyquist sampling rate is broken, the combination innovation of a non-uniform sampling technology and a compression perception theory is realized, the practical significance is important, and especially in electronic reconnaissance, the sparse representation of the signals in different transform domains is developed by using the sparse representation method, so that the estimation of various parameters of the signals can be obtained.
In short, the invention discloses a non-uniform ultra-wideband sparse signal sampling method based on an FPGA (field programmable gate array), which mainly solves the problem that the hardware of the conventional compression sampling method is difficult to realize and the problem that the traditional uniform sampling method is limited by the Nyquist theorem. The method comprises the following implementation steps: 1) building a hardware platform; 2) determining a sampling rate parameter; 3) setting the sampling rate of AD according to the required compression ratio; 4) determining a pseudo-random symbol formula; 5) generating a pseudo-random sequence; 6) storing the generated pseudo-random sequence into an RAM of the FPGA; 7) and sending out the pseudo-random sequence as a working clock of a sampling holder by a gigabit transceiver in the FPGA to finish the non-uniform sampling of the sparse signal. 8) The signal is reconstructed by a compressed perceptual recovery algorithm. The invention can realize 10 times compression of the maximum 4GHz Nyquist sampling rate, and the rear end can complete compression sampling of sparse signals within the 2GHz bandwidth range through the AD with the sampling rate of 400 MHz.
The method provided by the invention can be realized by mass-produced devices in the market, greatly reduces the complexity and the cost of the realization of the whole compression sampling system, and solves the problem that uniform sampling based on the Nyquist sampling theorem has high sampling rate and is difficult to realize in certain applications.
Claims (3)
1. A non-uniform ultra-wideband sparse signal sampling method based on an FPGA is characterized by comprising the following steps:
1) the method comprises the steps that a hardware platform for sampling ultra-wideband sparse signals is built, the platform mainly comprises an FPGA, an ADC, a DSP and a high-speed sampling holder, wherein the sampling holder is used for holding analog signals, the low-speed ADC is used for digitizing the signals held by the sampling holder, the FPGA is used for receiving digital signals output by the low-speed ADC and generating pseudo-random clock signals for controlling the working state of the sampling holder, and the DSP is used for configuring working parameters of related devices;
2) acquiring a signal frequency range according to actual needs to obtain a Nyquist sampling frequency Fs which is 2 times greater than the maximum frequency of the signal;
3) assuming that the nyquist rate needs to be compressed by K times, and the sampling rate of the low-speed ADC is F, then F is Fs/K, where K is a positive integer;
4) generating a pseudo-random sequence for controlling a high-speed sampling holder to accept or reject an input discrete signal, and if the total number of code elements is N, N is nK, and N is a positive integer, generating K bit code elements each time by using a pseudo-random code element generation formula, and generating N times in a circulating manner;
5) sequentially connecting the N groups of K bit code elements end to obtain a finally required N bit pseudo-random sequence P;
6) storing the pseudo-random sequence P into RAM in FPGA, and setting the user clock frequency of the FPGA gigabit transceiver to be FuserIf the data width of the RAM is width and the depth is depth, then:
7) sending out a pseudo-random sequence P by using a gigabit transceiver GTH of the FPGA at a Nyquist rate Fs to control a high-speed sampling holder to hold and pass signals, and digitizing analog signals output by the holder by using a low-speed ADC at the rear end to obtain discrete signals, wherein the signals contain complete information of original sparse signals;
8) and recovering a sparse representation vector of the original signal in a sparse domain by a signal recovery algorithm in compressed sensing.
2. The non-uniform ultra-wideband sparse signal sampling method based on the FPGA of claim 1, wherein the pseudo-random symbol generation formula in step 4 is as follows:
i＝1,2,3...n-1,n
wherein P isiK represents a symbol sequence generated in the ith cycle, and K represents a symbol sequence number K in the ith cycle as 1,2,3.. K; u. ofiIs a random number that takes on a range of values from 1 to (K-2) and is updated each time before a symbol is generated.
3. The non-uniform ultra-wideband sparse signal sampling method based on the FPGA as claimed in claim 1, wherein the hardware platform for ultra-wideband sparse signal sampling in step 1 is implemented by taking the FPGA as a core, connecting with a crystal oscillator, providing a reference input clock for the hardware platform, connecting with a clock chip, providing a working reference clock for a gigabit transceiver inside the hardware platform, connecting with a digital signal processor DSP as a transfer for configuration parameter transmission, and connecting with a low-speed ADC for receiving a digitized compressed sampling signal; a gigabit transceiver inside the FPGA provides a working clock for the sample holder; the clock chip simultaneously provides a working reference clock for the low-speed ADC; and the low-speed ADC digitizes the analog signal output by the sampling holder and transmits the digitized analog signal to the FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711258042.5A CN108155911B (en) | 2017-12-04 | 2017-12-04 | Non-uniform ultra-wideband sparse signal sampling method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711258042.5A CN108155911B (en) | 2017-12-04 | 2017-12-04 | Non-uniform ultra-wideband sparse signal sampling method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108155911A CN108155911A (en) | 2018-06-12 |
| CN108155911B true CN108155911B (en) | 2021-06-25 |
Family
ID=62466578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711258042.5A Active CN108155911B (en) | 2017-12-04 | 2017-12-04 | Non-uniform ultra-wideband sparse signal sampling method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108155911B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109085545B (en) * | 2018-06-28 | 2023-03-21 | 西安电子科技大学 | Compressed sensing signal real-time reconstruction method based on FISTA (FISTA) |
| CN111490793B (en) * | 2020-04-10 | 2023-03-14 | 哈尔滨工业大学 | Mixing matrix generation method of modulating broadband converter based on step-type random sequence |
| CN112532244A (en) * | 2020-12-14 | 2021-03-19 | 天津光电通信技术有限公司 | High-speed collection system of intermediate frequency based on PXIE |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101247137A (en) * | 2008-03-24 | 2008-08-20 | 西安电子科技大学 | Ultra-broadband analogue signal parallel sampling system based on accidental projection |
| CN103178853A (en) * | 2013-03-21 | 2013-06-26 | 哈尔滨工业大学 | Compressive-sensing-based sparse signal under-sampling method and implementation device |
| CN103257606A (en) * | 2013-04-22 | 2013-08-21 | 北京控制工程研究所 | USB interface high-speed and real-time sampling logic analyzer |
| CN103765780A (en) * | 2011-06-08 | 2014-04-30 | 纽兰斯公司 | Interference resistant compressive sampling |
-
2017
- 2017-12-04 CN CN201711258042.5A patent/CN108155911B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101247137A (en) * | 2008-03-24 | 2008-08-20 | 西安电子科技大学 | Ultra-broadband analogue signal parallel sampling system based on accidental projection |
| CN103765780A (en) * | 2011-06-08 | 2014-04-30 | 纽兰斯公司 | Interference resistant compressive sampling |
| CN103178853A (en) * | 2013-03-21 | 2013-06-26 | 哈尔滨工业大学 | Compressive-sensing-based sparse signal under-sampling method and implementation device |
| CN103257606A (en) * | 2013-04-22 | 2013-08-21 | 北京控制工程研究所 | USB interface high-speed and real-time sampling logic analyzer |
Non-Patent Citations (2)
| Title |
|---|
| 一种FPGA可实现的压缩传感采样方法;刘继忠等;《仪表技术与传感器》;20131031(第10期);全文 * |
| 频域稀疏信号可压缩采样方法;盖建新等;《哈尔滨理工大学学报》;20131231;第18卷(第6期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108155911A (en) | 2018-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101610095B (en) | FPGA-based ultra-wideband radio frequency digital receiver device and realization method thereof | |
| CN108155911B (en) | Non-uniform ultra-wideband sparse signal sampling method based on FPGA | |
| Yoo et al. | Design and implementation of a fully integrated compressed-sensing signal acquisition system | |
| Bellasi et al. | VLSI design of a monolithic compressive-sensing wideband analog-to-information converter | |
| Kirolos et al. | Expression of Concern: Practical Issues in Implementing Analog-to-Information Converters | |
| Chen et al. | A sub-Nyquist rate compressive sensing data acquisition front-end | |
| US8750438B2 (en) | Interference resistant compressive sampling | |
| D'Arco et al. | Design and implementation of a preprocessing circuit for bandpass signals acquisition | |
| CN201499161U (en) | Superwide band radio frequency digital receiver device based on FPGA | |
| Mishali et al. | Generic sensing hardware and real-time reconstruction for structured analog signals | |
| CN108181616B (en) | Method for generating radar digital interference based on System Generator | |
| CN116663670A (en) | Quantum measurement and control system, quantum computer, system, network and communication method | |
| Pelissier et al. | Hardware platform of Analog-to-Information converter using Non Uniform Wavelet Bandpass Sampling for RF signal activity detection | |
| Zhao et al. | Sparse multiband signal spectrum sensing with asynchronous coprime sampling | |
| Meng et al. | A method based on random demodulator and Waveform matching dictionary to estimate LFM signal parameter | |
| Song et al. | Towards a real-time UWB MIMO testbed for sensing and communications | |
| CN202634414U (en) | X-band broadband high-resolution digital channelization receiving machine | |
| CN105068061A (en) | Analog information conversion method based on chirp frequency mixing and system thereof | |
| Chen et al. | A frequency estimation method based on MWC discrete compressed sampling structure | |
| Si et al. | Adaptive reconstruction algorithm based on compressed sensing broadband receiver | |
| Meleshin et al. | Application Of An Analog-to-Information Converter In Multichannel Radio Systems | |
| Wang et al. | Low cost high frequency signal synthesis: Application to RF channel interference testing | |
| CN113126033B (en) | Radar signal digital quadrature down-conversion method | |
| Wang et al. | Antenna far-field measurement exploiting compressed sensing | |
| Marnat | Radiofrequency receiver based on compressive sampling for feature extraction in cognitive radio applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220507 Address after: 710000 room 312-314, third floor, building 1, No. 26, Gaoxin Sixth Road, high tech Zone, Xi'an, Shaanxi Province Patentee after: Shaanxi Weimai Instrument Equipment Co.,Ltd. Address before: 710071 Taibai South Road, Yanta District, Xi'an, Shaanxi Province, No. 2 Patentee before: XIDIAN University |
|
| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 710000 room 312-314, third floor, building 1, No. 26, Gaoxin Sixth Road, high tech Zone, Xi'an, Shaanxi Province Patentee after: Shaanxi VImeasurement Equipment Co.,Ltd. Address before: 710000 room 312-314, third floor, building 1, No. 26, Gaoxin Sixth Road, high tech Zone, Xi'an, Shaanxi Province Patentee before: Shaanxi Weimai Instrument Equipment Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |