CN108181616B

CN108181616B - Method for generating radar digital interference based on System Generator

Info

Publication number: CN108181616B
Application number: CN201711382421.5A
Authority: CN
Inventors: 董春曦; 麻鹏飞; 畅鑫; 饶鲜; 郑鑫
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2017-12-20
Filing date: 2017-12-20
Publication date: 2021-11-30
Anticipated expiration: 2037-12-20
Also published as: CN108181616A

Abstract

The invention belongs to the field of radar digital interference, and discloses a method for generating radar digital interference based on a System Generator, which comprises the following steps: building a basic operation module of radar digital interference; acquiring a required digital interference pattern to obtain a mathematical model of the digital interference pattern; converting the mathematical model of the digital interference pattern into a hardware circuit consisting of basic operation modules; the hardware circuit is subjected to generalized encapsulation to obtain the required digital interference circuit, so that the radar interference system architecture can be simplified, the design difficulty of the radar interference system is reduced, and the development efficiency of the radar interference system is improved.

Description

Method for generating radar digital interference based on System Generator

Technical Field

The invention belongs to the field of radar digital interference, and particularly relates to a method for generating radar digital interference based on a System Generator, which can be used for rapid simulation and realization of a radar interference System.

Background

In the design, simulation and implementation processes of a radar jamming system, how to quickly generate a jamming signal and modify jamming parameters is an important engineering problem in the design of a jammer. The traditional digital interference system mostly adopts a large-scale integrated circuit to process digital signals so as to adapt to complex environments with wide frequency band, multiple modulation modes and multiple signals where the interference system is located. There have been some research results on System and algorithm simulation and implementation by System Generator.

Simulation of the jamming-like algorithm using Simulink was proposed in the published article, "Simulink modeling and analysis of typical jamming" ("2016 Journal of Air Force Early Warning academic 2014, pp: 343-347) by Liviang et al. The method comprises the following specific steps: analyzing a typical mathematical model for suppressing interference, wherein the interference pattern comprises radio frequency noise interference, noise amplitude modulation interference and noise frequency modulation interference; the second step is that: modeling in Simulink; the third step: and carrying out dynamic simulation of interference effect. The method tries to build a typical suppression type interference pattern by using Simulink, and can reflect the dynamic change process of an interference signal compared with other simulation tools, but still has the defects that the interference pattern is few, only function simulation can be carried out, and the interference pattern cannot be directly converted into a hardware circuit.

Dianthus superbus et al in the thesis "smart interference platform design and implementation based on FPGA/DSP" (2009 Modern Electronics technologies 2009, PP: 33-36) discloses a smart interference platform design and implementation method based on FPGA/DSP. The method comprises the steps of constructing a smart interference hardware platform by using an FPGA and a DSP, sharing an external RAM by the FPGA and the DSP through an EMIF bus, cooperatively realizing high-speed processing of signals, and designing and writing hardware platform control software by using a Verilog language. Although the modularized design method of the method guarantees the functional requirements of platform design and builds a smart interference platform, the method has the defects of single interference mode, poor reusability of interference modules and the like which need to be supplemented.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a method for generating radar digital interference based on a System Generator, which can simplify a radar interference System architecture, reduce the design difficulty of a radar System, and improve the development efficiency of the radar System.

The technical idea for realizing the method is that a basic module is firstly established, a mathematical model of an interference pattern is analyzed, and the mathematical model is converted into a hardware model of a hardware parallel processing mode; then building each interference pattern module and carrying out universal encapsulation; and finally, packaging the data into a deception general interference library and a suppression general interference library.

In order to achieve the purpose, the invention is realized by adopting the following technical scheme.

A method for System Generator-based radar digital interference generation, the method comprising:

step 1, building a basic operation module of radar digital interference;

step 2, acquiring a required digital interference pattern to obtain a mathematical model of the digital interference pattern;

step 3, converting the mathematical model of the digital interference pattern into a hardware circuit consisting of the basic operation module;

and 4, carrying out generalized encapsulation on the hardware circuit to obtain the required digital interference circuit.

The technical scheme of the invention has the characteristics and further improvements that:

(1) in step 1, the basic operation module for radar digital interference at least comprises: the device comprises a counting frequency division module, a signal rising edge extraction module, a smart interference selection module, a positive sawtooth waveform generation module, an FIFO (first in first out) delay module and a Gaussian noise generation module.

(2) The counting frequency division module is used for dividing the frequency of a system clock to generate a clock signal required by the digital interference pattern;

the counting frequency division module comprises an accumulator and a comparator, when the accumulator reaches a preset bandwidth value, the comparator outputs a high level, and the accumulator is reset;

the input pins of the counting frequency division module comprise a bandwidth setting pin and a reset pin, the bandwidth setting pin is used for setting a bandwidth preset value, and the reset pin is effective in high level; the accumulator is controlled by the reset pin, when the reset pin outputs a low level, the accumulator completes the cycle counting from 1 to a preset bandwidth value, when the reset pin outputs a high level, the counting frequency division module outputs a high level, and therefore the frequency division result taking the preset bandwidth value as a multiple is completed.

(3) The rising edge extracting module is used for extracting the rising edge of the radar signal and generating effective enabling of the digital interference pattern;

the rising edge extraction module comprises a data splicing unit, a comparator and a delay unit, a 1-bit radar input signal and the 1-bit radar input signal delayed by one clock period are spliced into a 2-bit radar input signal, when the rising edge of the radar input signal arrives, the data splicing unit outputs 10, namely decimal number 2, the output of the data splicing unit is compared with the decimal number 2 in the comparator, and when the output of the data splicing unit is 2, the rising edge of the radar input signal is detected;

and the input pin of the rising edge extraction module is connected with the data splicing unit and is used for inputting a radar input signal with the bit width of 1 bit.

(4) The smart interference selection module is used for modulating the suppression interference signal to the received radar target signal;

the smart interference selection module comprises two signal selectors respectively used for selecting a real part and an imaginary part of a composite signal and selecting a real part and an imaginary part of an external signal; the synthetic signal is the suppression interference signal, and the external signal is the radar target signal;

the input pins of the smart interference selection module comprise a composite signal real part input pin, a composite signal imaginary part input pin, an external signal real part input pin, an external signal imaginary part input pin and a selection bit pin; when the selected bit is 1, the real part or the imaginary part of the combined signal is output, and when the selected bit is 0, the real part or the imaginary part of the external signal is output.

(5) The positive sawtooth waveform generating module is used for generating positive sawtooth waveforms of which extreme values and stepping intervals are respectively controllable;

the positive sawtooth waveform generation module comprises an accumulator, an adder and a comparator;

the input pins of the positive sawtooth waveform generation module comprise an enable pin, a stepping interval pin, a minimum value pin, a maximum value pin and a reset pin, and the high level of the reset pin is effective;

the stepping interval pin is used for setting a stepping value accumulated by the sawtooth waveform, and the minimum value pin and the maximum value pin are used for setting the amplitude variation range of the sawtooth waveform; when the reset pin is invalid, the accumulator accumulates at a step interval from a minimum value, and when an accumulated value reaches a maximum value, the reset pin is valid to reset the accumulator, thereby cyclically outputting a positive sawtooth waveform.

(6) The FIFO delay module is used for outputting a signal by preset delay;

the FIFO delay module comprises an FIFO memory, a subtractor and a comparator; a dcount pin and a dout pin are arranged on the FIFO memory; the dcount pin represents the number of data stored in the FIFO memory, and the dout pin is used for outputting the data in the FIFO memory;

the input pins of the FIFO delay module comprise a signal input pin, an enable pin, a delay number pin and a reset pin, and the high level of the reset pin is effective; when the enable pin is valid, data are written into the FIFO memory, and when the number of the data written into the FIFO memory reaches the delay time, the comparator outputs high level, so that the FIFO memory outputs the stored data.

(7) The Gaussian noise generation module is used for generating Gaussian noise;

the Gaussian noise generation module comprises a sine data memory, a cosine data memory, a logarithmic data memory, an imaginary multiplier, a real multiplier and two data bit width converters, wherein the two data bit width converters are respectively used for converting an input random number into an addressing address with a bit width of 10 bits, and the sine data memory, the cosine data memory and the logarithmic data memory are respectively used for storing corresponding waveform data.

(8) When the digital interference pattern is radio frequency noise interference, the hardware circuit composed of the basic operation module in step 3 is a radio frequency noise interference circuit, including: the counting frequency division module, the Gaussian noise generation module, the smart interference selection module, and a System Generator own signal Generator, a logic OR gate, a multiplier and a signal delay unit;

the input pin of the radio frequency noise interference circuit comprises: the device comprises a bandwidth setting pin, a frequency control pin, a signal selection pin, an external signal real part pin, an external signal imaginary part pin and a reset pin, wherein the reset pin is effective in high level; the output pin of the radio frequency noise interference circuit comprises: a signal output real part pin, a signal output imaginary part pin and a signal valid bit pin;

the bandwidth setting pin is used for setting the bandwidth of the noise generated by the Gaussian noise generation module; the frequency control pin is used for controlling the frequency of sine and cosine signals output by the signal generator, and the range of signals input by the frequency control pin is 0 to 1; the signal selection pin is used for selecting the signal output by the smart interference selection module to be a synthesized signal or an external signal;

and the signal output by the smart interference selection module and the noise signal output by the Gaussian noise generation module are subjected to complex multiplication to form the radio frequency noise interference.

Compared with the prior art, the invention has the following advantages: the digital interference toolbox can be rapidly deployed to generate interference signals, so that the difficulty in the interference field is isolated, and the difficulty in developing an interference system is greatly reduced by a universal interference module; the digital interference tool box disclosed by the invention covers various basic suppression type and deception type interference patterns, and a designer can conveniently generate various interferences.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic flow chart of a method for generating radar digital interference based on a System Generator according to an embodiment of the present invention;

fig. 2(a) is a schematic circuit diagram of a counting and frequency dividing module according to an embodiment of the present invention, fig. 2(b) is a schematic circuit diagram of a rising edge module of an extracted signal according to an embodiment of the present invention, fig. 2(c) is a schematic circuit diagram of a smart interference selection module according to an embodiment of the present invention, fig. 2(d) is a schematic circuit diagram of a positive sawtooth waveform generation module according to an embodiment of the present invention, fig. 2(e) is a schematic circuit diagram of a FIFO delay module according to an embodiment of the present invention, and fig. 2(f) is a schematic circuit diagram of a gaussian noise generation module according to an embodiment of the present invention;

in fig. 3, fig. 3(a) is a schematic circuit structure diagram of a radio frequency noise interference module according to an embodiment of the present invention, and fig. 3(b) is a schematic circuit structure diagram of a specific noise interference module in fig. 3(a) according to an embodiment of the present invention;

fig. 4(a) is a schematic diagram of a simulation system of a radio frequency noise interference module according to an embodiment of the present invention, and fig. 4(b) is a schematic diagram of a spectrum of a radio frequency noise interference signal output by a spectrometer according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides a method for generating radar digital interference based on a System Generator, as shown in fig. 1, the method comprises the following steps:

step 1, building a basic operation module of radar digital interference.

The mathematical operations involved in the interference pattern are mostly complex multiplication, accumulation, delay, comparison and other operations, and the construction of a basic operation module is required before the interference pattern module is established. And starting with complex multiplication, accumulation and delay involved in the basic module, the mathematical model is converted into a hardware circuit realizable model. Several basic operation methods are briefly introduced.

2a) Counting frequency division module

The counting and frequency dividing module has the main function of further dividing the system clock to generate the clock signal required by the element. The main structure is composed of an accumulator and a comparator, when the accumulator reaches the bandwidth preset value, the comparator outputs high level, and resets the accumulator, and enters the counting cycle process again.

In the specific circuit shown in fig. 2(a), the input pins include "bandwidth setting" and "reset", and the reset high level is active. The accumulator module is controlled by a reset pin, and when the level of the reset pin is invalid, accumulation with '1' as a stepping interval is completed. The reset signal is obtained by performing phase OR on an external reset pin and an output enable signal through a logic OR gate, and is converted into a data type of an accumulator reset terminal rst through a signal type conversion module. Finally, the function of the module is as follows: when the reset pin outputs a reset level (high level), the whole module is reset and outputs a low level; when the reset pin outputs an invalid level (low level), the accumulator completes the cycle counting from 1 to the bandwidth setting value, and each time the bandwidth setting output is counted, the module outputs a high level, namely, the frequency division effect of the bandwidth with the multiple of the preset value is completed.

2b) Signal rising edge extraction module

The module for extracting the rising edge of the signal mainly has the function of extracting the rising edge of the radar signal and generating effective enabling of the module. The device mainly comprises a data splicing module, a comparator and a delay unit, wherein a 1-bit input signal and a 1-bit input signal delayed by one clock period are connected into a signal with 2-bit width, and when a radar rising edge arrives, a signal connector outputs '10', namely decimal 2. The comparison is carried out in the comparator, and when the high level is output, the signal rising edge is detected.

In the specific circuit shown in fig. 2(b), the input pin is an envelope input signal with a bit width of 1 bit. The signal passes through a "delay unit" which delays the signal by one time unit. Splicing is finished at a data splicing module, comparison is carried out with a constant value of 2 in a comparator, and the output high level of 10 is detected, namely the rising edge is detected.

2c) Smart interference selection module

Smart interference is added to the module in view of its universal use. The smart interference modulates the generated suppression interference signal to the received target radar signal, and utilizes the characteristic of matching the suppression interference signal with the radar signal to resist pulse compression, pulse Doppler and other radar systems. The main components are two signal selectors, which respectively select the real part and the imaginary part of the signal.

As shown in fig. 2(c), the input pin includes "real part of synthesized signal", "imaginary part of synthesized signal", "real part of external signal", "imaginary part of external signal", and "selection bit", and the bit width of the input signal is determined by the outside. When the 'selection bit' is 1, selecting the synthesized signal to output; when the "selection bit" is 0, the external signal is selected and output. The synthesized signal is generated internally, and has larger amplitude, so a real part shifter and an imaginary part shifter are needed to regulate and control the signal amplitude. The whole module realizes the selection of signals and the regulation and control of amplitude.

2d) Positive sawtooth waveform generation module

The positive sawtooth waveform generation module is mainly used for generating a positive sawtooth waveform with controllable extreme values and step intervals and controlling and generating a positive sawtooth frequency modulation signal. The main components are accumulator, adder and comparator. The accumulator accumulates continuously, adds the initial value and compares the initial value with the extreme value, when the initial value is greater than or equal to the extreme value, the accumulator is reset, and the output of the accumulator is the positive sawtooth waveform.

In the specific circuit shown in fig. 2(d), the input pins include "enable", "step interval", "minimum", "maximum", and "reset", and the reset high is active. The "step interval" sets the step value of the sawtooth waveform accumulation, and the "minimum" and "maximum" set the range of sawtooth waveform variation. When the reset level is invalid, accumulation is carried out at a stepping interval from the minimum value, and when the accumulated value reaches the maximum value, the accumulator is reset to realize the circular accumulation effect, so that the positive sawtooth waveform is circularly output.

2e) FIFO delay module

The FIFO delay module (first-in first-out delay memory) mainly has the function of carrying out certain delay output on signals and consists of the FIFO memory, a subtractor and a comparator. When the output data counter of the FIFO memory reaches a set delay value, the read enable of the FIFO is pulled up, and the data stored in the FIFO starts to be read.

In the specific circuit shown in fig. 2(e), the input pins include "signal input", "enable", "delay number", and "reset", and the reset high level is active. When the enable is effective, signals are written into the FIFO memory, the 'dcount' is the number of the signals stored in the FIFO memory, when the count value reaches the 'delay number' setting, the comparator outputs high level, the FIFO starts to read out the stored data, and therefore delay storage with controllable delay is achieved.

2f) Gaussian noise generation module

Gaussian noise has an irreplaceable position in suppressing interference, and is required by both radio frequency noise interference and noise modulation interference. The module adopts a Mueller algorithm to transform random numbers obeying uniform distribution on (0, 1) into random numbers obeying Gaussian distribution. Let x, y be 2 mutually independent random numbers uniformly distributed on (0, 1), and make the following transformation:

m＝(-2lnx)^1/2cos(2πy)

n＝(-21nx)^1/2sin(2πy)

where m, N are 2 mutually independent random numbers obeying N (0, 1), generated using a linear shift feedback register. And taking m and n as addressing addresses, respectively storing values of sin, cos and log functions in a RAM, reading and multiplying to obtain Gaussian noise.

In the specific circuit shown in fig. 2(f), the input pins are "random number 1" and "random number 2", i.e., x and y as mentioned above. And converting the data bit width of the two random numbers into an addressing address with the bit width of 10 bits, inputting the addressing address into the RAM, and addressing. The sine data memory, the logarithm data memory and the cosine data memory store corresponding waveform data, the data obtained by addressing are multiplied to obtain imaginary part noise data and real part noise data, and the imaginary part noise data and the real part noise data are output to imaginary part data output pins and real part data output pins.

And 2, acquiring a required digital interference pattern to obtain a mathematical model of the digital interference pattern.

Step 2 is implemented by using a conventional general algorithm, which is not specifically described herein.

And 3, converting the mathematical model of the digital interference pattern into a hardware circuit consisting of the basic operation module.

After each basic module is built, the basic module is used for building the interference module according to the requirement of the interference module.

The rf noise interference module is taken as an example for explanation. Fig. 3(a) is an internal circuit diagram of the rf noise interference module. The input pins comprise 'bandwidth setting', 'frequency control', 'signal selection', 'external signal real part', 'external signal imaginary part' and 'reset', and the reset level is high in effectiveness. The bandwidth setting interface is used for setting the bandwidth of noise generated by the noise generation module, controlling the frequency of sine and cosine signals output by the signal generator by frequency control, and controlling the input range of a base pin of the frequency control to be 0-1. When the 'signal selection' is 1, the 'signal selection module' outputs a synthesized signal; when the "signal selection" is 0, the "signal selection module" outputs an external signal. The signal and the noise output by the noise generation module are subjected to complex multiplication to form noise modulation interference. The output pin "rdy" of the "signal generator" is the valid bit of the signal, which is OR' ed with "signal select", as the enable of the "multiplier", controlling the output of the signal. And delays the enable signal by 6 time units as the signal valid bit for the entire module.

The rf noise block in fig. 3(a) is composed of a "noise generation block", a "signal generator", a "signal selection block", a "logical or gate", a "multiplier", and a "signal delay unit". Fig. 3(b) is a circuit diagram of an internal circuit of the "noise generation module", which includes the basic modules such as the "frequency division module" and the "gaussian noise generation module" described above. The "random number 1" and the "random number 2" may output random numbers subject to uniform distribution. Wherein, in fig. 3(a), "signal selection module" is the basic module described in the above embodiment, and the selection of the external signal and the synthesized signal is performed by "signal selection".

Modern radar signals are generally large-time wide-bandwidth signals, so that the signals can be subjected to multi-channel processing by utilizing Matlab codes. In order to match with the multi-channel output of the analog-to-digital converter, a Matlab code construction module is used for initializing subfunctions, so that an interference circuit generation module becomes a multi-channel convertible mode.

4a) The number of the selectable channels of the interference module is 1-32, and the initialization function needs to be operated firstly when the module is simulated each time. Deleting input pins and output pins of 2-32 channels and connecting lines between the input pins and the output pins by using two functions of delete _ line and delete _ block; and then adding input pins, output pins and required connecting wires among the input pins and the output pins to corresponding channels by using add _ line and add _ block according to the setting of the number of the channels. The unneeded channel input adds a constant of 0 and the output is linked to a dummy pin.

4b) Setting a flag bit to store the channel number, comparing whether the stored channel number is the same as the channel number set at this time or not during each initialization, and if so, not executing any operation; if not, the operation in 4a) is executed. The non-working channel is optimized after synthesis and compiling, and the use resource of the FPGA is saved.

The effect of the present invention will be further explained with the simulation experiment.

Referring to fig. 4(a), a simulation system is created for the rf noise module, an "In" pin is allocated to each input pin, an "Out" pin is allocated to each output pin, an input signal is set at an input end, an output end is connected to a test element, two paths of real signals of the output signal are converted into complex signals, and the complex signals are input into a frequency spectrograph to check the signal spectrum change.

1. Simulation conditions are as follows:

in the simulation experiment, the computer configuration environment is an Intel (R) Core (i5-3470)3.20GHZ central processing unit and an internal memory 16G, WINDOWS 7 operating system, computer simulation software adopts MATLAB R2013a software, and the FPGA model is Spartan 6. The simulation parameters of the invention are as follows: the system frequency is set to 350MHz, the bandwidth is set to "20", the frequency control input "0.1", and the "signal select" is set to 0.

2. Simulation content:

and performing function simulation of the radio frequency noise module based on the simulation parameters, and observing the signal frequency spectrum change in the frequency spectrograph.

3. And (3) simulation result analysis:

the following describes the rf noise jamming module in the jamming kit according to the present invention with reference to the simulation operation result shown in fig. 4 (b). The system frequency is set to 350MHz, and the bandwidth is set to "20", that is, the noise generation module generates radio frequency noise with a bandwidth of 350/20-17.5 MHz. The frequency control input "0.1" internally generates a sine-cosine signal of 350 x 0.1-35 MHz. The "signal select" sets 0, i.e., selects the composite signal for complex multiplication output. Therefore, the signal generated by the whole module should be 35-17.5/2-35 +17.5/2, and the frequency range of the generated RF noise bandwidth is 26.25-43.75 MHz.

As shown in fig. 4(b), the output of the spectrometer is shown, the horizontal axis "Frequency" is the Frequency axis, the unit is MHz, the vertical axis is the amplitude, the unit is dBm, it can be seen from the figure that the signal energy is concentrated between 26.19MHz and 43.72MHz, corresponding to the setting parameters, and the simulation is error-free.

In conclusion, the method can effectively eliminate the technical difficulty of interference, realizes the rapid deployment and realization of the digital interference signal on a single platform, greatly improves the interference design efficiency, and accords with the development trend of modern industrial system design.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for generating radar digital interference based on a System Generator, the method comprising:

step 1, building a basic operation module of radar digital interference;

the basic operation module of the radar digital interference at least comprises: the device comprises a counting frequency division module, a signal rising edge extraction module, a smart interference selection module, a positive sawtooth waveform generation module, an FIFO (first in first out) delay module and a Gaussian noise generation module;

the smart interference selection module is used for modulating the suppression interference signal to the received radar target signal;

the input pins of the smart interference selection module comprise a composite signal real part input pin, a composite signal imaginary part input pin, an external signal real part input pin, an external signal imaginary part input pin and a selection bit pin; when the selected bit is 1, outputting a real part or an imaginary part of the composite signal, and when the selected bit is 0, outputting a real part or an imaginary part of the external signal;

2. The System Generator-based radar digital interference generating method of claim 1, wherein the count frequency dividing module is configured to divide a System clock to generate a clock signal required by the digital interference circuit;

3. The System Generator-based radar digital interference generating method of claim 1, wherein the rising edge extracting module is configured to extract a rising edge of a radar signal to generate an effective enable of the digital interference circuit;

the rising edge extraction module comprises a data splicing unit, a comparator and a time delay unit, and splices the 1-bit radar input signal and the 1-bit radar input signal delayed by a time unit into a 2-bit radar input signal;

when the rising edge of the radar signal arrives, the data splicing unit outputs 10, namely decimal number 2, and then the output of the data splicing unit is compared with decimal number 2 in the comparator, and when the output of the data splicing unit is 2, the rising edge of the radar signal is detected;

4. The System Generator-based radar digital interference generating method of claim 1, wherein the positive sawtooth waveform generating module is used for generating positive sawtooth waveforms with separately controllable extremum and step interval;

5. The System Generator-based radar digital interference generating method of claim 1, wherein the FIFO delay module is configured to output a signal with a preset delay;

6. The System Generator-based radar digital interference generating method of claim 1, wherein the gaussian noise generating module is used for generating gaussian noise;

the Gaussian noise generation module comprises a sine data memory, a cosine data memory, a logarithm data memory, an imaginary multiplier, a real multiplier and two data bit width converters, wherein the two data bit width converters are respectively used for converting input random numbers into addressing addresses, and the sine data memory, the cosine data memory and the logarithm data memory are respectively used for storing corresponding waveform data.

7. The System Generator-based radar digital interference generating method of claim 1, wherein when the digital interference pattern is rf noise interference, the hardware circuit composed of the basic operation module in step 3 is an rf noise interference circuit, comprising: the counting frequency division module, the Gaussian noise generation module, the smart interference selection module, and a System Generator own signal Generator, a logic OR gate, a multiplier and a signal delay unit;

the bandwidth setting pin is used for setting the bandwidth of the noise generated by the Gaussian noise generation module; the frequency control pin is used for controlling the frequency of sine and cosine signals output by the signal generator, the range of the input signals of the frequency control pin is 0 to 1, and sine and cosine signals with the frequency of 0MHz to 350MHz are correspondingly generated; the signal selection pin is used for selecting the signal output by the smart interference selection module to be a synthesized signal or an external signal;