CN108153699A

CN108153699A - A kind of AHB turns AXI protocol switching controller design method

Info

Publication number: CN108153699A
Application number: CN201711400805.5A
Authority: CN
Inventors: 张贞雷
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2017-12-21
Filing date: 2017-12-21
Publication date: 2018-06-12

Abstract

The present invention relates to chip design fields, the method for converting protocol and controller of more particularly to a kind of AHB to AXI, the normal communication being used to implement between the IP with AHB interface and the IP with AXI interfaces, and implementation method is simple, only take up seldom logical resource, extra-pay is not needed to, greatly reduces project cost.

Description

A kind of AHB turns AXI protocol switching controller design method

Technical field

The present invention relates to chip design field, more particularly to a kind of method for converting protocol of AHB to AXI.

Background technology

In one complete SoC systems design, ready-made, the reusable much based on AXI either AHB interfaces can be related to IP, but the IP of distinct interface, it is not possible to be connected directly.If carry out normal communication, it is necessary to use connection-bridge.

But the IP of connection-bridge much all need pay, extra purchase, this can undoubtedly increase project/product into This.Connection-bridge between AHB to AXI, needs extra purchase, and project cost can be significantly greatly increased in this.

Invention content

The present invention devises a kind of AHB and turns AXI protocol switching controller, is used to implement the IP with AHB interface with being connect with AXI Normal communication between the IP of mouth, and implementation method is simple, only takes up seldom logical resource, does not need to extra-pay, Greatly reduce project cost.

The present invention is achieved through the following technical solutions, and a kind of AHB turns AXI protocol switching controller, which uses Normal communication between the IP with the AHB interface and IP with AXI interfaces is realized, including AHB_Slave_Convert modules, AXI_Master_Convert modules, CMD_FIFO, WR_DATA_FIFO, WR_RESP_FIFO, RD_DATA_FIFO.

Further, AHB_Slave_Convert modules receive the AHB instructions that AHB Master IP are sent, and solve Analysis takes out read/write signal Hwrite from AHB instructions, and address signal Haddr, Hburst signal, Hsize signals are as one group CMD_FIFO is written in CMD；Using Hrequest signals as the write enable signal of CMD_FIFO, when the signal is high, and And the value of Htrans is when be equal to 2 or 3, just captures AHB instruction, in write-in CMD_FIFO；And in CMD_FIFO When being full, Hready is dragged down, AHB Master IP is made to stop inputting new AHB instructions.

Further, if it is write order that AHB_Slave_Convert modules, which are resolved to current AHB instructions, after continued access Hwdata is received, is written in WR_DATA_FIFO, and receive AXI Slave IP and write sound by what write response channel was fed back Induction signal is written WR_RESP_FIFO, AHB Master IP is returned to by the Hresp signals of AHB.

Further, if it is read command that AHB_Slave_Convert modules, which are resolved to current AHB instruction, AHB_ Slave_Convert modules receive the reading data signal that AXI Slave IP are fed back by reading data channel, and RD_ is written DATA_FIFO returns to AHB Master IP by the Hrdata signals of AHB.

Further, AXI_Master_Convert modules read instruction from CMD_FIFO, and the instruction of reading is turned It is changed to AXI sequential and is sent to AXI Slave IP, if writing data command, then the Haddr signals in CMD are sent to AXI The write address channel of bus, and the data of writing in WR_DATA_FIFO are read, write data channel is written, while receive AXI The write response signal that Slave IP are returned by write response channel, and the signal is returned into AHB_Slave_Convert modules.

Further, if the instruction that AXI_Master_Convert modules read instruction from CMD_FIFO is to read data Haddr signals in CMD, then is sent to the reading address tunnel of AXI buses, and receive AXI Slave IP and pass through reading by instruction The reading data signal that data channel returns, and the signal is returned into AHB_Slave_Convert modules.

The present invention also provides a kind of AHB to turn AXI protocol conversion method, and this method comprises the following steps：1) AHB is parsed to refer to It enables, including read/write signal, address, burst information writes data；2) AHB parsed is instructed, be stored in respectively corresponding FIFO including instruction FIFO and writes data FIFO；3) if write operation, by read/write signal, address, burst information writes number The corresponding channels of AXI are sent into according to waiting, AXI protocol is converted to, and collect the write response signal that AXI interfaces are fed back, writes into Whether WRITE RESPONSE FIFO instruction current write operations are correctly completed, while feed back to AHB interface；4) if reading behaviour Make, then by the reading returned data of AXI interfaces, RD_data_FIFO is written, and sequential is read according to AHB, feeds back to AHB interface.

Description of the drawings

The AHB that Fig. 1 one embodiment of the invention provides turns AXI controller block diagrams

The AHB_Slave_Convert state machines that Fig. 2 one embodiment of the invention provides

The AXI_Master_Convert state machines that Fig. 3 one embodiment of the invention provides

Specific embodiment

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.Following embodiment is only used for clearer Ground illustrates technical scheme of the present invention, and is not intended to limit the protection scope of the present invention and limits the scope of the invention.

One embodiment of the invention provides a kind of AHB and turns AXI protocol conversion method, and method and step is as follows：

1) AHB instructions are parsed, including read/write signal, address, burst information writes data etc..

2) AHB parsed is instructed, is stored in corresponding FIFO respectively, including instruction FIFO and write data FIFO.

3) if write operation, by read/write signal, address, burst information writes data etc. and is sent into the corresponding channels of AXI, Be converted to AXI protocol.And the write response signal that AXI interfaces are fed back is collected, it writes into WRITE RESPONSE FIFO instructions and works as Whether preceding write operation is correctly completed, while feeds back to AHB interface.

4) if read operation, then by the reading returned data of AXI interfaces, when RD_data_FIFO is written, and being read according to AHB Sequence feeds back to AHB interface.

AXI controller block diagrams are turned by the AHB that one embodiment of the invention provides as shown in Figure 1, specifically, including AHB Maste IP, AHB Slave Convert, AHB2AXI, AXI Slave IP, wherein AHB2AXI include AHB_Slave_ Convert modules, XI_Master_Convert modules, CMD_FIFO, WR_DATA_FIFO, WR_RESP_FIFO, RD_DATA_ FIFO。

Further, the controller realizes that AHB turns AXI and is as follows：

1. AHB_Slave_Convert modules receive the AHB instructions that AHB Master IP are sent first, and parse, from Read/write signal Hwrite, address signal Haddr, Hburst signal are taken out in AHB instructions, Hsize signals are write as one group of CMD Enter CMD_FIFO.

Using Hrequest signals as the write enable signal of CMD_FIFO, when the signal is high, and Htrans Value when be equal to 2 or 3, AHB instruction is just captured, in write-in CMD_FIFO.

And when CMD_FIFO is full, Hready is dragged down, AHB Master IP is made to stop the new AHB of input and are referred to It enables.

2. it is write order that if AHB_Slave_Convert modules, which are resolved to current AHB instructions, continue to Hwdata is written in WR_DATA_FIFO, and receives the write response that AXI Slave IP are fed back by write response channel Signal is written WR_RESP_FIFO, AHB Master IP is returned to by the Hresp signals of AHB.

3. it were read command that if AHB_Slave_Convert modules, which are resolved to current AHB instruction, AHB_Slave_ Convert modules receive the reading data signal that AXI Slave IP are fed back by reading data channel, and RD_DATA_ is written FIFO returns to AHB Master IP by the Hrdata signals of AHB.

4.AXI_Master_Convert modules read instruction from CMD_FIFO, and the instruction of reading is converted to AXI Sequential is sent to AXI Slave IP, if writing data command, then the Haddr signals in CMD is sent to writing for AXI buses Address tunnel, and the data of writing in WR_DATA_FIFO are read, write data channel is written, while receive AXI Slave IP and pass through The write response signal that write response channel returns, and the signal is returned into AHB_Slave_Convert modules.

If 5. the instruction that AXI_Master_Convert modules read instruction from CMD_FIFO be read data command, Haddr signals in CMD are sent to the reading address tunnel of AXI buses, and receives AXI Slave IP and is led to by reading data The reading data signal that road returns, and the signal is returned into AHB_Slave_Convert modules.

As shown in Fig. 2, for AHB_Slave_Convert state machines, wherein,

IDLE:Original state

RV_AHB_CMD：Receive AHB instructions

WR_CMD_FIFO：Write CMD_FIFO

WR_DATA_FIFO：Write WR_DATA_FIFO

RV_RESP：Receive write response order

RV_RD_DATA：It receives and reads returned data

Shown in Fig. 3, for AXI_Master_Convert state machines, IDLE:Original state

RD_CMD_FIFO：CMD_FIFO is read, and is parsed

WR_DATA_ADDR:The write data channel of AXI and write address channel will be transformed into induction signal

RV_WR_RESP：Receive the return signal of write response channel

WR_RD_ADDR：The reading address tunnel data of AXI will be converted to induction signal

RV_RD_DATA：Receive the returned data that AXI reads data channel

The present invention utilizes simple logic control and FIFO array, by AHB agreements first resolve to simple read-write, address, The signals such as data, and these signals are cached, then convert these signals into AXI timing protocols, complete the association between AHB to AXI View conversion, and seldom logical resource is only taken up, reduce system complexity, do not need to extra purchase connection-bridge IP, greatly Reduce project cost.

Term " computer system " according to the above embodiment including realizing system or performs the hardware of method, software sum number According to storage device.For example, computer system may include that central processing unit (CPU), input unit, output device and data are deposited Storage.Preferably, computer system has to provide the monitor (for example, commercial processes design) that visual output is shown.Data Storage may include RAM, disk drive or other computer-readable mediums.Computer system may include through the multiple of network connection Computing device, and can communicate with one another by the network.

The method of embodiment of above can be set as computer program or carry the computer program product of computer program Or computer-readable medium, the computer program perform the above method when being arranged to run on computers.

Term " computer-readable medium " including but not limited to can directly be read by computer or computer system or Any non-provisional media or medium that person accesses.The medium may include (but not limited to) such as floppy disk, hard disc storage medium and The magnetic storage medium of tape；The optical storage medium of such as CD or CD-ROM；The electric storage medium of such as memory, including RAM, ROM and flash memory；And above mixing and combination, such as magnetic optical storage medium.

The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention All any modification, equivalent and improvement made within refreshing and principle etc., should all be included in the protection scope of the present invention.

Claims

1. a kind of AHB turns AXI protocol switching controller, it is characterised in that：The controller is used to implement IP and band with AHB interface Normal communication between the IP of AXI interfaces, including AHB_Slave_Convert modules, AXI_Master_Convert modules, CMD_FIFO、WR_DATA_FIFO、WR_RESP_FIFO、RD_DATA_FIFO。

2. controller according to claim 1, it is characterised in that：AHB_Slave_Convert modules receive AHB The AHB instructions that Master IP are sent, and parse, read/write signal Hwrite, address signal Haddr are taken out from AHB instructions, CMD_FIFO is written as one group of CMD in Hburst signals, Hsize signals；Make Hrequest signals as writing for CMD_FIFO Energy signal when the signal is high and when the value of Htrans is equal to 2 or 3, just captures an AHB instruction, writes Enter in CMD_FIFO；And when CMD_FIFO is full, Hready is dragged down, AHB Master IP is made to stop inputting newly AHB is instructed.

3. controller according to claim 1, it is characterised in that：Work as if AHB_Slave_Convert modules are resolved to Preceding AHB instructions are write orders, then continue to Hwdata, be written in WR_DATA_FIFO, and receive AXI Slave IP and lead to The write response signal that write response channel is fed back is crossed, WR_RESP_FIFO is written, AHB is returned to by the Hresp signals of AHB Master IP。

4. controller according to claim 1, it is characterised in that：Work as if AHB_Slave_Convert modules are resolved to Preceding AHB instructions are read commands, then AHB_Slave_Convert modules receive AXI Slave IP and fed back to by reading data channel The reading data signal come, and RD_DATA_FIFO is written, AHB Master IP are returned to by the Hrdata signals of AHB.

5. controller according to claim 1, it is characterised in that：AXI_Master_Convert modules are from CMD_FIFO Instruction is read, and the instruction of reading is converted into AXI sequential and is sent to AXI Slave IP, if writing data command, then will Haddr signals in CMD are sent to the write address channel of AXI buses, and read the data of writing in WR_DATA_FIFO, and write-in is write Data channel, while the write response signal that AXI Slave IP are returned by write response channel is received, and the signal is returned to AHB_Slave_Convert modules.

6. controller according to claim 1, it is characterised in that：If AXI_Master_Convert modules are from CMD_ The instruction that instruction is read in FIFO is to read data command, then the reading address that the Haddr signals in CMD are sent to AXI buses leads to Road, and the reading data signal that AXI Slave IP are returned by reading data channel is received, and the signal is returned into AHB_ Slave_Convert modules.

7. a kind of AHB turns AXI protocol conversion method, it is characterised in that：This method comprises the following steps：1) AHB instructions are parsed, Including read/write signal, address, burst information writes data；2) AHB parsed is instructed, is stored in corresponding FIFO respectively, wrapped It includes instruction FIFO and writes data FIFO；3) if write operation, by read/write signal, address, burst information writes the feedings such as data The corresponding channels of AXI, are converted to AXI protocol, and collect the write response signal that AXI interfaces are fed back, and write into WRITE Whether RESPONSE FIFO instruction current write operations are correctly completed, while feed back to AHB interface；4) if read operation, then will The reading returned data of AXI interfaces is written RD_data_FIFO, and reads sequential according to AHB, feeds back to AHB interface.