CN108152599B - Wafer capacitance test method and test device - Google Patents
Wafer capacitance test method and test device Download PDFInfo
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- CN108152599B CN108152599B CN201711465714.XA CN201711465714A CN108152599B CN 108152599 B CN108152599 B CN 108152599B CN 201711465714 A CN201711465714 A CN 201711465714A CN 108152599 B CN108152599 B CN 108152599B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a capacitance testing method and a capacitance testing device for a wafer. The testing method comprises the steps of obtaining an error parasitic capacitance corresponding to a first testing position of a wafer, wherein the error parasitic capacitance is a parasitic capacitance of a testing circuit in capacitance testing equipment; acquiring a first measurement capacitance; acquiring an actual measured capacitance at the first test position of the wafer according to the error parasitic capacitance and the first measured capacitance at the first test position of the wafer; updating the error parasitic capacitance at the first test position of the wafer to the error parasitic capacitance at the second test position of the wafer; acquiring a second measurement capacitance; and acquiring the actual measured capacitance at the second test position of the wafer according to the updated error parasitic capacitance and the second measured capacitance until the actual measured capacitances of all the test positions of the wafer are acquired. By the technical scheme, the test accuracy of the actual capacitance of each test position of the wafer is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of capacitance testing, in particular to a method and a device for testing capacitance of a wafer.
Background
Static electricity exists in daily life, and the accumulation of static electricity has great damage to electronic products. In addition to reducing static buildup from a source, ESD protection is often added to electronic products or static-sensitive devices to prevent damage to the electronic products or devices due to static buildup. Different electronic products have different requirements on the parasitic capacitance of the ESD protective device, so that in the production process of the ESD device, people can screen the ESD device with unqualified parasitic capacitance by measuring the parasitic capacitance of the ESD device through test equipment.
The capacitance testing equipment generally measures the parasitic capacitance of the testing circuit of the capacitance testing equipment before measuring the parasitic capacitance of the device to be used as an error parasitic capacitance, and obtains the actual parasitic capacitance of the device according to the measured parasitic capacitance and the error parasitic capacitance.
Disclosure of Invention
The invention provides a capacitance testing method and a testing device for a wafer, after the actual tested capacitance at the current testing position of the wafer is obtained, the error parasitic capacitance for error correction is updated along with the change of the testing position of the wafer, the obtained actual tested capacitance is prevented from being influenced by the change of the error parasitic capacitance, the accuracy of the measured actual tested capacitance at each testing position of the wafer is improved, and the testing yield of the wafer capacitance is improved.
In a first aspect, an embodiment of the present invention provides a capacitance testing method for a wafer, where the capacitance testing method includes:
acquiring error parasitic capacitance corresponding to the first test position of the wafer, wherein the error parasitic capacitance is parasitic capacitance of a test circuit in capacitance test equipment;
measuring the capacitance of the wafer at a first test position to obtain a first measured capacitance;
acquiring an actual measured capacitance at the first test position of the wafer according to the error parasitic capacitance at the first test position of the wafer and the first measured capacitance;
updating the error parasitic capacitance corresponding to the first test position of the wafer to the error parasitic capacitance corresponding to the second test position of the wafer;
measuring the capacitance of the wafer at a second test position to obtain a second measured capacitance;
and acquiring actual measured capacitance at a second test position of the wafer according to the updated error parasitic capacitance and the second measured capacitance until the actual measured capacitance at all test positions of the wafer is acquired.
Further, the updating the error parasitic capacitance corresponding to the first test position of the wafer to the error parasitic capacitance corresponding to the second test position of the wafer comprises:
controlling a movable part of the capacitance testing equipment to move along a direction parallel to a plane where the wafer is located, so that a second testing position of the wafer is located below a detection part of the capacitance testing equipment, and the detection part is not in contact with the wafer in the moving process;
and acquiring the error parasitic capacitance corresponding to the second test position of the wafer, and updating the error parasitic capacitance corresponding to the first test position of the wafer to the error parasitic capacitance corresponding to the second test position of the wafer.
Further, the obtaining the error parasitic capacitance at the second test position corresponding to the wafer comprises:
and controlling a movable part of the capacitance testing equipment to move along a direction perpendicular to the plane of the wafer, and acquiring error parasitic capacitance corresponding to a second testing position of the wafer in the moving process of the movable equipment.
Further, the obtaining of the actual measured capacitance at the second test position of the wafer according to the updated error parasitic capacitance and the second measured capacitance until obtaining of the actual measured capacitances at all test positions of the wafer includes:
after the actual measured capacitance at the current test position of the wafer is obtained, updating the error parasitic capacitance corresponding to the current test position of the wafer to the error parasitic capacitance corresponding to the next test position of the wafer;
measuring the capacitance at the next test position to obtain the measured capacitance at the next test position;
and acquiring the actual measured capacitance of the next test position according to the error parasitic capacitance corresponding to the next test position and the measured capacitance at the next test position until the actual measured capacitances of all the test positions of the wafer are acquired.
Further, measuring capacitance at any test position of the wafer, and acquiring the measured capacitance at the test position includes:
controlling a movable part of the capacitance testing equipment to move along a direction parallel to a plane where the wafer is located, so that a detection part of the capacitance testing equipment is located above the testing position of the wafer, and the detection part is not in contact with the wafer in the moving process; and controlling the probe component to contact with the wafer, measuring the capacitance at the test position, and acquiring the measured capacitance at the test position.
Further, the movable component is a stage.
Further, the test circuit includes a probe part, a movable part, a circuit where the wafer is electrically connected with the probe part, and a circuit where the wafer is electrically connected with the movable part.
Further, the actual measured capacitance at any test position of the wafer is equal to the difference between the measured capacitance at the test position and the error parasitic capacitance corresponding to the test position.
In a second aspect, an embodiment of the present invention further provides a capacitance testing apparatus for a wafer, where the capacitance testing apparatus for a wafer includes:
the error parasitic capacitance acquisition module is used for acquiring error parasitic capacitance at a corresponding wafer test position, wherein the error parasitic capacitance is parasitic capacitance of a test circuit in the capacitance test equipment;
the measurement capacitance acquisition module is used for acquiring the measurement capacitance at the wafer test position;
the updating module is used for updating the error parasitic capacitance corresponding to a testing position of the wafer to the error parasitic capacitance corresponding to the next testing position of the wafer;
and the actual measured capacitor obtaining module is used for obtaining the actual measured capacitor at the test position of the wafer according to the error parasitic capacitor and the measurement capacitor at the same test position of the corresponding wafer until obtaining the actual measured capacitors at all the test positions of the wafer.
Further, the air conditioner is provided with a fan,
the update module is specifically configured to:
controlling a movable part of the capacitance testing equipment to move along a direction parallel to a plane where the wafer is located, so that a second testing position of the wafer is located below a detection part of the capacitance testing equipment, and the detection part is not in contact with the wafer in the moving process;
and controlling a movable part of the capacitance testing equipment to move along a direction vertical to the plane of the wafer, acquiring the error parasitic capacitance corresponding to the second testing position of the wafer in the moving process of the movable equipment, and updating the error parasitic capacitance corresponding to the first testing position of the wafer to the error parasitic capacitance corresponding to the second testing position of the wafer.
And the delay module is used for acquiring the error parasitic capacitance corresponding to the next test position when the error parasitic capacitance module updates the error parasitic capacitance delay.
The method and the device obtain the actual parasitic capacitance of the current test position of the wafer according to the error parasitic capacitance of the current test position of the corresponding wafer and the measured parasitic capacitance of the current test position, and then update the error parasitic capacitance of the current test position of the corresponding wafer to the error parasitic capacitance of the next test position of the corresponding wafer, namely after the actual parasitic capacitance of the current test position of the wafer is obtained, the error parasitic capacitance for error correction is updated along with the change of the test position of the wafer, so that the obtained actual parasitic capacitance is prevented from being influenced by the change of the error parasitic capacitance, the accuracy of the measured actual parasitic capacitance of each test position of the wafer is improved, and the test yield of the wafer capacitance is improved.
Drawings
Fig. 1 is a flowchart illustrating a method for testing capacitance of a wafer according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating another method for testing capacitance of a wafer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a wafer capacitance testing apparatus according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic flow chart of a method for testing a capacitance of a wafer according to an embodiment of the present invention, where the embodiment is applicable to a scenario where a capacitance of a wafer needs to be tested, and the method can be executed by a device for testing a capacitance of a wafer according to an embodiment of the present invention, and specifically includes the following steps:
s110, obtaining an error parasitic capacitance corresponding to the first testing position of the wafer, wherein the error parasitic capacitance is a parasitic capacitance of a testing circuit in the capacitance testing equipment.
Specifically, the error parasitic capacitance of the wafer is a parasitic capacitance of a test circuit in the capacitance test apparatus, and for example, the capacitance test apparatus includes a movable part, the movable part may be a stage, the probing part may be a probe, and the test circuit of the capacitance test apparatus includes, for example, the probing part, the movable part, a circuit where the wafer is electrically connected to the probing part, and a circuit where the wafer is electrically connected to the movable part, where the circuit where the wafer is electrically connected to the probing part and the circuit where the wafer is electrically connected to the movable part may include devices such as switches, connectors, and the like.
Specifically, the parasitic capacitance of the test circuit is mainly divided into two types, one type is generated among the probe components corresponding to different electrodes in the wafer and among the circuits connected with the wafer and the probe components, the other type is generated among the probe components, the circuits connected with the wafer and the probe components, the movable components and the circuits connected with the wafer and the movable components, the parasitic capacitance of the two types of test circuits is related to the wafer test position, when the test position of the wafer is changed, the relative positions of the probe components, the movable components and the circuits connected with the probe components and the movable components are changed, and the error parasitic capacitance is changed. Particularly, for the parasitic capacitance of the second type of test line, when the test position of the wafer changes, the relative position between the probe unit and the movable unit changes, that is, the relative area between the probe unit and the movable unit changes, and the parasitic capacitance of the test line changes.
When the error parasitic capacitance corresponding to the first test position of the wafer is obtained, the movable part of the capacitance test equipment can be controlled to move along the direction parallel to the plane where the wafer is located, so that the detection part of the capacitance test equipment is located above the first test position of the wafer, and the detection part of the capacitance test equipment is not in contact with the wafer.
S120, measuring the capacitance of the first test position of the wafer to obtain a first measured capacitance.
For example, the movable component of the capacitance testing apparatus may be controlled to move in a direction parallel to the plane of the wafer, so that the probing component of the capacitance testing apparatus, such as the probe, is located above the first testing position of the wafer, and the probing component is controlled not to contact with the wafer during the moving, the probing component of the capacitance testing apparatus is controlled to contact with the wafer, and the capacitance at the first testing position of the wafer is measured to obtain the first measured capacitance.
Illustratively, the wafer capacitance can be divided into two categories, one is the parasitic capacitance between different electrodes on the front side of the wafer, and the other is the parasitic capacitance between the front side electrode and the back side electrode of the wafer, where the first measured capacitance includes the parasitic capacitance between the different electrodes on the front side and the parasitic capacitance between the front side electrode and the back side electrode at the first test position of the wafer.
S130, obtaining an actual measured capacitance at the first test position of the wafer according to the error parasitic capacitance and the first measured capacitance at the first test position of the corresponding wafer.
For example, the actual measured capacitance and the error parasitic capacitance at the same position of the wafer may be in a parallel relationship, the measured capacitance at the position of the wafer is equal to the sum of the actual measured capacitance and the error parasitic capacitance at the position of the wafer, and for the first test position of the wafer, the actual measured capacitance at the first test position corresponding to the wafer is equal to the difference between the measured capacitance at the first test position and the error parasitic capacitance at the corresponding first test position. The measured capacitance at the first test position of the wafer may be set, that is, the first measured capacitance is Cm1, and the error parasitic capacitance corresponding to the first test position of the wafer is Cps, so that the actual measured capacitance C1 at the first test position of the wafer satisfies the following calculation formula:
C1＝Cm1-Cps
s140, updating the error parasitic capacitance at the first testing position of the corresponding wafer to the error parasitic capacitance at the second testing position of the corresponding wafer.
For example, the movable part of the capacitance testing device can be controlled to move along the direction parallel to the plane of the wafer, so that the second testing position of the wafer is positioned below the detection part of the capacitance testing device, and the detection part is not contacted with the wafer during the movement; and acquiring the error parasitic capacitance at the second testing position of the corresponding wafer, and updating the error parasitic capacitance at the first testing position of the corresponding wafer to the error parasitic capacitance at the second testing position of the corresponding wafer.
For example, the movable component of the capacitance testing device can be controlled to move along the direction vertical to the plane of the wafer, and the error parasitic capacitance at the second testing position of the corresponding wafer is acquired during the movement of the movable component.
Specifically, after the actual measured capacitance at the first test position of the wafer is measured, the error parasitic capacitance at the second test position of the wafer needs to be measured. When the error parasitic capacitance at the second test position of the wafer is measured, the movable part of the capacitance test equipment is moved to enable the detection part to be located above the second test position of the wafer, and in the moving process of the movable part, the parasitic capacitance of a test circuit in the capacitance test equipment, namely the error parasitic capacitance, is changed.
The movable component of the capacitance testing equipment is controlled to move along the direction parallel to the plane of the wafer, so that the second testing position of the wafer is positioned below the detection component.
When the error parasitic capacitance corresponding to the second test position of the wafer is obtained, the movable component of the capacitance test equipment is controlled to move along the direction perpendicular to the plane of the wafer, before the detection component contacts with the second test position of the wafer, the error parasitic capacitance corresponding to the second test position of the wafer is obtained in the moving process of the movable component, and compared with the method that the error of the second test position of the wafer is measured after the detection component contacts with the second test position of the wafer, the error parasitic capacitance corresponding to the test position of the wafer is accurately obtained, and meanwhile, the test efficiency is improved.
The distance between the second testing position of the wafer and the first testing position of the wafer in the plane of the wafer can be larger than or equal to the distance between any devices in the wafer. For example, when the first test position of the wafer is located at one of the devices (e.g., a device) of the wafer, the second test position of the wafer may be located at a device adjacent to the a device or at another device that is n devices apart from the a device (n is an integer greater than or equal to 1). When the first test position and the second test position are separated by n devices, the error parasitic capacitance at the first test position is adopted when the capacitance of the device in front of the second test position of the wafer is tested. And when the detection component is positioned at the second test position, acquiring the error parasitic capacitance of the wafer at the second test position.
S150, measuring the capacitance of the second test position of the wafer to obtain a second measured capacitance.
For example, the movable component of the capacitance testing apparatus may be controlled to move in a direction parallel to the plane of the wafer, so that the probing component of the capacitance testing apparatus, such as the probe, is located above the second testing position of the wafer, and the probing component is controlled not to contact with the wafer during the moving process, the probing component of the capacitance testing apparatus is controlled to contact with the wafer, the capacitance at the second testing position of the wafer is measured, and the second measured capacitance is obtained.
The detection component is in contact with the second testing position of the wafer to realize electric connection, the movable component sends a testing start signal to the capacitance testing equipment, the capacitance testing equipment executes the testing process of the testing program in the testing software after receiving the testing start signal, the capacitance at the second testing position of the wafer is measured, and the obtained second measured capacitance is stored.
And S160, acquiring the actual measured capacitance at the second test position of the wafer according to the updated error parasitic capacitance and the second measured capacitance until the actual measured capacitances at all the test positions of the wafer are acquired.
For example, the actual measured capacitance and the error parasitic capacitance at the same position of the wafer may be in a parallel relationship, the measured capacitance at the position of the wafer is equal to the sum of the actual measured capacitance and the error parasitic capacitance at the position of the wafer, and for the second test position of the wafer, the actual measured capacitance at the second test position corresponding to the wafer is equal to the difference between the measured capacitance at the second test position and the error parasitic capacitance at the corresponding second test position. The measured capacitance at the second testing position of the wafer may be set, that is, the second measured capacitance is Cm2, and the error parasitic capacitance corresponding to the second testing position of the wafer is Cps, so that the actual measured capacitance C2 at the second testing position of the wafer satisfies the following calculation formula:
C2＝Cm2-Cps
specifically, in the whole testing process of the capacitance testing equipment, after the actual tested capacitance at the current testing position of the wafer is obtained, the error parasitic capacitance at the current testing position of the corresponding wafer is updated to the error parasitic capacitance at the next testing position of the corresponding wafer; measuring the capacitance at the next test position to obtain the measured capacitance at the next test position; and acquiring the actual measured capacitance of the next test position according to the error parasitic capacitance corresponding to the next test position and the measured capacitance at the next test position, namely, circularly re-reading the steps S110 to S140 until the actual measured capacitances of all the test positions of the wafer are acquired.
And by analogy, after the actual measured capacitance at the second test position of the wafer is measured, sequentially measuring the error parasitic capacitance and the measured capacitance at other test positions of the wafer according to the sequence, and calculating the actual measured capacitance at other test positions of the wafer until the actual measured capacitance at all test positions of the wafer is obtained, thereby completing the test of the actual measured capacitance at all test positions of the wafer.
According to the technical scheme of the embodiment, the actual measured capacitance of the current test position of the wafer is obtained according to the error parasitic capacitance of the current test position of the corresponding wafer and the measurement capacitance of the current test position, and then the error parasitic capacitance of the current test position of the corresponding wafer is updated to the error parasitic capacitance of the next test position of the corresponding wafer, namely after the actual measured capacitance of the current test position of the wafer is obtained, the error parasitic capacitance for error correction is updated along with the change of the test position of the wafer, the fact that the obtained actual measured capacitance is influenced by the change of the error parasitic capacitance is avoided, the accuracy of the measured actual capacitance of each test position of the wafer obtained through measurement is improved, and the test yield of the wafer capacitance is improved.
Fig. 2 is a flowchart of another wafer capacitance testing method according to an embodiment of the present invention, which may also be applied to a scenario where a capacitor of a wafer needs to be tested, and may be executed by the wafer capacitance testing apparatus according to the embodiment of the present invention, as shown in fig. 2, the testing method includes:
s210, the slide holder moves to the initial test position.
S220, obtaining the error parasitic capacitance at the initial test position of the corresponding wafer.
And S230, starting automatic testing.
S240, judging whether the test of all the test positions of the wafer is finished.
When the testing of all the testing positions of the wafer is completed, the method for testing the capacitance of the wafer provided by the embodiment of the invention further comprises the following steps:
and S251, completing the test.
At this point, the test of the capacitance of the wafer is finished.
When the testing of all the testing positions of the wafer is not completed, the method for testing the capacitance of the wafer provided by the embodiment of the invention further comprises the following steps:
and S250, the probe card sends a test starting signal to the capacitance test equipment, and the wafer carrying table moves upwards along the direction vertical to the plane of the wafer, so that the probe is in contact with the current test position of the wafer.
And S260, measuring the capacitance of the current test position of the wafer, and obtaining the measured capacitance of the current test position.
And S270, acquiring the actual measured capacitance at the current test position of the wafer according to the error parasitic capacitance and the measured capacitance at the current test position of the corresponding wafer.
And S280, the capacitance testing equipment sends a parameter grading signal and a current testing end signal to the probe card.
And S290, moving the slide holder to the next testing position, wherein the probe is not contacted with the wafer in the moving process.
While performing step S290, the method further includes:
and S291 delaying.
And when the capacitance testing equipment sends a parameter grading signal and a current testing end signal to the probe card, starting time delay for ensuring that the probe is disconnected with the current testing position of the wafer when the error parasitic capacitance at the next testing position of the wafer is tested.
S292, updating the error parasitic capacitance at the current testing position of the wafer to the error parasitic capacitance at the next testing position of the wafer.
The movable member is illustratively provided here as a stage and the probing members are probes on a probe card.
The capacitance testing equipment comprises a wafer carrying table and a probe card, wherein the probe card is provided with at least one probe. In the wafer testing process, generally, the capacitance testing equipment moves the slide holder to make the probes contact with different testing positions of the wafer. The side of the wafer having the devices is referred to as the front side of the wafer, and the side opposite thereto is referred to as the back side of the wafer. The electrode on the front side of the wafer is connected with the capacitance testing equipment through a probe through a lead, and the electrode on the back side of the wafer is led out through the slide holder and then is connected with the capacitance testing equipment through a lead.
During the testing process, the slide holder in the capacitance testing equipment can be controlled by testing software in the capacitance testing equipment. For example, the capacitance testing apparatus may include testing software including a testing program, and the slide stage of the capacitance testing apparatus is controlled to move in a direction parallel to the plane of the wafer through an interactive interface of the testing software, so that the probe of the capacitance testing apparatus is located above the initial testing position of the wafer, and the wafer testing program is invoked. In the process of loading the test program by the test software, the capacitance test equipment tests the parasitic capacitance of the test circuit corresponding to the initial test position of the wafer, and stores the parasitic capacitance of the test circuit into the error parasitic capacitance.
And after the loading of the wafer test program is finished, starting automatic test through an interactive interface of the test software, judging whether the wafer completes the test of all test positions, and when the test of all test positions of the wafer is finished, completing the test of the wafer. When all the testing positions of the wafer are not finished, the slide glass table moves upwards along the direction vertical to the plane of the wafer, so that the probe is contacted with the wafer at the initial testing position to realize electric connection. After the probe and the wafer are electrically connected at the initial test position, the probe sends a test start signal to the capacitance test equipment, the capacitance test equipment executes a test process of a test program in test software after receiving the test start signal, measures the capacitance at the first test position of the wafer, and stores the obtained first measured capacitance.
And acquiring the actual measured capacitance at the current test position of the wafer according to the error parasitic capacitance and the measured capacitance at the current test position of the corresponding wafer. When the actual measured capacitance at any test position of the wafer is measured, the actual measured capacitance at any test position of the wafer and the parasitic capacitance of the test circuit at any test position of the wafer are in parallel connection, so that the capacitance value of any measured capacitance is the sum of the capacitance values of the two capacitors, and the actual measured capacitance at any test position of the wafer is equal to the difference value between the measured capacitance at the test position and the error parasitic capacitance corresponding to the test position. The capacitance Cj of the actual measured capacitor at any test position of the wafer is as follows:
Cj＝Cmj-Cps
where Cmj is the capacitance value of the jth measured capacitance at the jth test location.
After the operation of the test program in the test software of the capacitance test equipment is finished, the measurement of the actual measured capacitance at the initial test position of the wafer is finished, and at the moment, the capacitance test equipment sends a parameter grading signal and a current test finishing signal to the probe. The parametric binning signal classifies the devices in the first test site of the wafer, for example, the devices may be classified into both pass and fail categories, or may include other categories, so as to determine the yield of the devices in the wafer at a later time. The current end-of-test signal is a signal indicating that the inspection of the device at the current position of the wafer is finished, so that the inspection of the device at the next test position of the wafer is performed. Generally, the end of the test program in the test software of the capacitance test device is taken as a sending condition of the current test end signal. When the probe receives a parameter grading signal and a current test ending signal sent by the capacitance test equipment, the capacitance test equipment controls the slide glass table to move downwards along a direction vertical to the plane of the wafer, so that the probe is disconnected from the initial test position of the wafer, and controls the slide glass table to move horizontally along a direction parallel to the plane of the wafer, so that the probe is positioned above the next test position of the wafer, and at the moment, the probe and the next test position of the wafer are in a disconnected state.
After the capacitance testing equipment sends the parameter grading signal and the current testing end signal to the probe, two processes of testing the error parasitic capacitance of the next testing position of the wafer and controlling the slide holder to move to the next testing position of the wafer are carried out simultaneously. For the stage with different specifications, the time taken for the stage to move to the next test position of the wafer is different, and generally it takes several tens to several hundreds of milliseconds. Typically, the time taken to test the error parasitic capacitance at the next test position of the wafer is shorter than the time taken to move the movable component toward the second test position of the wafer. In order to disconnect the probe from the first test position of the wafer when testing the error parasitic capacitance at the next test position of the wafer, a delay procedure needs to be added after the test procedure in the test software is finished, so as to ensure that the probe is disconnected from the current test position of the wafer when testing the error parasitic capacitance at the next test position of the wafer. The delay value in the delay program needs to be debugged according to the specification of the slide holder, and the probe approaches the next testing position of the wafer when the error parasitic capacitance at the next testing position of the wafer is tested as much as possible. In addition, at the end of testing the error parasitic capacitance at the next test location of the wafer, the probe is not in contact with the next test location of the wafer.
And after testing the error parasitic capacitance at the next testing position of the wafer, circulating, detecting whether the testing at all the testing positions is finished or not by the testing program, and circulating the testing process when the testing at all the testing positions is not finished.
Fig. 3 is a schematic structural diagram of a wafer capacitance testing apparatus according to an embodiment of the present invention, and as shown in fig. 3, the wafer capacitance testing apparatus includes:
an error parasitic capacitance obtaining module 10, configured to obtain an error parasitic capacitance at a corresponding wafer test position, where the error parasitic capacitance is a parasitic capacitance of a test circuit in a capacitance test device;
a measured capacitance obtaining module 20, configured to obtain a measured capacitance at a wafer test position;
an updating module 30, configured to update the error parasitic capacitance at a test position corresponding to a wafer to the error parasitic capacitance at a next test position corresponding to the wafer;
and the actual measured capacitance obtaining module 40 is configured to obtain actual measured capacitances at the test positions of the wafer according to the error parasitic capacitance and the measurement capacitance at the same test position of the corresponding wafer until actual measured capacitances at all the test positions of the wafer are obtained.
Optionally, the update module 30 may be specifically configured to control the movable component of the capacitance testing apparatus to move along a direction parallel to the plane of the wafer, so that the second testing position of the wafer is located below the detecting component of the capacitance testing apparatus, and the detecting component is not in contact with the wafer during the moving process;
and controlling the movable part of the capacitance testing equipment to move along the direction vertical to the plane of the wafer, acquiring the error parasitic capacitance at the second testing position of the corresponding wafer in the moving process of the movable equipment, and updating the error parasitic capacitance at the first testing position of the corresponding wafer to the error parasitic capacitance at the second testing position of the corresponding wafer.
According to the method, the actual measured capacitance at the current testing position of the wafer is obtained according to the error parasitic capacitance at the current testing position of the corresponding wafer and the measuring capacitance at the current testing position of the wafer, and then the error parasitic capacitance at the current testing position of the corresponding wafer is updated to the error parasitic capacitance at the next testing position of the corresponding wafer, namely after the actual measured capacitance at the current testing position of the wafer is obtained, the error parasitic capacitance for error correction is updated along with the change of the testing position of the wafer, the obtained actual measured capacitance is prevented from being influenced by the change of the error parasitic capacitance, the accuracy of the measured capacitance at each testing position of the wafer obtained by measurement is improved, and the testing yield of the capacitance of the wafer is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. A capacitance test method of a wafer is characterized by comprising the following steps:
acquiring error parasitic capacitance corresponding to the first test position of the wafer, wherein the error parasitic capacitance is parasitic capacitance of a test circuit in capacitance test equipment;
measuring the capacitance of the wafer at a first test position to obtain a first measured capacitance;
acquiring an actual measured capacitance at the first test position of the wafer according to the error parasitic capacitance at the first test position of the wafer and the first measured capacitance;
updating the error parasitic capacitance corresponding to the first test position of the wafer to the error parasitic capacitance corresponding to the second test position of the wafer;
measuring the capacitance of the wafer at a second test position to obtain a second measured capacitance;
obtaining actual measured capacitance at a second test position of the wafer according to the updated error parasitic capacitance and the second measured capacitance until obtaining actual measured capacitance at all test positions of the wafer;
the updating the error parasitic capacitance corresponding to the first test position of the wafer to the error parasitic capacitance corresponding to the second test position of the wafer comprises:
controlling a movable part of the capacitance testing equipment to move along a direction parallel to a plane where the wafer is located, so that a second testing position of the wafer is located below a detection part of the capacitance testing equipment, and the detection part is not in contact with the wafer in the moving process;
and acquiring the error parasitic capacitance corresponding to the second test position of the wafer, and updating the error parasitic capacitance corresponding to the first test position of the wafer to the error parasitic capacitance corresponding to the second test position of the wafer.
2. The capacitance testing method of claim 1, wherein the obtaining the error parasitic capacitance at the second test location corresponding to the wafer comprises:
and controlling a movable part of the capacitance testing equipment to move along a direction perpendicular to the plane of the wafer, and acquiring error parasitic capacitance corresponding to a second testing position of the wafer in the moving process of the movable equipment.
3. The capacitance testing method according to claim 1, wherein the obtaining actual measured capacitances at the second test positions of the wafer according to the updated error parasitic capacitances and the second measured capacitances until obtaining actual measured capacitances at all test positions of the wafer comprises:
after the actual measured capacitance at the current test position of the wafer is obtained, updating the error parasitic capacitance corresponding to the current test position of the wafer to the error parasitic capacitance corresponding to the next test position of the wafer;
measuring the capacitance at the next test position to obtain the measured capacitance at the next test position;
and acquiring the actual measured capacitance of the next test position according to the error parasitic capacitance corresponding to the next test position and the measured capacitance at the next test position until the actual measured capacitances of all the test positions of the wafer are acquired.
4. The capacitance test method according to claim 1, wherein measuring the capacitance at any test location on the wafer, and obtaining the measured capacitance at the test location comprises:
controlling a movable part of the capacitance testing equipment to move along a direction parallel to a plane where the wafer is located, so that a detection part of the capacitance testing equipment is located above the testing position of the wafer, and the detection part is not in contact with the wafer in the moving process;
and controlling the probe component to contact with the wafer, measuring the capacitance at the test position, and acquiring the measured capacitance at the test position.
5. The capacitance testing method of any one of claims 1 or 4, wherein the movable member is a stage.
6. The capacitance testing method according to claim 1 or 4, wherein the test lines include a probe part, a movable part, a line in which a wafer is electrically connected to the probe part, and a line in which a wafer is electrically connected to the movable part.
7. The capacitance testing method according to claim 1, wherein the actual measured capacitance at any one test position on the wafer is equal to the difference between the measured capacitance at the test position and the error parasitic capacitance corresponding to the test position.
8. A capacitance testing device for a wafer is characterized by comprising:
the error parasitic capacitance acquisition module is used for acquiring error parasitic capacitance at a corresponding wafer test position, wherein the error parasitic capacitance is parasitic capacitance of a test circuit in the capacitance test equipment;
the measurement capacitance acquisition module is used for acquiring the measurement capacitance at the wafer test position;
the updating module is used for updating the error parasitic capacitance corresponding to a testing position of the wafer to the error parasitic capacitance corresponding to the next testing position of the wafer;
the actual measured capacitor obtaining module is used for obtaining actual measured capacitors at the test positions of the wafer according to the error parasitic capacitors and the measurement capacitors at the same test positions of the corresponding wafer until the actual measured capacitors at all the test positions of the wafer are obtained;
the update module is specifically configured to:
controlling a movable part of the capacitance testing equipment to move along a direction parallel to a plane where the wafer is located, so that a second testing position of the wafer is located below a detection part of the capacitance testing equipment, and the detection part is not in contact with the wafer in the moving process;
and controlling a movable part of the capacitance testing equipment to move along a direction vertical to the plane of the wafer, acquiring the error parasitic capacitance corresponding to the second testing position of the wafer in the moving process of the movable equipment, and updating the error parasitic capacitance corresponding to the first testing position of the wafer to the error parasitic capacitance corresponding to the second testing position of the wafer.
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| US6008660A (en) * | 1996-08-22 | 1999-12-28 | International Business Machines Corporation | Method for developing circuit capacitance measurements corrected for stray capacitance |
| TW464764B (en) * | 2000-06-14 | 2001-11-21 | Faraday Tech Corp | Measurement circuit of chip capacitance |
| TW472335B (en) * | 2001-01-31 | 2002-01-11 | Nat Science Council | Structure for measuring parasitic capacitance of metal interconnects and its measuring method |
| CN102043096A (en) * | 2009-10-15 | 2011-05-04 | 瑞鼎科技股份有限公司 | Capacitance measurement circuit and method |
| CN103969511A (en) * | 2014-05-27 | 2014-08-06 | 上海先进半导体制造股份有限公司 | Measuring method for capacity parameters of each chip on silicon chip |
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