CN108122894B - Method for improving arc discharge defect of MIM capacitor - Google Patents
Method for improving arc discharge defect of MIM capacitor Download PDFInfo
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- CN108122894B CN108122894B CN201611073794.XA CN201611073794A CN108122894B CN 108122894 B CN108122894 B CN 108122894B CN 201611073794 A CN201611073794 A CN 201611073794A CN 108122894 B CN108122894 B CN 108122894B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
The invention provides a method for improving the arc discharge defect of an MIM capacitor, which comprises the following steps: providing a semiconductor substrate, and forming an interlayer dielectric layer on the surface of the semiconductor substrate; forming a groove exposing the semiconductor substrate in the interlayer dielectric layer; forming a conductive layer on the bottom wall and the side wall of the groove; forming a lower electrode on the conducting layer and the interlayer dielectric layer; forming a filling structure between the lower electrodes in the groove; and sequentially forming an inter-electrode dielectric layer and an upper electrode on the lower electrode and the filling structure from bottom to top, wherein the lower electrode, the inter-electrode dielectric layer and the upper electrode form an MIM capacitor. In the invention, when the upper electrode is formed, the flat surface can avoid the formation of point discharge in the MIM capacitor and prevent the formation of arc discharge defects in the interelectrode dielectric layer, thereby improving the performance of the device and improving the yield.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for improving an arc discharge defect of an MIM capacitor.
Background
Capacitive elements are commonly used as electronic passive devices in integrated circuits such as radio frequency ICs, monolithic microwave ICs, smart cards, and the like. Currently, common capacitor devices include Metal Oxide Semiconductor (MOS) capacitors, PN junction capacitors, and MIM (metal-insulator-metal, MIM) capacitors. Since both the MOS capacitor and the PN junction capacitor are limited in their own structures, the electrodes easily generate a hole layer during operation, resulting in a decrease in frequency characteristics. While MIM capacitors can provide better frequency and temperature dependent characteristics, MIM capacitors can provide better electrical characteristics than MOS capacitors or PN junction capacitors.
The MIM capacitor formed in the prior art comprises a lower electrode, an interelectrode dielectric layer and an upper electrode which are positioned on an interlayer dielectric layer, and a groove is usually formed in the interlayer dielectric layer while the MIM capacitor is formed, so that the parasitic MIM capacitor positioned in the groove is usually included in the device. In addition, the generation rate of arcing defects of the parasitic MIM capacitor is 10-15%, which causes the failure rate (kill rate) of the device to be 30-50%, and seriously affects the yield of the device.
Disclosure of Invention
The invention aims to provide a method for improving the arc discharge defect of an MIM capacitor, which solves the technical problem of the arc discharge defect existing in a parasitic MIM capacitor at a groove in the prior art.
In order to solve the above technical problem, the present invention provides a method for improving the arc discharge defect of an MIM capacitor, comprising:
providing a semiconductor substrate, and forming an interlayer dielectric layer on the surface of the semiconductor substrate;
forming a groove exposing the semiconductor substrate in the interlayer dielectric layer;
forming a conductive layer on the bottom wall and the side wall of the groove;
forming a lower electrode on the conducting layer and the interlayer dielectric layer;
forming a filling structure between the lower electrodes in the groove; and
and sequentially forming an inter-electrode dielectric layer and an upper electrode on the lower electrode and the filling structure from bottom to top, wherein the lower electrode, the inter-electrode dielectric layer and the upper electrode form an MIM capacitor.
Optionally, the method further includes: and forming a through hole exposing the semiconductor substrate in the interlayer dielectric layer, wherein the width of the groove is greater than that of the through hole.
Optionally, the width of the trench is 0.8 μm to 2.0 μm, and the width of the via is 500nm to 1000 nm.
Optionally, the conductive layer also completely fills the via.
Optionally, the semiconductor substrate includes a multilayer interconnection structure, and the conductive layer is electrically connected to the multilayer interconnection structure.
Optionally, the conductive layer is made of metal tungsten.
Optionally, the lower electrode includes a first metal nitride layer, a metal layer, and a second metal nitride layer stacked in sequence from bottom to top.
Optionally, the first metal nitride layer is titanium nitride or tantalum nitride, and the thickness of the first nitride layer is 20nm to 50 nm.
Optionally, the metal layer is metal aluminum or metal copper, and the thickness of the metal layer is 50nm to 200 nm.
Optionally, the second metal nitride layer is titanium nitride or tantalum nitride, and the thickness of the second nitride layer is 20nm to 50 nm.
Optionally, the step of forming the filling structure includes:
forming a filling layer, wherein the filling layer fills the groove completely and covers the lower electrode;
and chemically and mechanically grinding the filling layer, removing the filling layer on the lower electrode to form the filling structure, and forming a flat surface between the filling structure and the lower electrode.
Optionally, the filling layer is formed by a chemical vapor deposition process.
Optionally, the material of the filling layer is silicon dioxide.
Optionally, the inter-electrode dielectric layer is formed by a plasma enhanced chemical vapor deposition process.
Optionally, the inter-electrode dielectric layer is one or a combination of silicon nitride, silicon oxide and silicon oxynitride, and the thickness of the inter-electrode dielectric layer is 20nm to 100 nm.
Optionally, the upper electrode is formed by a physical vapor deposition process.
Optionally, the upper electrode is made of metal aluminum or metal copper, and the thickness of the upper electrode is 50nm to 200 nm.
Compared with the prior art, in the method for improving the arc discharge defect of the MIM capacitor, the filling structure is formed on the lower electrode, and the filling structure completely fills the region between the groove and the lower electrode, so that a flat plane is formed between the lower electrode and the filling structure. And then, forming an interelectrode dielectric layer and an upper electrode on the surfaces of the lower electrode and the filling structure, wherein when the upper electrode is formed, the flat surface can avoid the formation of point discharge in the MIM capacitor and prevent the formation of arc discharge defects in the interelectrode dielectric layer, thereby improving the performance of the device and improving the yield.
Drawings
FIG. 1 is a flow chart of a method for fabricating a MIM capacitor according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a semiconductor substrate and an interlayer dielectric layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure for forming trenches and vias according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure for forming a conductive layer according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating the formation of an upper electrode and a filling layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a filling structure formed according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an inter-electrode dielectric layer and an upper electrode according to an embodiment of the present invention.
Detailed Description
The method of ameliorating MIM capacitor arcing defects of the present invention will now be described in greater detail with reference to the schematic drawings, wherein preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous results of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the invention is to provide a method for improving the arc discharge defect of the MIM capacitor, wherein a filling structure is formed on the lower electrode, and the filling structure completely fills the region between the trench and the lower electrode, so that a flat plane is formed between the lower electrode and the filling structure. And then, forming an interelectrode dielectric layer and an upper electrode on the surfaces of the lower electrode and the filling structure, wherein when the upper electrode is formed, the flat surface can avoid the formation of point discharge in the MIM capacitor and prevent the formation of arc discharge defects in the interelectrode dielectric layer, thereby improving the performance of the device and improving the yield.
The following describes in detail the preparation of the MIM capacitor according to the present invention with reference to the accompanying drawings, where fig. 1 is a flowchart of a method for preparing the MIM capacitor, and fig. 2 to 7 are schematic structural diagrams corresponding to respective steps, and the method for improving the arc discharge defect of the MIM capacitor according to the present invention specifically includes the following steps:
first, step S1 is executed, and referring to fig. 2, a semiconductor substrate 100 is provided, where the semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbon substrate, an SOI substrate, or other substrate structures commonly used in the art. The semiconductor substrate 100 of the present invention includes device structures (not shown), such as amplifiers, digital-to-analog converters, analog processing circuits and/or digital processing circuits, interface circuits, etc., and the methods for forming these device structures may be CMOS processes. The semiconductor substrate 100 further includes a multi-layer interconnect structure located on the device structure, and the interconnect structure is electrically connected to the device structure. The interconnect structure may include plugs and interconnect lines, and fig. 2 shows only one layer of interconnect structure 101, and the specific structure needs to be determined according to actual situations. An interlayer dielectric layer 110 is formed on the surface of the semiconductor substrate 100, the interlayer dielectric layer is one or a combination of silicon oxide, silicon nitride or silicon oxynitride, and the interlayer dielectric layer 101 is used for forming electrical isolation in a subsequent process.
Step S2 is executed, and referring to fig. 3, a Trench (Trench)112 exposing the semiconductor substrate 100 is formed in the interlayer dielectric layer 110. In addition, the method of the present invention further includes forming a Via hole (Via)111 exposing the semiconductor substrate 100 in the interlayer dielectric layer 110 while forming the trench 112, and the width of the trench 112 is greater than the width of the Via hole 111. The via 111 is used for filling metal later, and is electrically connected to the interconnect structure 101 to electrically connect the device structure, and the trench 112 is used to form a guard ring, a Scribe line, or a lithographic mark, for example, a trench used to form a lithographic mark such as an SPM mark, an AGA mark, an Over layer mark, an overlay measurement mark, or a guard ring (Sealingring) trench, or a trench used to form a number or letter mark in a Scribe line (Scribe line), which is a choice according to the actual process, and is not limited in this embodiment. In the present embodiment, the width of the trench 112 is 0.8 μm to 2.0 μm, for example, the width of the trench 112 may be 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, etc., the width of the via 111 may be 500nm to 1000nm, for example, the width of the via 111 may be 600nm, 700nm, 800nm, 900nm, 1000nm, etc.
Next, step S3 is performed, and referring to fig. 4, a conductive layer 120 is formed in the via hole 111, the bottom wall and the side wall of the trench 112. The conductive layer 120 in the via 111 is electrically connected to the interconnect 101 for forming a via structure, thereby forming an interconnect structure for electrically connecting the device structure, and the conductive layer 120 in the trench 112 is used for electrically connecting the interconnect structure 101 to the lower plate of the MIM capacitor. The conductive layer 120 is made of metal tungsten, and in the filling process of the metal tungsten, since the width of the trench 112 is greater than the width of the via 111, the via 111 is completely filled with the metal tungsten, but the sidewall portion of the trench 112 cannot be completely filled with the metal tungsten, so that a defect is formed on the sidewall of the trench 112, which may cause a tip discharge in a subsequent metal deposition process to form an arc discharge defect.
Next, step S4 is executed, and referring to fig. 5, a lower electrode 131 is formed on the conductive layer 120 and the interlayer dielectric layer 110. In this embodiment, the lower electrode 131 includes a first metal nitride layer, a metal layer, and a second metal nitride layer stacked in sequence, where the first metal nitride layer is titanium nitride or tantalum nitride, the first nitride layer has a thickness of 20nm to 50nm1, the metal layer is metal aluminum or metal copper, the metal layer has a thickness of 50nm to 200nm, the second metal nitride layer is titanium nitride or tantalum nitride, the second nitride layer has a thickness of 20nm to 50nm, and the lower electrode 131 is used to form a lower plate of an MIM capacitor.
Thereafter, step S5 is performed, and with continued reference to fig. 5, a filling layer 140 'is formed, wherein the filling layer 140' completely fills the trench 112 and covers the lower electrode 131. In this embodiment, the material of the filling layer 140 'may be silicon dioxide, and a Chemical Vapor Deposition (CVD) process is used to form the filling layer 140'. Of course, the filling layer 140' may also be other dielectric materials such as silicon nitride, silicon oxynitride, etc., which is not limited in the present invention.
Next, referring to fig. 6, the filling layer 140 'is planarized by using a chemical mechanical polishing process, the filling layer on the lower electrodes 131 is removed, and the filling layer 140' in the trenches 112 between the lower electrodes 131 is remained, so as to form the filling structure 140. Therefore, the filling structure 140 completely fills the region between the trench 112 and the lower electrode 131, so that a flat plane is formed between the lower electrode 131 and the filling structure 140, and the influence of the defect of the trench portion on the subsequent deposition is avoided.
Finally, step S6 is executed, referring to fig. 7, an inter-electrode dielectric layer 132 and an upper electrode 133 are sequentially formed on the lower electrode 131 and the filling structure 140 from bottom to top, the lower electrode 131, the inter-electrode dielectric layer 132 and the upper electrode 133 form an MIM capacitor 130, and the MIM capacitor 130 is electrically connected to the interconnect structure 101. In this embodiment, the inter-electrode dielectric layer 132 is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, the inter-electrode dielectric layer 132 is one or a combination of silicon nitride, silicon oxide, and silicon oxynitride, and the thickness of the inter-electrode dielectric layer 132 is 20nm to 100nm, for example, the thickness of the inter-electrode dielectric layer 132 is 30m, 50nm, 60nm, 80nm, and the like. The upper electrode 133 is formed by a Physical Vapor Deposition (PVD) process, the upper electrode 133 is made of aluminum or copper, and the thickness of the upper electrode 133 is 50nm to 200nm, for example, the thickness of the upper electrode 133 is 80nm, 120nm, 150nm, 160nm, 180nm, or the like. In the present invention, when the inter-electrode dielectric layer 132 and the upper electrode 133 are formed on the surfaces of the lower electrode 131 and the filling structure 140, the flat surface can prevent the tip discharge from occurring in the trench when the upper electrode 133 is formed, and prevent the arc discharge defect from being formed in the inter-electrode dielectric layer 132, thereby improving the performance of the device and increasing the yield.
In summary, in the method for improving the arc discharge defect of the MIM capacitor according to the present invention, the filling structure is formed on the lower electrode, and the filling structure completely fills the trench and the region between the lower electrodes, so that a flat plane is formed between the lower electrode and the filling structure. And then, forming an interelectrode dielectric layer and an upper electrode on the surfaces of the lower electrode and the filling structure, wherein when the upper electrode is formed, the flat surface can avoid the formation of point discharge in the MIM capacitor and prevent the formation of arc discharge defects in the interelectrode dielectric layer, thereby improving the performance of the device and improving the yield.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (17)
1. A method of ameliorating MIM capacitor arcing defects, comprising:
providing a semiconductor substrate, and forming an interlayer dielectric layer on the surface of the semiconductor substrate;
forming a groove exposing the semiconductor substrate in the interlayer dielectric layer;
forming a conductive layer on the bottom wall and the side wall of the groove;
forming a lower electrode on the conducting layer and the interlayer dielectric layer;
forming a filling structure between the lower electrodes in the groove, wherein the filling structure completely fills the area between the groove and the lower electrodes, so that a flat plane is formed between the lower electrodes and the filling structure; and
and sequentially forming an inter-electrode dielectric layer and an upper electrode on the lower electrode and the filling structure from bottom to top, wherein the lower electrode, the inter-electrode dielectric layer and the upper electrode form an MIM capacitor.
2. The method for ameliorating MIM capacitor arcing defects of claim 1 further comprising: and forming a through hole exposing the semiconductor substrate in the interlayer dielectric layer, wherein the width of the groove is greater than that of the through hole.
3. The method for mitigating MIM capacitor arcing defects according to claim 2 wherein the trench has a width of 0.8 μm to 2.0 μm and the via has a width of 500nm to 1000 nm.
4. The method for ameliorating MIM capacitor arcing defects according to claim 2 wherein the conductive layer also completely fills the via.
5. The method of ameliorating MIM capacitor arcing defects according to claim 2, wherein the semiconductor substrate comprises a multi-layered interconnect structure, the conductive layer being electrically connected to the multi-layered interconnect structure.
6. The method for ameliorating MIM capacitor arcing defects according to claim 5 wherein the material of the conductive layer is metallic tungsten.
7. The method of improving the arc discharge defect of the MIM capacitor according to claim 1 wherein the bottom electrode comprises a first metal nitride layer, a metal layer and a second metal nitride layer stacked in that order from bottom to top.
8. The method of ameliorating MIM capacitor arc discharge defects according to claim 7 wherein the first metal nitride layer is titanium nitride or tantalum nitride and the first metal nitride layer has a thickness of from 20nm to 50 nm.
9. The method for mitigating MIM capacitor arc discharge defects according to claim 7 wherein the metal layer is aluminum metal or copper metal and the metal layer has a thickness of from 50nm to 200 nm.
10. The method of ameliorating MIM capacitor arc discharge defects according to claim 7 wherein the second metal nitride layer is titanium nitride or tantalum nitride and the second metal nitride layer has a thickness of from 20nm to 50 nm.
11. The method for ameliorating MIM capacitor arcing defects according to claim 1 wherein forming the fill structure comprises:
forming a filling layer, wherein the filling layer fills the groove completely and covers the lower electrode;
and chemically and mechanically grinding the filling layer, removing the filling layer on the lower electrode to form the filling structure, and forming a flat surface between the filling structure and the lower electrode.
12. The method for mitigating MIM capacitor arc discharge defects according to claim 11 wherein the fill layer is formed using a chemical vapor deposition process.
13. The method for mitigating MIM capacitor arcing defects according to claim 11 wherein the material of the fill layer is silicon dioxide.
14. The method of ameliorating MIM capacitor arcing defects according to claim 1 wherein the inter-electrode dielectric layer is formed using a plasma enhanced chemical vapor deposition process.
15. The method for improving the arc discharge defect of the MIM capacitor according to claim 1 wherein the inter-electrode dielectric layer is one or a combination of silicon nitride, silicon oxide and silicon oxynitride, and the thickness of the inter-electrode dielectric layer is 20nm to 100 nm.
16. The method of ameliorating MIM capacitor arcing defects according to claim 1 wherein the upper electrode is formed using a physical vapor deposition process.
17. The method for mitigating MIM capacitor arc discharge defects according to claim 1 wherein the top electrode is aluminum metal or copper metal and the top electrode has a thickness of from 50nm to 200 nm.
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| CN108122894B true CN108122894B (en) | 2019-12-27 |
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| CN109065521A (en) * | 2018-08-17 | 2018-12-21 | 安徽信息工程学院 | Improve the method and capacitor of arc discharge defect in capacitor fabrication |
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| KR20060072223A (en) * | 2004-12-22 | 2006-06-28 | 동부일렉트로닉스 주식회사 | Method of fabricating mim(metal-insulator-metal) capacitor |
| KR20080018414A (en) * | 2006-08-24 | 2008-02-28 | 동부일렉트로닉스 주식회사 | Method of fabricating semiconductor devices |
| CN101364532A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor and manufacturing method thereof, semiconductor device and manufacturing method thereof |
| CN103187241A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for avoiding arc discharge defect in metal-insulator-metal (MIM) capacitor manufacturing process |
| CN205069629U (en) * | 2015-10-13 | 2016-03-02 | 格科微电子（上海）有限公司 | Metal level - insulating layer - metal level condenser |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7601604B2 (en) * | 2006-10-12 | 2009-10-13 | Atmel Corporation | Method for fabricating conducting plates for a high-Q MIM capacitor |
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|---|---|---|---|---|
| KR20060072223A (en) * | 2004-12-22 | 2006-06-28 | 동부일렉트로닉스 주식회사 | Method of fabricating mim(metal-insulator-metal) capacitor |
| KR20080018414A (en) * | 2006-08-24 | 2008-02-28 | 동부일렉트로닉스 주식회사 | Method of fabricating semiconductor devices |
| CN101364532A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor and manufacturing method thereof, semiconductor device and manufacturing method thereof |
| CN103187241A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for avoiding arc discharge defect in metal-insulator-metal (MIM) capacitor manufacturing process |
| CN205069629U (en) * | 2015-10-13 | 2016-03-02 | 格科微电子（上海）有限公司 | Metal level - insulating layer - metal level condenser |
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