CN108122589A - It is a kind of to eliminate the inconsistent method of the Nand bit error rates and solid state disk - Google Patents
It is a kind of to eliminate the inconsistent method of the Nand bit error rates and solid state disk Download PDFInfo
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- CN108122589A CN108122589A CN201711370815.9A CN201711370815A CN108122589A CN 108122589 A CN108122589 A CN 108122589A CN 201711370815 A CN201711370815 A CN 201711370815A CN 108122589 A CN108122589 A CN 108122589A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
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Abstract
The inconsistent method of the Nand bit error rates is eliminated the invention discloses a kind of, it is characterized in that increasing an experience difference table in solid state disk, the experience difference table has recorded the difference of preferred read voltage threshold values of the block under different erasable numbers and retention time and default threshold voltage；Solid state disk is read the normal data of threshold voltage using acquiescence and is read, when there is read error, experience difference table is searched according to the erasable number of current block and retention time, is found with the presence or absence of corresponding difference, and if so, directly adjusting the reading threshold voltage of the block using the difference；It if there is no then using the mode of reading again or calibration read mode by attempting different reading threshold voltages, finds optimal read voltage and reads data, and calculate the erasable number of the block and retention time corresponding difference voltage, and add the data in experience difference table.The phenomenon that 3D Nand difference Page bit error rate rates are inconsistent, while the reading threshold voltage of energy fast prediction optimization can be effectively eliminated.
Description
Technical field
It is more particularly to a kind of to eliminate the inconsistent method of the Nand bit error rates and consolidate the present invention relates to solid state disk control technology
State hard disk.
Background technology
The factors such as field of solid state storage, storage density and cost are just accelerating the application of 3D Nand Flash.3DNand is special
Internal structure and manufacturing process, cause the characteristic that it shows and traditional 2D Nand completely different.The mistake of this patent concern
Code check rate is one aspect.
Under same Block, the bit error rate rate (Error Bits) of different Page shows in certain 3D Nand is not
Identical, there are larger fluctuations.The inconsistent characteristic of this bit error rate rate can influence the reliability of data storage, while
Higher demand is proposed to firmware design.
The source of bit error rate rate is that there are non-optimal matched situations with Vth distributions for reading threshold voltage.It is distributed and fixes in Vth
In the case of, reading threshold voltage deviation optimal threshold voltage is more remote, and the feature showed is exactly that bit error rate rate is higher.Similarly,
In the case of fixed reading threshold voltage, Vth distributions generate displacement, and optimal threshold voltage caused by displacement is from fixed reading threshold value
Voltage is more remote, and bit error rate rate is higher.In the case where bit error rate rate is higher, the mode that adjusting reading threshold voltage can be used causes
It is current to read threshold voltage as close to optimal threshold voltage to reduce bit error rate rate.
Fig. 1 shows be a certain 3D Nand TLC Page Vth distribution schematic diagrams, in Fig. 2 between L4 and L5 distributions
Default read voltage Default Read Level can increase the bit error rate compared to optimal read voltage OptimizedRead Level
Rate.
The Page Vth of different zones are distributed there are displacement situation (that is, L0~L7 in Fig. 2 in 3D Nand Block
Vth be distributed compared with 0V overall offsets), when use it is same acquiescence read threshold voltage, these Page Vth distribution it is optimal
The difference that threshold voltage and acquiescence read threshold voltage is also different, and the bit error rate rate of the different zones Page showed is inconsistent.
And 2D Nand its internal structure determines that the Vth distributions of different Page are similar, so the Page bit error rate rates of same Block
Than more consistent.
The content of the invention
It is inconsistent the present invention seeks to how eliminate or reduce the Nand bit error rates for disadvantages described above.
The present invention proposes a kind of inconsistent method of elimination Nand bit error rates in order to solve problem above, it is characterised in that
Increase an experience difference table in solid state disk, the experience difference table has recorded block in different erasable numbers and retention time
Under preferred read voltage threshold values and default threshold voltage difference；Solid state disk reads the normal data of threshold voltage using acquiescence
Read, when there is read error, experience difference table searched according to the erasable number of current block and retention time, find with the presence or absence of pair
The difference answered, and if so, directly adjusting the reading threshold voltage of the block using the difference；If there is no then square using reading again
Formula or calibration read mode find optimal read voltage and read data, and calculate the block by attempting different reading threshold voltages
Erasable number and retention time corresponding difference voltage, and add the data in experience difference table.
Described eliminates the inconsistent method of the Nand bit error rates, it is characterised in that the experience difference table passes through to same batch
Nand is sampled, and is extracted multiple pieces while made burn-in test, obtains the erasable number of multiple pieces of differences and under the retention time
Difference establishes complete experience difference table, using the experience difference table as the propulsion experience difference table of the batch solid state disk.
Described eliminates the inconsistent method of the Nand bit error rates, it is characterised in that the experience difference table passes through hard in solid-state
At least one block is chosen in disk as test block, carries out different erasable tests to the data block in the solid state hard disk system free time
And the difference under different erasable numbers is obtained, and the data for testing acquisition are added in experience difference table.
A kind of solid state disk, it is characterised in that one experience difference table of middle increase, the experience difference table have recorded block and exist
The difference of preferred read voltage threshold values and default threshold voltage under different erasable numbers and retention time；Solid state disk is using silent
Recognize and read the normal data reading of threshold voltage, when there is read error, warp is searched according to the erasable number of current block and retention time
Difference table is tested, is found with the presence or absence of corresponding difference, and if so, directly adjusting the reading threshold voltage of the block using the difference；
If there is no then using the mode of reading again or calibration read mode by attempting different reading threshold voltages, optimal read voltage is found
Data are read, and calculate the erasable number of the block and retention time corresponding difference voltage, and it is poor to add the data to experience
It is worth in table.
The solid state disk, it is characterised in that the experience difference table is taken out by being sampled to same batch Nand
It takes multiple pieces while makees burn-in test, obtain the erasable number of multiple pieces of differences and the difference under the retention time, establish complete warp
Difference table is tested, using the experience difference table as the propulsion experience difference table of the batch solid state disk.
The solid state disk, it is characterised in that the experience difference table in solid state disk by choosing at least one block
As test block, different erasable tests is carried out to the data block in the solid state hard disk system free time and obtains different erasable numbers
Under difference, and by test obtain data be added in experience difference table.
The beneficial effects of the invention are as follows：The phenomenon that 3D Nand difference Page bit error rate rates are inconsistent can be effectively eliminated, simultaneously
Can fast prediction optimization readings threshold voltage to reach influence of elimination PE Cycle and the Retention factor to bit error rate rate.
Description of the drawings
Fig. 1 shows be a certain 3D Nand TLC Page Vth distribution schematic diagrams；
Fig. 2 is optimal read voltage and the difference schematic diagram of acquiescence read voltage threshold values；
Fig. 3 be by repeatedly it is erasable after the optimal changed schematic diagram of read voltage；
Fig. 4 is to eliminate the inconsistent method flow diagram of bit error rate rate.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment belongs to the scope of protection of the invention.
The Page Vth of different zones are distributed there are displacement situation (that is, L0~L7 in Fig. 2 in 3D Nand Block
Vth be distributed compared with 0V overall offsets), when use it is same acquiescence read threshold voltage, these Page Vth distribution it is optimal
The difference that threshold voltage and acquiescence read threshold voltage is also different, and the bit error rate rate of the different zones Page showed is inconsistent.
And 2D Nand its internal structure determines that the Vth distributions of different Page are similar, so the Page bit error rate rates of same Block
Than more consistent.
It is distributed on Vth, analyzes to have obtained following two features by lot of experimental data：
1st, the Vth regularities of distribution of the identical Page of same Nand, different Block are similar, i.e., the bit error rate of identical Page
Rate is similar.
2nd, as erasable number PE Cycle and retention time Retention consistent, the difference of same Nand
The Vth changes in distribution rules of Block are similar, and equidistant displacement (distribution shifts) in the same direction and the modal variations of same Vth (divide
Cloth broadens short), as shown in Fig. 3 and Fig. 2.
3rd, assume that the optimal threshold voltage of Page N and the Page M of Block A and acquiescence read the difference difference of threshold voltage
For Δ Vn、ΔVm.After certain PE Cycle and Retention, the Vth distributions of Page N, Page M generate variation,
The difference that optimal threshold voltage reads threshold voltage with acquiescence is respectively Δ Vn’、ΔVm’。
Based on the feature of front two, can deduce：
1st, the optimal threshold voltage of Page N and the Page M of all Block of same Nand reads threshold voltage with acquiescence
Difference is approximately Δ VnWith Δ Vm；
2nd, Page N and the Page M's of all Blocks consistent with Block A PE Cycle and Retention is optimal
The difference that threshold voltage reads threshold voltage with acquiescence is approximately Δ Vn’、ΔVm’；
3、ΔVn’-ΔVn≈ΔVm’-ΔVm；
Δ V based on these characteristics, in advance Page N and the Page M of acquisition 3D NandnWith Δ VmAfterwards, in PE Cycle
After changing with Retention conditions, it is only necessary to obtain Δ Vn', with regard to that can derive Δ Vm’。
It eliminates there are two types of the inconsistent approach of bit error rate rate：It reads Read Retry again and Calibration is read in calibration
Read, the latter's precision are higher than the former, and two methods all rely on the support of Nand Flash, change inside Nand Flash and read threshold value
Voltage so that read threshold voltage and be intended to optimal threshold voltage.But both approaches take it is more, every time using both approaches
Going reduction bit error rate rate, there are undesirable parts.
This programme gathers the threshold voltage shift amount of a certain kind 3D Nand, optimal threshold by Calibration Read
Voltage reads the offset of threshold voltage with acquiescence, this threshold voltage shift amount is as a reference value, as PE Cycle and Retention
Change drawn Vth distribution variation, can rely on single Calibration Read obtain current threshold voltage offset and
Threshold voltage is read in the optimization of threshold voltage shift amount information fast prediction other Block, other Page for gathering in advance.Using this
The quick elimination bit error rate rate of technical solution is inconsistent.
Fig. 4 is to eliminate the inconsistent method flow diagram of bit error rate rate.Datum quantity is first obtained, then passes through current offset and base
The other offsets of quasi- amount prediction.
Based on conclusion above and Fig. 4 flows, have to draw a conclusion：
1. rely on difference Page in some Block of the Calibration Read acquisition 3D Nand of Nand Flash
Optimal threshold voltage with acquiescence read threshold voltage difference, be denoted as Δ ViI ∈ [0, Max Page Index], other Block
There is also such Δ Vi.The bit error rate rate of all Page should be at very low level in Block at this time；
After the variation of 2.PE Cycle and Retention condition, bit error rate rate rises, to some Page N of arbitrary Block
Calibration Read are re-started, the optimal threshold voltage of the Page under present case is obtained and reads threshold voltage with acquiescence
Difference DELTA Vn', based on inference can all Page of fast prediction optimal threshold voltage and acquiescence read threshold voltage difference be
ΔVi+ΔVn–ΔVn', i ∈ [0, Max Page Index]；
The application flow of Fig. 4 can not only eliminate the inconsistent of different Page bit error rates rates, moreover it is possible to it is quick eliminate PECycle and
The influence that Retention conditions are brought to bit error rate rate.
The above disclosed interest field for being only an embodiment of the present invention, sheet cannot being limited with this certainly,
One of ordinary skill in the art will appreciate that realize all or part of flow of above-described embodiment, and according to the claims in the present invention institute
The equivalent variations of work still fall within the scope that the present invention is covered.
Claims (6)
1. a kind of eliminate the inconsistent method of the Nand bit error rates, it is characterised in that increase an experience difference table in solid state disk,
The experience difference table has recorded preferred read voltage threshold values and default threshold of the block under different erasable numbers and retention time
The difference of voltage；Solid state disk is read the normal data of threshold voltage using acquiescence and is read, when there is read error, according to current block
Erasable number and retention time search experience difference table, find with the presence or absence of corresponding difference, should and if so, directly using
Difference adjusts the reading threshold voltage of the block；If there is no then using the mode of reading again or calibration read mode by attempting different readings
Threshold voltage finds optimal read voltage and reads data, and calculates the erasable number of the block and retention time corresponding difference electricity
Pressure, and add the data in experience difference table.
2. according to claim 1 eliminate the inconsistent method of the Nand bit error rates, it is characterised in that the experience difference table
By being sampled to same batch Nand, and extract multiple pieces while make burn-in test, obtain multiple pieces of erasable numbers of difference and
Difference under retention time establishes complete experience difference table, using the experience difference table as the propulsion of the batch solid state disk
Experience difference table.
3. according to claim 1 eliminate the inconsistent method of the Nand bit error rates, it is characterised in that the experience difference table
It is used as test block by choosing at least one block in solid state disk, the data block is carried out not in the solid state hard disk system free time
Erasable test together simultaneously obtains the difference under different erasable numbers, and the data for testing acquisition are added in experience difference table.
4. a kind of solid state disk, it is characterised in that one experience difference table of middle increase, the experience difference table have recorded block not
The difference of preferred read voltage threshold values and default threshold voltage under same erasable number and retention time；Solid state disk is using acquiescence
It reads the normal data of threshold voltage to read, when there is read error, experience is searched according to the erasable number of current block and retention time
Difference table is found with the presence or absence of corresponding difference, and if so, directly adjusting the reading threshold voltage of the block using the difference；Such as
Fruit finds optimal read voltage and reads there is no then using the mode of reading again or calibration read mode by attempting different reading threshold voltages
Access evidence, and the erasable number of the block and retention time corresponding difference voltage are calculated, and add the data to experience difference
In table.
5. solid state disk according to claim 4, it is characterised in that the experience difference table by same batch Nand into
Line sampling, and extract multiple pieces while make burn-in test, the erasable number of multiple pieces of differences and the difference under the retention time are obtained, is built
Complete experience difference table is found, using the experience difference table as the propulsion experience difference table of the batch solid state disk.
6. solid state disk according to claim 4, it is characterised in that the experience difference table in solid state disk by selecting
At least one block is taken to carry out different erasable tests as test block to the data block in the solid state hard disk system free time and obtain
Difference under different erasable numbers, and the data for testing acquisition are added in experience difference table.
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Cited By (10)
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| CN109240615A (en) * | 2018-08-30 | 2019-01-18 | 浪潮电子信息产业股份有限公司 | Data reading method, device and equipment of solid state disk |
| CN109271293A (en) * | 2018-09-17 | 2019-01-25 | 浪潮电子信息产业股份有限公司 | Hard disk data reading method and device and related equipment |
| CN109460191A (en) * | 2018-11-15 | 2019-03-12 | 苏州韦科韬信息技术有限公司 | A kind of method of dynamic quantization solid state hard disk data reliability |
| CN109859792A (en) * | 2018-12-25 | 2019-06-07 | 北京大学 | A kind of threshold voltage distribution forecasting method and device |
| CN109871594A (en) * | 2019-01-28 | 2019-06-11 | 山东华芯半导体有限公司 | A kind of NAND Flash characteristic model method for building up |
| CN110347335A (en) * | 2019-07-30 | 2019-10-18 | 河南文正电子数据处理有限公司 | A kind of solid state hard disk date storage method, device |
| CN110534152A (en) * | 2019-08-08 | 2019-12-03 | 杭州电子科技大学 | A method of preventing flash data read error |
| CN110689914A (en) * | 2019-09-06 | 2020-01-14 | 苏州浪潮智能科技有限公司 | Solid state disk reading error correction method, device, equipment and storage medium |
| CN111124278A (en) * | 2019-11-21 | 2020-05-08 | 苏州浪潮智能科技有限公司 | Method, device and medium for improving reading performance of solid state disk |
| CN118069075A (en) * | 2024-04-22 | 2024-05-24 | 江苏华存电子科技有限公司 | Background fine data retention scanning method applied to enterprise-level solid state disk |
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| CN109240615A (en) * | 2018-08-30 | 2019-01-18 | 浪潮电子信息产业股份有限公司 | Data reading method, device and equipment of solid state disk |
| CN109240615B (en) * | 2018-08-30 | 2021-10-15 | 浪潮电子信息产业股份有限公司 | Data reading method, device and equipment of solid state disk |
| CN109271293A (en) * | 2018-09-17 | 2019-01-25 | 浪潮电子信息产业股份有限公司 | Hard disk data reading method and device and related equipment |
| CN109460191A (en) * | 2018-11-15 | 2019-03-12 | 苏州韦科韬信息技术有限公司 | A kind of method of dynamic quantization solid state hard disk data reliability |
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| CN110347335A (en) * | 2019-07-30 | 2019-10-18 | 河南文正电子数据处理有限公司 | A kind of solid state hard disk date storage method, device |
| CN110347335B (en) * | 2019-07-30 | 2022-12-13 | 河南文正电子数据处理有限公司 | Solid state disk data storage method and device |
| CN110534152A (en) * | 2019-08-08 | 2019-12-03 | 杭州电子科技大学 | A method of preventing flash data read error |
| CN110689914A (en) * | 2019-09-06 | 2020-01-14 | 苏州浪潮智能科技有限公司 | Solid state disk reading error correction method, device, equipment and storage medium |
| CN111124278A (en) * | 2019-11-21 | 2020-05-08 | 苏州浪潮智能科技有限公司 | Method, device and medium for improving reading performance of solid state disk |
| CN118069075A (en) * | 2024-04-22 | 2024-05-24 | 江苏华存电子科技有限公司 | Background fine data retention scanning method applied to enterprise-level solid state disk |
| CN118069075B (en) * | 2024-04-22 | 2024-06-18 | 江苏华存电子科技有限公司 | Background fine data retention scanning method applied to enterprise-level solid state disk |
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Application publication date: 20180605 |