CN114325196B - Signal testing system - Google Patents
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Abstract
The application provides a signal testing system which comprises a PI module, an ALGO module and an EOM module, wherein the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and clock phase control signals sent by the ALGO module, outputting a target clock signal, the EOM module is used for receiving signals to be tested, the target clock signal and threshold voltage control signals sent by the ALGO module, outputting a statistical result of sampling the signals to be tested, the ALGO module is used for receiving the statistical result, determining the eye width value and the eye height value of an eye pattern of the signals to be tested, sampling and counting the signals to be tested by the EOM module by utilizing the target clock signals input by the PI module and the threshold voltage control signals sent by the ALGO module through the phase interpolation, and the ALGO module determines the eye width value and the eye height value of the eye pattern of the signals to be tested by utilizing the obtained statistical result, so that the eye height and the eye width of high-speed signals can be automatically stored and read, and the power consumption of the signal testing system is low.
Description
Technical Field
The invention relates to the field of signal testing, in particular to a signal testing system.
Background
With the progress of technology, there is an increasing demand for high-speed transmission of signals. However, as the transmission rate of the signal increases, the attenuation of the signal during transmission increases accordingly. Equalization techniques are therefore used in systems for high-speed transmission of signals to compensate for the loss of the high-frequency channel. And then the equalized signal can be tested to obtain the parameters of the current signal, and the signal can be optimized by continuously utilizing the equalization technology.
When a signal is specifically tested, the eye diagram can reflect the quality of the signal, and how to acquire the relevant information of the eye diagram of the signal is a problem to be solved.
Disclosure of Invention
Accordingly, the present application is directed to a signal testing system capable of automatically acquiring information about an eye pattern of a signal, such as eye height and eye width.
The embodiment of the application provides a signal testing system, which comprises: the system comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module;
the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and clock phase control signals sent by the ALGO module and outputting target clock signals;
The EOM module is used for receiving a signal to be detected, the target clock signal and a threshold voltage control signal sent by the ALGO module and outputting a statistical result of sampling the signal to be detected;
The ALGO module is used for receiving the statistical result and determining the eye width value and the eye height value of the eye pattern of the signal to be detected.
Optionally, the EOM module includes a threshold voltage setting module and a signal processing module;
The threshold voltage setting module is used for traversing a threshold voltage value according to the threshold voltage control signal, and the threshold voltage value is traversed and comprises the eye height value of the eye diagram;
The signal processing module is used for sampling the signal to be detected according to the rising edge and the falling edge of the target clock signal when traversing the threshold voltage value according to the threshold voltage control signal, so as to obtain and store a statistical result.
Optionally, the statistical result includes a first statistical result and a second statistical result;
the signal processing module is specifically configured to sample the signal to be tested according to a rising edge of the target clock signal when traversing the threshold voltage value according to the threshold voltage control signal, obtain and store a first statistical result, and sample the signal to be tested according to a falling edge of the target clock signal, obtain and store a second statistical result;
the ALGO module is used for receiving the first statistical result and the second statistical result and determining the eye width value and the eye height value of the eye pattern of the signal to be detected according to the sum of the first statistical result and the second statistical result.
Optionally, the EOM module is further configured to send a statistics end flag signal to the ALGO module, so as to send a statistics result of the signal to be measured to the ALGO module.
Optionally, the ALGO module is further configured to send a reset signal to the EOM module after receiving the statistics end flag signal sent by the EOM module, so that the EOM module resets according to the reset signal.
Optionally, the ALGO module is configured to keep the threshold voltage control signal at a voltage initial value, traverse the clock phase control signal, and obtain a plurality of statistical results of the signal to be measured.
Optionally, the plurality of statistical results include a first critical result and a second critical result, and a distance between clock phase values corresponding to adjacent first critical result and second critical result is an eye width value of an eye pattern of the signal to be measured, the value of the first critical result is from 0 to 0, and the value of the second critical result is from 0 to 0.
Optionally, the ALGO module is configured to keep the clock phase control signal as a phase initial value, traverse the threshold voltage control signal, and obtain a plurality of statistical results of the signal to be measured.
Optionally, the phase initial value is an intermediate value between clock phase values corresponding to the first critical result and the second critical result, the plurality of statistical results include a third critical result, a threshold voltage value corresponding to the third critical result is an eye height value of the signal to be measured, and a value of the third critical result is 0 to non-0.
Optionally, the initial clock signal includes a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, where the frequency of the first clock signal is one half of the frequency of the signal to be measured, the second clock signal is an inverted signal of the first clock signal, the third clock signal is the same frequency as the first clock signal, and the phase difference is 90 °, and the fourth clock signal is an inverted signal of the third clock signal.
The signal testing system provided by the embodiment of the application comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module, wherein the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and clock phase control signals sent by the ALGO module, outputting a target clock signal, the EOM module is used for receiving a signal to be tested, the target clock signal and threshold voltage control signals sent by the ALGO module, outputting a statistical result of sampling the signal to be tested, and the ALGO module is used for receiving the statistical result and determining the eye width value and the eye height value of an eye pattern of the signal to be tested, namely, sampling statistics is carried out on the signal to be tested by the EOM module by utilizing the target clock signals input by the phase interpolation PI module and the threshold voltage control signals sent by the ALGO module, then the ALGO module utilizes the obtained statistical result to determine the eye width value and the eye height value of the signal to be tested, so that the automatic storage and reading of the eye width of the high-speed signal are realized, the design flow of signal testing is simplified, the design and the test cost of the signal testing is reduced, and the power consumption of the signal testing system is lower, and the requirements are also lower.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are some embodiments of the application and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a block diagram of a signal testing system according to an embodiment of the present application;
FIG. 2 is a block diagram of another signal testing system according to an embodiment of the present application;
FIG. 3 is a schematic waveform diagram of an initial clock signal according to an embodiment of the present application;
Fig. 4 shows an eye diagram according to an embodiment of the present application.
Detailed Description
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
In the following detailed description of the embodiments of the present application, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration only, and in which is shown by way of illustration only, and in which the scope of the application is not limited for ease of illustration. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
With the progress of technology, there is an increasing demand for high-speed transmission of signals. However, as the transmission rate of the signal increases, the attenuation of the signal during transmission increases accordingly. Equalization techniques are therefore used in systems for high-speed transmission of signals to compensate for the loss of the high-frequency channel. And then the equalized signal can be tested to obtain the parameters of the current signal, and the signal can be optimized by continuously utilizing the equalization technology.
When a signal is specifically tested, the eye diagram can reflect the quality of the signal, the eye diagram (EYE DIAGRAM) is a graph displayed after a series of code elements of the signal are accumulated on an oscilloscope according to a certain rule, the eye diagram is commonly used for analyzing the signal integrity of a high-speed interconnection system, the signal integrity refers to the quality of the signal on a transmission path, and the eye diagram is a standard for measuring the quality of the signal.
One of the more important information that an Eye diagram has is Eye height (EYE HEIGHT), which refers to the distance on the vertical axis of the blank area on the Eye diagram, and Eye Width (Eye Width), which can reflect the noise margin of a signal on a transmission path when there is a sufficient amount of signal data superimposed on the Eye diagram. The eye width refers to the distance of a blank area on an eye diagram on the horizontal axis, and when signal data superimposed on the eye diagram is sufficiently large, the eye width can reflect the settling time of a signal on a transmission path.
The current system for acquiring the related information of the eye pattern has higher implementation difficulty and higher cost, the clock signal used for sampling is the same as the frequency of the signal to be detected, the sampling difficulty is higher, and the system power consumption is higher.
How to collect the related information of the eye pattern of the high-speed signal with high efficiency and low cost is a problem to be solved.
Based on the above, the signal testing system provided by the embodiment of the application comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module, wherein the PI module is used for receiving a plurality of initial clock signals which are orthogonal to each other and clock phase control signals sent by the ALGO module, outputting a target clock signal, the EOM module is used for receiving a signal to be tested, the target clock signal and threshold voltage control signals sent by the ALGO module, outputting a statistical result of sampling the signal to be tested, the ALGO module is used for receiving the statistical result, determining the eye width value and the eye height value of the eye pattern of the signal to be tested, that is, the eye pattern of the signal to be tested is sampled and counted by the EOM module by utilizing the target clock signals input by the phase interpolation PI module and the threshold voltage control signals sent by the ALGO module, and then the ALGO module utilizes the obtained statistical result to determine the eye width value and the eye height value of the signal to be tested, so that the eye height and the eye pattern of the high-speed signal are automatically stored and read, the design flow of the signal test is simplified, the design and the test cost of the signal test is lowered, and the difficulty of implementing the signal testing system is lower.
For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a schematic structural diagram of a signal testing system according to an embodiment of the present application is shown. The signal testing system in the embodiment of the application can be applied to testing the signals transmitted at high speed and automatically acquiring the related information of the eye pattern of the signals transmitted at high speed. The signal testing system may be integrated in a chip.
The signal testing system 100 provided in the embodiment of the application includes: a phase interpolation (Phase Interpolation, PI) module 110, a logic control Algorithm (ALGO) module 120, and a data sampling and processing module 130, namely Eye opening monitoring (eye_ Opening Moniter, EOM) for implementing an Eye pattern of a signal to be measured, abbreviated as EOM module 130.
In the embodiment of the present application, the PI module 110 is configured to receive a plurality of initial clock signals in quadrature and the clock phase control signal pi_phsel_code <5:0> sent by the ALGO module 120, and output the target clock signal pi_clk to the EOM module 130.
The plurality of initial clock signals include a first clock signal CLKI, a second clock signal CLKIB, a third clock signal CLKQ and a fourth clock signal CLKQB, the frequency of the first clock signal CLKI is half of the frequency of the signal to be measured Vin, the second clock signal CLKIB is an inverted signal of the first clock signal CLKI, the frequency of the third clock signal CLKQ is identical to the frequency of the first clock signal CLKI, the phase difference is 90 °, and the fourth clock signal CLKQB is an inverted signal of the third clock signal CLKQ, which is shown in fig. 3.
The four initial clock signals CLKI, CLKIB, CLKQ and CLKQB have a strict phase relationship and must be in quadrature, so that the target clock signal pi_clk generated by the PI module 110 is uniformly distributed over the clock period after traversing one cycle of the clock phase control signal pi_phsel_code <5:0>, so that the complete eye diagram information can be obtained.
That is, the PI module 110 receives four phase initial clock signals and outputs a target clock signal pi_clk having a phase between the four initial clock signals according to a clock phase control signal pi_phsel_code <5:0> of a 6bit (bit) code value provided by the ALGO module 120. After the ALGO module 120 traverses the clock phase control signal pi_phsel_code <5:0> of the 6bit code value for controlling the phase of the target clock signal pi_clk, the phase of the target clock signal pi_clk output by the PI module 110 is exactly and uniformly distributed for two clock cycles of the high-speed signal Vin, that is, the information of the horizontal axis of the eye diagram in two Unit Intervals (UIs) is covered, as shown in fig. 4, which is an eye diagram provided in the embodiment of the present application.
In the embodiment of the present application, the EOM module 130 is configured to receive the signal Vin to be detected, the target clock signal pi_clk, and the threshold voltage control signal eom_vref_code <5:0> sent by the ALGO module 120, and output a statistical result of sampling the signal Vin to be detected.
The EOM module 130 includes a threshold voltage setting module 131 and a signal processing module 132, referring to fig. 2, the threshold voltage setting module 131 is configured to traverse a threshold voltage value according to a threshold voltage control signal eom_vref_code <5:0>, and the threshold voltage value traversed includes eye height values of an eye pattern. That is, the threshold voltage control signal eom_vref_code <5:0> of the 6bit code value provided by the ALGO module 120 may control the threshold voltage setting module 131 to set the threshold voltage value.
As an example, when the code value of the threshold voltage control signal eom_vref_code <5:0> is 00, which indicates that the threshold voltage is v1+/V1-shown in fig. 4, that is, the common mode voltage corresponding to the high-speed signal Vin, when the code value of the threshold voltage control signal eom_vref_code <5:0> is correspondingly increased, the threshold voltage becomes v2+/v2-, v3+/V3-, so that the threshold voltage control signal eom_vref_code <5:0> controlling the threshold voltage 6bit code value is traversed once, the threshold voltage is just uniformly distributed to swing of the high-speed signal Vin, that is, the information covering the direction of the vertical axis of the eye diagram is covered, and the threshold voltage value is traversed to include the eye height value of the eye diagram.
The signal processing module 132 is configured to sample the signal Vin to be detected according to the rising edge and the falling edge of the target clock signal pi_clk when traversing the threshold voltage value according to the threshold voltage control signal eom_vref_code <5:0>, and obtain and store the statistical result.
The target clock signal pi_clk provides the EOM module 130 with sampling clocks of different phases, which have a frequency half that of the high-speed signal Vin, i.e. the rising edge and the falling edge of the target clock signal pi_clk are used for sampling simultaneously, so that the sampling speed requirement on the EOM module 130 is relatively low, and the power consumption of the whole signal testing system is reduced.
In practical applications, the EOM module 130 is mainly configured to count the number of signal edges passing between the corresponding positive and negative threshold voltages for each phase clock in a period of time, so as to obtain a statistical result.
The statistical result includes a first statistical result eom_value_p <5:0> and a second statistical result eom_value_n <5:0>, and the signal processing module 132 is specifically configured to sample the signal Vin to be measured according to a rising edge of the target clock signal pi_clk when traversing the threshold voltage according to the threshold voltage control signal eom_vref_code <5:0>, obtain and store the first statistical result eom_value_p <5:0>, and sample the signal Vin to be measured according to a falling edge of the target clock signal pi_clk, obtain and store the second statistical result eom_value_n <5:0>.
In practical applications, the EOM module 130 is further configured to send a statistics end flag signal eom_done to the ALGO module 120, so as to send statistics results of the signal Vin to be measured to the ALGO module 120, specifically, send a first statistics result eom_value_p <5:0> and a second statistics result eom_value_n <5:0> of the signal Vin to be measured to the ALGO module 120.
After the level of the statistics end flag signal eom_done is changed from low to high, the representative EOM module 130 obtains the statistics result, and the statistics of a certain clock phase or a certain voltage threshold of the signal Vin to be measured is ended.
In an embodiment of the present application, the ALGO module 120 is configured to receive the statistics and determine the eye width value and the eye height value of the eye pattern of the signal Vin to be measured.
Specifically, the ALGO module 120 outputs clock phase control signals pi_phsel_code <5:0> to the PI module 110, controls the phase pi_clk of the target clock signal output by the PI module 110, simultaneously outputs threshold voltage control signals eom_vref_code <5:0> to the EOM module 130, controls the threshold voltage set by the EOM module 130, receives the first statistical result eom_value_p <5:0> and the second statistical result eom_value_n <5:0> transmitted by the EOM module 130, and determines the eye width value and the eye height value of the signal to be tested Vin according to the sum of the first statistical result eom_value_p <5:0> and the second statistical result eom_value_n <5:0>, and simultaneously receives the statistical end flag signal eom_done transmitted by the EOM module 130, and transmits a reset signal eom_t_n to the EOM module 130 so as to reset the EOM module 130 according to the rsm reset signal eom_t_n.
That is, the ALGO module 120 sends the reset signal eom_rst_n to the EOM module 130, resets the EOM module 130 before the EOM module 130 starts working and after the statistics end flag signal eom_done changes from low to high, and ensures that each statistics result of the EOM module 130 is counted from zero.
In the embodiment of the present application, when the PI module 110, the eom module 130, and the ALGO module 120 are specifically utilized to test the high-speed signal Vin, the following steps may be included: initializing a system, traversing a phase code value, determining eye width, traversing a threshold voltage code value, and determining eye height.
Prior to testing, the system may be initialized, i.e., ALGO module 120 pulls the reset signal eom_rst_n down to reset EOM module 130 and sets the code value of the threshold voltage control signal eom_vref_code <5:0> to 00 and the code value of the clock phase control signal pi_phsel_code <5:0> to 00.
The phase code values are then traversed to determine the eye width. After the PI module 110 and the EOM module 130 stabilize, the threshold voltage control signal eom_vref_code <5:0> is kept as the voltage initial value 00, and the code value of the clock phase control signal pi_phsel_code <5:0> is traversed to obtain a plurality of statistical results of the signal Vin to be measured.
Specifically, the reset signal eom_rst_n is released, at which time EOM module 130 operates normally, and ALGO module 120 starts traversing the code value of clock phase control signal pi_phsel_code <5:0> from 00 to 3F.
The traversing flow is as follows: firstly, the threshold voltage control signal eom_vref_code <5:0> is set to be a voltage initial value 00, and the voltage initial value 00 is kept unchanged, the threshold voltage corresponding to the voltage initial value is set to be v1+/v1-, namely, the voltage initial value transversely passes through the threshold voltage in the middle of the eye, as shown in fig. 4, the PI module 110 sends a statistical end mark signal eom_done under the initial phase of the code value 00 of the clock phase control signal pi_phsel_code <5:0>, a corresponding target clock signal pi_clk is output, the EOM module 130 utilizes the target clock signal pi_clk to sample and process the high-speed signal Vin, the sampling frequency is half of the frequency of the signal to be measured, and the rising edge sampling result of the target clock signal pi_clk is obtained, namely, the first statistical result eom_value p <5:0> and the falling edge sampling result are obtained, namely, the second statistical result eom_value n <5:0>, at this moment, the EOM module 130 sends a statistical end mark signal eom_done, after the first statistical end mark signal eom_glue_2:0 > is locked to the value of the clock phase control signal has been locked, the two statistical end mark signals having been controlled by the first clock signal having been found, the value of the first statistical end mark signal having been locked by the first clock signal pi_ph_ph_sel_0, the second statistical result has been locked by the first statistical result 5:0, the value has been obtained by the second statistical result 2:0, and the second statistical result having been obtained by the first statistical result value <5:0> after the value has been locked by the first statistical value, and the value 2 m_value has been locked by the first value 0:0, and the value is continuously locked by the first value, and the value 1 value is continuously by the first value 1 value, and the value is kept by the value 0 value is 0 value 5 is 0 5. The process of traversing the phase ends.
After obtaining a plurality of statistics results corresponding to the code values of the plurality of clock phase control signals pi_phsel_code <5:0>, the plurality of statistics results comprise a first critical result and a second critical result, the distance between clock phase values corresponding to the adjacent first critical result and second critical result is the eye width value of the eye pattern of the signal Vin to be measured, the value of the first critical result is from 0 to 0, and the value of the second critical result is from 0 to 0.
When determining the eye width of the eye diagram of the signal Vin to be measured, first determining a first critical result from a plurality of statistical results, wherein the value of the first critical result is from non-0 to 0, the non-0 indicates that a signal edge at the phase passes through positive and negative threshold voltages, the 0 indicates that no signal edge at the phase passes through positive and negative threshold voltages, then determining a second critical result, the value of the second critical result is from 0 to non-0, determining the code value of the clock phase control signal pi_phsel_code <5:0> corresponding to the adjacent first critical result and the second critical result respectively, at this time, the distance between the code values of the two adjacent clock phase control signals pi_phsel_code <5:0> is the blank space appearing on the horizontal axis in the eye diagram, and the jitter appears on each critical result is caused by the limitation of the signal testing system precision, which is shown in fig. 4, namely the signal is shifted relative to the ideal position at a certain specific moment, thus resulting in calculation to obtain a plurality of blank spaces, but not the actual eye width value, and thus the maximum eye width of the eye diagram is automatically found, namely the maximum blank space is the blank space, namely the maximum eye width is determined by the ALGO.
After traversing the phase code values to determine the eye width of the eye pattern, the threshold voltage code values may also be traversed to determine the eye height. Maintaining the clock phase control signal pi_phsel_code <5:0> as the phase initial value, traversing the code value of the threshold voltage control signal eom_vref_code <5:0>, and obtaining a plurality of statistical results of the signal Vin to be detected.
Specifically, the EOM module 130 is reset first, and the phase initial value is set to be an intermediate value between clock phase values corresponding to the first critical result and the second critical result, that is, the code value of the clock phase control signal pi_phsel_code <5:0> corresponding to the intermediate point of the two critical results of the eye width is used as the phase initial value of the PI module 110, then the threshold voltage control signal eom_vref_code <5:0> is traversed from the code value 00, and the code value of the clock phase control signal pi_phsel_code <5:0> is kept unchanged as the initial phase value in the traversal process, so as to obtain a plurality of statistical results.
The traversing flow is as follows: firstly, the code value of the clock phase control signal pi_phsel_code <5:0> is set as the phase initial value, and the phase initial value is kept unchanged, the PI module 110 outputs a corresponding target clock signal pi_clk when the code value of the clock phase control signal pi_phsel_code <5:0> is the phase initial value, the EOM module 130 utilizes the target clock signal pi_clk to sample and process the high-speed to-be-detected signal Vin, the sampling frequency is half of the frequency of the to-be-detected signal Vin, the rising edge sampling result of the target clock signal pi_clk is obtained, namely, the first statistical result eom_value_p <5:0> and the falling edge sampling result are obtained, namely, the second statistical result eom_value_n <5:0>, when the second statistical result eom_n <5:0>, after the rising edge of the statistical end mark signal eom_done arrives, the first statistical result eom_value p <5:0> and the second statistical result value m_n <5:0> are locked, the threshold value is not locked, the threshold value is continuously changed from the first statistical result eom_value and the second statistical result eom_value m_n <5:0>, the threshold value is locked, the threshold value is not locked by the threshold value after the first statistical result value is changed by the EOM module 130, the threshold value is changed, the threshold value is continuously locked by the threshold value after the first statistical result value is changed, and the threshold value is changed by the threshold value, the threshold value is controlled by the second statistical result signal, and the EOM module 130, the threshold value is reset, and the threshold value is controlled.
And determining a third critical result in the plurality of statistical results, wherein the value of the third critical result is 0 to non-0, and the threshold voltage value corresponding to the code value of the threshold voltage control signal eom_vref_code <5:0> corresponding to the third critical result is the eye height value of the signal to be detected.
In practical applications, the code value of the threshold voltage control signal eom_vref_code <5:0> may be traversed from 00 to 3F, but the code value of the threshold voltage control signal eom_vref_code <5:0> may be traversed to the first statistical result eom_value_p <5:0> and the second statistical result eom_value_n <5:0> of the EOM module 130, when the values of the sum are from 0 to non-0, the third critical result is obtained, the code value of the threshold voltage control signal eom_vref_code <5:0> at this time is recorded, the code value of the threshold voltage control signal eom_vref_code <5:0> is traversed, and the threshold voltage value corresponding to the code value of the threshold voltage control signal eom_vref_code <5:0> at this time is approximately equivalent to the maximum eye height value.
In practical application, when the signal Vin to be detected is not input, the signal detection system is in an off state, so that the power consumption of the signal detection system can be saved. When a high-speed signal Vin is input, the signal detection system can work normally.
It can be seen that the signal testing system provided by the embodiment of the application comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module, wherein the PI module is used for receiving a plurality of initial clock signals which are orthogonal to each other and clock phase control signals sent by the ALGO module, outputting a target clock signal, the EOM module is used for receiving a signal to be tested, the target clock signal and threshold voltage control signals sent by the ALGO module, outputting a statistical result of sampling the signal to be tested, the ALGO module is used for receiving the statistical result, determining the eye width value and the eye height value of the signal to be tested, that is, the eye pattern module performs sampling statistics on the signal to be tested by utilizing the target clock signals input by the phase interpolation PI module and the threshold voltage control signals sent by the ALGO module, and then the ALGO module determines the eye width value and the eye height value of the signal to be tested by utilizing the obtained statistical result, so that the eye height and eye width of the high-speed signal can be automatically stored and read, the design flow of signal testing is simplified, the design of signal testing and the test cost is lowered, and the implementation requirements are lower.
The foregoing is merely a preferred embodiment of the present application, and the present application has been disclosed in the above description of the preferred embodiment, but is not limited thereto. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.
Claims (5)
1. A signal testing system, the system comprising: the system comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module;
the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and clock phase control signals sent by the ALGO module and outputting target clock signals;
The EOM module is used for receiving a signal to be detected, the target clock signal and a threshold voltage control signal sent by the ALGO module and outputting a statistical result of sampling the signal to be detected;
the ALGO module is used for receiving the statistical result and determining an eye width value and an eye height value of the eye pattern of the signal to be detected;
The ALGO module is used for keeping the threshold voltage control signal as a voltage initial value, traversing the clock phase control signal, and sampling the signal to be detected according to the rising edge and the falling edge of the target clock signal to obtain a plurality of statistical results A of the signal to be detected; the statistical results A comprise a first critical result and a second critical result, the distance between clock phase values corresponding to the adjacent first critical result and second critical result is the eye width value of the eye pattern of the signal to be measured, the value of the first critical result is 0 to 0, and the value of the second critical result is 0 to 0;
The ALGO module is used for keeping the clock phase control signal as a phase initial value, traversing the threshold voltage control signal, and sampling the signal to be detected according to the rising edge and the falling edge of the target clock signal to obtain a plurality of statistical results B of the signal to be detected; the phase initial value is an intermediate value between clock phase values corresponding to a first critical result and a second critical result, the plurality of statistical results B comprise a third critical result, a threshold voltage value corresponding to the third critical result is an eye height value of the signal to be detected, the value of the third critical result is 0 to non-0, non-0 indicates that a signal edge at the phase passes through positive and negative threshold voltages, and 0 indicates that no signal edge at the phase passes through positive and negative threshold voltages.
2. The system of claim 1, wherein the EOM module comprises a threshold voltage setting module and a signal processing module;
The threshold voltage setting module is used for traversing a threshold voltage value according to the threshold voltage control signal, and the threshold voltage value is traversed and comprises the eye height value of the eye diagram;
The signal processing module is used for sampling the signal to be detected according to the rising edge and the falling edge of the target clock signal when traversing the threshold voltage value according to the threshold voltage control signal, so as to obtain and store a statistical result.
3. The system of claim 1, wherein the EOM module is further configured to send a statistics end flag signal to the ALGO module to send statistics of the signal under test to the ALGO module.
4. The system of claim 3, wherein the ALGO module is further configured to send a reset signal to the EOM module after receiving the statistics end flag signal sent by the EOM module, such that the EOM module resets according to the reset signal.
5. The system of any of claims 1-4, wherein the initial clock signal comprises a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the first clock signal having a frequency that is one-half of a frequency of the signal under test, the second clock signal being an inverse of the first clock signal, the third clock signal being the same frequency as the first clock signal and 90 ° out of phase, the fourth clock signal being an inverse of the third clock signal.
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