CN108062234B - System and method for realizing server host to access BMC FLASH through mailbox protocol - Google Patents
System and method for realizing server host to access BMC FLASH through mailbox protocol Download PDFInfo
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Abstract
The embodiment of the invention discloses a system and a method for realizing that a server HOST accesses a BMCFLASH through a mailbox protocol, which solve the problem that a server HOST controls FLASH through a BMC in the implementation process of using SoCFPGA to finish the BMC function of the server.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a system and a method for realizing that a server host accesses BMC FLASH through a mailbox protocol.
Background
A BMC (Baseboard Management Controller) in the server is responsible for monitoring and controlling functions of the server, and a server host in the standard realizes communication with the BMC through an LPC interface. Meanwhile, there is an application scenario in which: the server host needs to read or update the content in the FLASH controlled by the BMC, and the FLASH stores the firmware information of the system, i.e., the BIOS, thereby implementing the information acquisition and upgrading functions of the server host to the BIOS.
In the process of BMC localization, replacing an original BMC chip with an SoC (System on chip) FPGA to realize each interface function in the BMC function becomes a reality. The SoC FPGA is a programmable logic system integrating an ARM MPU, a kernel and various devices, has higher integration and lower cost, and greatly shortens the development cycle of products. In the BMC function completed by using the SoC FPGA, the HOST also needs to be implemented to control the FLASH. Currently, in the existing mode, HOST directly controls an SPI controller in the BMC through an LPC (Low Pin Count, an interface protocol) interface, so as to realize control of FLASH through the SPI interface. However, there are problems with this approach, such as: the access conflict problem, the problem brought by BMC restart, the problem of slow access speed and the potential safety hazard.
Disclosure of Invention
The embodiment of the invention provides a system and a method for realizing that a server host accesses BMC FLASH through a mailbox protocol, which aim to solve the problem of logic realization of the mailbox protocol in the localization process of BMC in the prior art.
In order to solve the technical problem, the embodiment of the invention discloses the following technical scheme:
the invention provides a system for realizing access of a server HOST to BMC FLASH through a mailbox protocol, and realizes access of the server HOST to BMC FLASH.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the mailbox module includes a write FIFO module, a read FIFO module, a write operation controller, a read operation controller, and a register module, where the write FIFO module is connected to the LPC controller and stores a read-write FLASH command and data received by the LPC controller; the write operation controller detects whether the write FIFO module has data or not; the register module stores data sent by the write operation controller and data written by the ARM controller; the read operation controller reads the data written by the register module ARM controller and stores the data into the read FIFO module.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the register module includes a read register unit and a write register unit, the read register unit is connected to the ARM controller and the read operation controller respectively, and the read register unit receives an address and data written by the ARM controller through an APB bus and sends the data to the read operation controller; the write register unit is respectively connected with the write operation controller and the ARM controller, receives the address and the data sent by the write operation controller, and sends the address and the data to the ARM controller through an APB bus.
The second aspect of the invention provides a method for realizing that a server host accesses BMC FLASH through a mailbox protocol, which comprises the following steps:
the server HOST sends a FLASH control instruction to the ARM controller through the mailbox module;
and the ARM controller sends the FLASH data to the server HOST through the mailbox module.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the server HOST sends a FLASH control command to the ARM controller through the mailbox module, including,
the server HOST sends a command for controlling the FLASH to the LPC controller;
the LPC controller analyzes the received command and then sends the analyzed command to the mailbox module;
the mailbox module processes the command according to a mailbox protocol and informs the ARM controller of reading the command;
and after reading the command, the ARM controller operates the BMC controller according to the content of the command, so that the read-write operation of the BMC controller on the FLASH is realized.
Further, the mailbox module processes the command according to the mailbox protocol and notifies the ARM controller of reading the command, including:
the write FIFO receives the data of the LPC controller, the write operation controller reads the address and the data from the write FIFO and sends the address and the data to the register module through the write register operation interface; and the write register unit receives the address and the data sent by the write operation controller, writes the address and the data into the corresponding register, and informs the ARM to read the content in the corresponding register through the APB bus by setting the interrupt register.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the ARM controller sends the FLASH data to the server HOST through the mailbox module, including,
the ARM controller sends the read FLASH data to the mailbox module;
the mailbox module processes the received data according to a mailbox protocol and informs the LPC controller to read the data;
the LPC controller sends the read data to the server HOST.
Further, the mailbox module processes the received data according to the mailbox protocol and informs the LPC controller to read the data, wherein the register reading unit receives addresses and data written by the ARM controller through an APB bus, writes the addresses and the data into a corresponding register, and informs the read operation controller to read the content of the corresponding register by setting an interrupt register; the read operation controller detects the write signal in the register module by reading the contents of the interrupt register, and if it is high, it will read the contents of the register and write the read data into the read FIFO.
According to the technical scheme, the problem that the server HOST controls FLASH through the BMC is well solved in the implementation process that the SoC FPGA is used for completing the function of the BMC of the server, and the mailbox protocol module logic developed by using the Verilog HDL language can be well butted with other modules and has good portability. The invention has good portability and operability, and is an important component of the localization of the BMC chip.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 2 is a schematic diagram of an internal implementation of the mailbox module of the present invention;
FIG. 3 is a flow chart of the steps of an embodiment of the method of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The Mailbox protocol is a mode that HOST can control FLASH through BMC, and is mainly characterized in that HOST and BMC perform information interaction through a register specified in the Mailbox, so that the HOST transmits data and commands to the BMC through the Mailbox, then the BMC operates FLASH independently, and the operated result is returned to the HOST through the register in the Mailbox, so that the operation on the FLASH is completed by the BMC completely. The invention mainly completes the design and realization of the mailbox protocol on the SoC FPGA.
As shown in figure 1, the system for realizing the access of the server HOST to the BMC FLASH through the mailbox protocol realizes the FLASH access of the server HOST to the BMC control, and comprises an ARM controller, a mailbox module, an LPC controller and a server HOST which are positioned on an SOC FPGA, wherein the ARM controller is connected with an APB bus, the APB bus is respectively connected with a BMC SPI controller, the mailbox module and the LPC controller, the BMC SPI controller is connected with the FLASH, the mailbox module is connected with the LPC controller, and the LPC controller is connected with the server HOST.
As shown in fig. 2, the mailbox module includes a write FIFO module, a read FIFO module, a write operation controller, a read operation controller, and a register module, where the write FIFO module is connected to the LPC controller and stores read-write FLASH commands and data received by the LPC controller; the write operation controller detects whether the write FIFO module has data or not; the register module stores data sent by the write operation controller and data written by the ARM controller; the read operation controller reads the data written by the register module ARM controller and stores the data into the read FIFO module.
The register module comprises a read register unit and a write register unit, the read register unit is respectively connected with the ARM controller and the read operation controller, and the read register unit receives an address and data written by the ARM controller through an APB bus and sends the data to the read operation controller; the write register unit is respectively connected with the write operation controller and the ARM controller, receives the address and the data sent by the write operation controller, and sends the address and the data to the ARM controller through an APB bus.
As shown in fig. 3, a method for realizing that a server host accesses a BMC FLASH through a mailbox protocol includes the following steps:
s1, the server HOST sends a command for controlling FLASH to the LPC controller;
s2, the LPC controller analyzes the received command and sends the command to the mailbox module;
s3, the mailbox module processes the command according to the mailbox protocol and informs the ARM controller of reading the command;
and S4, after the ARM controller reads the command, operating the BMC controller according to the content of the command, and realizing the read-write operation of the BMC controller on the FLASH.
S5, the ARM controller sends the read FLASH data to the mailbox module;
s6, the mailbox module processes the received data according to the mailbox protocol and informs the LPC controller to read the data;
s7, the LPC controller sends the read data to the server HOST.
In step S3, the mailbox module processes the command according to the mailbox protocol and notifies the ARM controller of reading the command, including: the write FIFO receives the data from the LPC controller, and when the LPC controller receives the command and data for controlling FLASH sent by HOST, the command and data are written into the write FIFO. The write operation controller detects an empty signal in the write FIFO, sets the empty signal to 0 to indicate that data exists in the FIFO, reads addresses and data from the write FIFO at the moment, and then sends the addresses and the data to the register module through the write register operation interface.
And the write register unit receives the address and the data sent by the write operation controller, writes the address and the data into the corresponding register, and informs the ARM to read the content in the corresponding register through the APB bus by setting the interrupt register.
In step S6, the mailbox module processes the received data according to the mailbox protocol and notifies the LPC controller to read the data, including that the register reading unit receives the address and data written by the ARM controller through the APB bus, writes the address and data into a corresponding register, and notifies the read operation controller to read the content of the corresponding register by setting an interrupt register.
The read operation controller detects the write signal in the register module by reading the contents of the interrupt register, and if it is high, it will read the contents of the register and write the read data into the read FIFO. The read FIFO receives data from the read operation controller and waits for the LPC module to read the data in the FIFO.
The interface signals of the logic module of the present invention are shown in table 1 below:
table 1 mailbox module interface signal table
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (2)
1. A system for realizing access of a server HOST to BMC FLASH through a mailbox protocol is characterized by comprising an ARM controller, a mailbox module, an LPC controller and a server HOST which are positioned on an SOC FPGA, wherein the ARM controller is connected with an APB bus, the APB bus is respectively connected with a BMC SPI controller, the mailbox module and the LPC controller, the BMC SPI controller is connected with FLASH, the mailbox module is connected with the LPC controller, and the LPC controller is connected with the server HOST;
the mailbox module comprises a write FIFO module, a read FIFO module, a write operation controller, a read operation controller and a register module, wherein the write FIFO module is connected with the LPC controller and stores read-write FLASH commands and data received by the LPC controller; the write operation controller detects whether the write FIFO module has data or not; the register module stores data sent by the write operation controller and data written by the ARM controller; the read operation controller reads the data written by the register module ARM controller and stores the data into the read FIFO module;
the register module comprises a read register unit and a write register unit, the read register unit is respectively connected with the ARM controller and the read operation controller, and the read register unit receives an address and data written by the ARM controller through an APB bus and sends the data to the read operation controller; the write register unit is respectively connected with the write operation controller and the ARM controller, receives the address and the data sent by the write operation controller, and sends the address and the data to the ARM controller through an APB bus.
2. A method for realizing access of a server host to a BMC FLASH through a mailbox protocol is characterized by comprising the following steps:
the server HOST sends a FLASH control instruction to the ARM controller through the mailbox module;
the ARM controller sends FLASH data to the server HOST through the mailbox module;
the server HOST sends a FLASH control instruction to the ARM controller through the mailbox module, including,
the server HOST sends a command for controlling the FLASH to the LPC controller;
the LPC controller analyzes the received command and then sends the analyzed command to the mailbox module;
the mailbox module processes the command according to the mailbox protocol and informs the ARM controller of reading the command;
after reading the command, the ARM controller operates the BMC controller according to the content of the command, so that the read-write operation of the BMC controller on the FLASH is realized;
the mailbox module processes the command according to the mailbox protocol and informs the ARM controller of reading the command, wherein the steps comprise:
the write FIFO receives the data of the LPC controller, the write operation controller reads the address and the data from the write FIFO and sends the address and the data to the register module through the write register operation interface; the write register unit receives the address and data sent by the write operation controller, writes the address and data into the corresponding register, and informs the ARM to read the content in the corresponding register through the APB bus by setting the interrupt register;
the ARM controller sends the FLASH data to the server HOST through the mailbox module, including,
the ARM controller sends the read FLASH data to the mailbox module;
the mailbox module processes the received data according to the mailbox protocol and informs the LPC controller to read the data;
the LPC controller sends the read data to the server HOST;
the mailbox module processes the received data according to the mailbox protocol, informs the LPC controller to read the data, including,
the register reading unit receives the address and data written by the ARM controller through the APB bus, writes the address and data into a corresponding register, and informs the read operation controller to read the content of the corresponding register by setting an interrupt register; the read operation controller detects the write signal in the register module by reading the contents of the interrupt register, and if it is high, it will read the contents of the register and write the read data into the read FIFO.
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| CN110781527B (en) * | 2019-09-29 | 2022-02-22 | 苏州浪潮智能科技有限公司 | Control register protection method and device |
| CN111290977B (en) * | 2020-01-16 | 2021-11-16 | 芯创智（北京）微电子有限公司 | Register access system and method based on DDR multi-data unit |
| CN113190482B (en) * | 2021-03-12 | 2023-03-14 | 山东英信计算机技术有限公司 | IPMI communication method, transmission system and receiving system for IPMI communication |
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