CN1080446A - Radio device with quick lock in phase-locked loop - Google Patents
Radio device with quick lock in phase-locked loop Download PDFInfo
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- CN1080446A CN1080446A CN 92105655 CN92105655A CN1080446A CN 1080446 A CN1080446 A CN 1080446A CN 92105655 CN92105655 CN 92105655 CN 92105655 A CN92105655 A CN 92105655A CN 1080446 A CN1080446 A CN 1080446A
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Abstract
A kind of communicator comprises a transmitter, a receiver and a fescan, also comprise a phase-locked loop, this phase-locked loop comprises a voltage controlled oscillator (VGO) with a signal input end, also comprises one first filter and one second filter.This first filter has a wideband response, and this second filter comprises a memory element, and having narrow frequency response should.This phase-locked loop comprises that also a change-over circuit determines that in two filters which be coupled on the voltage controlled oscillator.
Description
The present invention relates generally to communicator, particularly have the communicator of quick lock in (acquisition) phase-locked loop.
In the art, the radio device that has a phase-locked loop (PLL) is known.In general, PLL has a VCO and a ring wave filter, and it can be used for eliminating noise contribution from the control signal of VCO.Ring wave filter can be changed between two states, i.e. first state, it is logical that this state has a broadband of the noise bandwidth that is used to realize that phase-locked loop is big, so that obtain big carrying off the scope of obtaining and lock (acquistion) and one second state rapidly, it has a narrow passband that is used to realize the little noise bandwidth encircled, with reduce the influence of noise output signal on the oscillator and in given frequency spectrum the chatter of phase place.At F.M.Gardner, the book " Phase Lock Technique " (1966, the 53rd page) that John Wiley and Sons company etc. is shown illustrates.
In time division multiplex (TDM) communication system, at this moment, need to go to scan and on spendable channel, communicate with a high speed receiver and transmitter, so, aforesaid ring wave filter may not satisfy the requirement of system.The generation of problem is such fact, be that narrow band filter is not sufficiently fast for those channels that locking is being scanned, therefore, in order successfully to scan a plurality of channels, must make sacrifice aspect sweep time, United States Patent (USP) 4,117,420(Deconinck etc.) disclosed a PLL, it has a VCO and an additional filter that is coupling on the VCO control line.This ring wave filter comprises that two resistance connect with a memory element, changes between two states allowing.Two state conversion process are present in such moment, and the instantaneous value that promptly is stored in the signal in the ring wave filter electric capacity equals the mean value of VCO control signal.And this convertibility provides by two resistance of connecting with memory element.The output signal that time of changing between two states of this filter and method make VCO presents transition extremely responsive.These transitions can not allowed in the conversion TDM system fast.Therefore, obviously have a kind of needs, promptly for the radio device with PLL, it can successfully scan a plurality of channels and have minimum transition, and not sacrifice stability, noise immunity and transmitting time fast.
(the present invention) provides a kind of radio device that is used in time division multiplex transmission (TDM) communication system.It comprises a dispensing device, a receiving system, and a quick scanning radio frequency communications channels is to determine the scanning means of an exploitable channel.This radio device also comprises a phase-locked loop, is used to provide a reference signal that is used for this radio device, and locks above-mentioned available channel.This phase-locked loop comprises a voltage controlled oscillator (VCO), and it has a signal input end.This phase-locked loop also comprises one first filter and one second filter.This first filter has an output and a wideband response.This second filter comprises a memory element, and have narrow frequency response should.Described phase-locked loop also comprises a switching circuit, and it determines which and voltage controlled oscillator in two filters are coupled.
Fig. 1 is a phase-locked loop block diagram in accordance with the principles of the present invention.
Fig. 2 is the schematic diagram of the phase-locked loop part of Fig. 1 relevant with the present invention.
Fig. 3 is the block diagram of a radio communications set.
Fig. 4 is a time diagram of a TDM communication system.
Fig. 5 is according to TDM communication system of the present invention.
At first with reference to Fig. 5, it shows according to time division multiplex communication system 500 of the present invention.This communication system 500 comprises a control station 504, has an antenna relevant with it 502.This communication system 500 also comprises several wireless sets, has two portable radio devices 508 and 512 of associated antenna 506 and 510 as represented respectively.Communication between two portable radio devices 508 and 512 is communicated with by control station 504.This control station 504 also provides between portable radio device 508 and 512 to the communication of the unit that comprises other system that is not limited to telephone system.The transceiver of other type for example mobile radio apparatus also is suitable for this system, also can use.Above-mentioned portable radio device 508 constitutes communicator of the present invention.
Referring now to Fig. 1,, it has shown the block diagram of phase-locked loop of the present invention (PLL) 100.Although it is preferably that PLL is used for the present invention, adopt a FLL also can satisfy purpose of the present invention.Shown PLL100 comprises phase detectors 102, and it has the first input end that is connected to a reference signal 101, and reference signal 101 is self-excitation stabilized oscillators.Second input signal of phase detectors 102 is the feedback signals from the output of PLL circuit 100, and after the composition to PLL100 made an explanation, the origin of this feedback signal will have been known.The output of phase detectors 102 is coupled on the control input end of voltage controlled oscillator (VCO) 104.The output of switching circuit 106 is coupled on the control incoming line 103.Some doors are contained on switch road 106, and they are used to make narrow ring wave filter 108 couplings of a wide ring wave filter 110 and or decoupling from the control incoming line 103.Described wide ring wave filter 110 and narrow ring wave filter 108 constitute first and second filters among the present invention respectively.The switch of the door in switching circuit 106 is controlled by controller 116.Controller 116 involved other element uses that the communicator 508 of PLL100 is arranged.One of VCO104 output sampling feeds back to second input of phase detectors 102 behind 112N frequency division of a Fractional-N frequency device, the output signal 114 of VCO104 will be coupled on the proper circuit in the communicator 508, as hereinafter will discussing.
In order to address this problem, under the control of controller 116, switching circuit 106 is given the memory element charging of narrow ring wave filter 108 in advance, makes wide ring wave filter 110 be coupled on the control line 103 simultaneously.Because pre-charge, so, when it was coupled, narrow ring wave filter 108 was prepared.This pre-charge has caused reducing greatly in effective locking time of narrow ring wave filter 108.When use contains the communicator of PLL100, effective meaning that shortens locking time of narrow ring wave filter 108 will become more obvious.In send mode, after determined a spendable channel, just produced one leniently ring wave filter 110 to the conversion command of narrow ring wave filter 108.Then, in receive mode, utilize employed wide ring wave filter 110 to receive after the suitable digital code, this order just can produce.
With reference to Fig. 2, it is the part schematic diagram of phase-locked loop in accordance with the principles of the present invention, and including among this figure is the element of two filters 110 and 108, the part of switching circuit 106, phase detectors 102, and VCO104.For fear of unnecessary loaded down with trivial details, most of element of the element of frequency divider 112, controller 116 and phase detectors 102 is not included among Fig. 2.Two control signals 201 and 203 from phase detectors 102 are coupled to two current sources, i.e. source apparatus 202 and subside (sinking) device 204.As the part of its operation, source apparatus 202 provides current to switching circuit 106 with the memory element pre-charge to narrow ring wave filter 108.The element of switching circuit 106 comprises a buffer 206, and (non-inverting) input of not reversing is coupled to source apparatus 202 and is subside the node of (sinking) device 204.An analog gate 208 is coupled in the output of buffer 206, and this control signal is the D1214 analog gate in order to electric capacity 218 and 222 chargings, and they are memory elements of narrow ring wave filter 108.Resistance 220 is also contained in the narrow ring wave filter 108.What be coupled to resistance 220 nodes is the output of analog gate 216, and the control signal of this analog gate 216 is D1214, its input end grounding.The 3rd analog gate 212 is received in the output of analog gate 208, and the control signal of analog gate 212 is D2210.Control signal D1 and D2 provide their signals on the analog gate separately by controller 116.The output of analog gate 212 is coupled on the element of control line 103 and wide ring wave filter 110.These elements comprise an electric capacity 228, are in parallel with the branch road of connecting of electric capacity 224 and resistance 226.Their total binding place receives the input of analog gate 230, the output head grounding of this analog gate, and its control signal is D1 214.The feature of electric capacity 228,224 and resistance 226 is such, and promptly they offer wide ring wave filter 110 with the logical feature in desired broadband, are used for the fast frequency lock operation.
When phase-locked loop 100 went to lock a specific frequency by controller 116 order, control signal D1 214 and D2 210 were respectively high with low.When control signal D1 214 was high, three analog gates 208,216,230 were in connection (ON) state.Analog gate 208 is coupled to two electric capacity 222 and 218 with the output of buffer 206.At this moment, electric capacity 222 and 218 is by buffer 206 beginning precharge.When analog gate 216 was in by logical (ON) position, resistance 220 was removed from the grounding path of electric capacity 218, therefore, can provide than Low ESR to be used for charging current to electric capacity 218 chargings.Because analog gate 212 is in disconnection (OFF) position, the decoupling from the control line 103 of narrow ring wave filter 108.Get face generation be that wide ring wave filter 110 is coupled on the control line 103 because analog gate 230 is in the ON state.Because wide ring wave filter 110 is on the path of control incoming line 103, some noise contribution or be eliminated.After after a while, (this time) determines control signal D1 214 and D2 210 change states by the feature of the feature of phase-locked loop 100 or received signal of communication.Controller 116 order control line D1 214 and D2 210 become low and high state respectively.This causes analog gate 208,216 and 230 to convert the OFF attitude to, and analog gate 212 is the ON state.The OFF state of analog gate 208, just disconnected electric capacity 218 and 222 with precharge buffer 206 between connect.The OFF state of analog gate 216 just disconnects the grounding path of electric capacity 218 and resistance 220, so that allow two elements to play the filter effect.The OFF state of analog gate 230, the grounding path of wide ring wave filter 110 disconnects, and makes it to present floating shape.On the other hand, the ON state of analog gate 212 is coupled to narrow ring wave filter 108 on the control incoming line 103 of VCO 104.Because the more noise composition that narrow ring wave filter 108 in circuit, is present on the control incoming line 103 so can be eliminated.
In a word, shown phase-locked loop 100 will use two filters, promptly wide ring wave filter 110 and narrow ring wave filter 108.The use of these two filters has utilized their features separately to obtain quick lock in and to satisfy the low noise requirement of phase-locked loop 100.When wide ring wave filter 110 was worked, the memory element process buffer 206 of narrow ring wave filter 108 and analog gate 208 charged to one to it and control voltage accurately.The precharge of filter 108 has reduced its locking time effectively.After charging process is finished, (whether this process is finished) can be by the control voltage indication of narrow ring wave filter 108 outputs, this control voltage equals the voltage of wide ring wave filter 110 outputs substantially, at this moment, wide ring wave filter 110 can shift out in operation, and by narrow ring wave filter 108 replacements, so that narrow ring wave filter is provided for VCO control signal 103.Conversion regime between this two filters 108 and 110 has been eliminated the conversion transient in filter 108 and 110 coupling process.The operation of the needed time of conversion of control signal D1 214 and D2 210 ON and OFF to phase-locked loop 100 is important.Because concerning PLL100, in the short as far as possible time, lock a desirable frequency, so the above-mentioned time will carefully be calculated.Conversion between two wide ring wave filters 110 and the narrow ring wave filter 108 is important to the performance that allows to obtain the quick lock in time and don't sacrifice ring.
With reference to Fig. 3, shown in it is a kind of communicator 508 according to the principle of the invention.This communicator 508 comprises a transmitter and a receiver and makes its other element with scan function and PLL device that one is used for sending fast locking.The transmitter of communicator 508 and receiver have some squares, as shown in Figure 3.For avoiding complexity, the work of the element of communicator 508 will be described according to correlation between them.Antenna 302 is used for receiving and sending radiofrequency signal.Antenna 302 is coupled on the duplexer 304.Under the guidance of controller 116, duplexer 304 can partly and between the receiving unit be changed in the transmission of communicator 508.
In receive mode, a radiofrequency signal, preferably digital modulation can be received by antenna 302, and, be coupled on the RF amplifier 306 by duplexer 304 and a preselected device filter 305.The RF signal that amplifies is by filter 308 filtering.And deliver on the first input end of a frequency mixer 310.Second input of this frequency mixer 310 is coupled on first output of a switch 316.The input of this switch 316 (pole) is coupled on the output of a frequency multiplier 314, and the input of this frequency multiplier 314 is the output of PLL100.At this moment (in this), wide ring wave filter 110 is that engagement (engaged) is in PLL100.It is possible providing intrinsic bigger noise immunity by digital modulation system, and in general, numeral sends has quite high control random noise level ability, and therefore wide endless belt is wide allows for signal that is received of decoding.
Next, second input of frequency mixer 310 receives the signal 114 by frequency multiplier 314 frequencys multiplication, the output of frequency mixer 310 is coupled on the TDM demodulator 312 through filter 311, and here by demodulation, demodulated signal is delivered on the controller 116, and controller 116 determines whether the signal that is received is that communicator 508 is desirable.Its result is exactly that controller 116 command switch circuit 106 replace it with the wide ring wave filter 110 of decoupling and with narrow ring wave filter 108.When the memory element 218 and 222 of narrow ring wave filter 108 was charged to the required voltage of control signal 103, above-mentioned conversion was finished again.Because the desired charging process of electric capacity 218 and 222 exists, the so this transfer process that is transformed into a filter 108 from a filter 110 only can cause the correlated noise of minimum degree.Buffer 206 is amplifiers, has low-down bucking voltage.The low bucking voltage of this buffer 206 makes its output voltage be in close proximity to the input voltage of following it, and this input voltage is the control signal 103 that wide ring wave filter 110 connects.Analog gate 208,212,216 and 230 has low-down opening (ON) impedance, and this is necessary for the precise voltage that electric capacity 218 and 222 is charged to control signal 103.These selection of components provide one smoothly to change to the cardinal principle of another filter 108 from filter 110, and this suitable operation for PLL100 is necessary.
The content of 116 pairs of demodulated signals of controller is decoded to determine its suitable terminal point.Audio-frequency information is coupled on the loud speaker 318 through TDM demodulator 312.Data message via controller 316 is coupled on the display 326.The work of each square of communicator 508 is known in the prior art.For maximum possible also reduces complicated, remove detailed description to these square work, except those to work of element of the present invention necessary, TDM demodulator 312 can comprise the frequency that further reduces the signal that entered of one second change-over circuit.Also have digital demodulator, encoder, decoder and some that are included in the TDM demodulator 312 are used at the IF signal of the output of frequency mixer 310 circuit of demodulation in addition.Frequency multiplier 314 is used to increase the output frequency of phase-locked loop 100, is complementary to satisfy the requirement of frequency mixer 310 with the frequency of the signal that makes it and received.The reference signal 101 of PLL100 provides through oscillator 340.Controller 116 provides the scanning means of the receiver of communicator 508.
In send mode, switch 316 is transformed into transmitting terminal (pole), and duplexer 304 is transformed into send mode.Be applied to the output signal of information signal modulation VCO104 of the FM input 322 of PLL, as well known in the prior art.The output signal 114 of PLL100 is delivered on the frequency multiplier 314.At 314 places, the frequency of VCO output signal 114 is increased the requirement with the operating frequency that satisfies communicator 508.Frequency-doubled signal is coupled to amplifier 324 through switch 316 then.Amplifying signal earlier by 322 filtering of transmitter filter, was amplified by power amplifier 320 before it is sent to duplexer 304 again.Duplexer 304 is coupled to the transmission signal that is exaggerated to be used on the antenna 302 and sends.Controller 116 is coupled on duplexer 304 and the switch 316.Several other elements of the work of these two switches and this communicator 508 such as display 326 and demodulator 312 are all by controller 116 controls.
Refer again to Fig. 5, when the user of communicator 508 proposed a transmission request, receiver will attempt repeatedly to scan all spendable channels can be used for communication to determine which channel.In a preferred embodiment, communication system 500 comprises that 40 channels and receiver and transmitter are operated on the same frequency.So, receiver scans these 40 channels repeatedly, particularly 5 times, determines two spendable channels each time.Spendable channel is to select according to their signal strength signal intensity.The receiver of communicator 508 is chosen two channels with lowest signal intensity.This process repeats 5 times.Then, detect to determine which can remain on low signal intensity in these channels with lowest signal intensity in continuing scanning by controller 116.Like this, controller 116 selects a channel to be used for the transmission of communicator 508.The operating quick scan mode of this just communicator 508, it requires phase-locked loop 100 to have an antithesis (dual) filter scheme, so quick lock in and lowest noise degree can be provided in transmission.Scan a plurality of channels, particularly, 40, and repeatedly scanning (being 5 times among this embodiment) requires phase-locked loop to lock a channel with very high speed.Phase-locked loop 100 shown in Figure 1 can offer communicator 508 and have this high speed requirement.
With reference to Fig. 4, it has shown the time diagram of the course of work of communicator 508.This time diagram has comprised the starting point and the whole process of process.The starting point that 402 expression user requests begin to send.In other words, the 402nd, such moment is that synthesizer reception order removes to search and enter into a new channel.Are settling times of PLL100 periods 403.During the foundation of synthesizer, wide ring wave filter 110 inserts, and the memory element of narrow ring wave filter 108 is that electric capacity 218 and 222 is by precharge.Continuing of this time by 403 expressions.Starting point 404, communicator 508 is prepared reception information.In period 405, communicator 508 reception information, here, it is decoded to discern its number to data.At 406 places, positively discerned number, communicator 508 begins to handle the information that is received.The processing time of communicator 508 indicates by 407.After 407 finish, by 408 the indication, phase-locked loop 100 is transformed on the narrow ring wave filter 108.In period 409.Communicator 508 is according to the process of transmitting of TDM agreement (Protocol) the beginning signal that requires.
In order to understand the system of being discussed better, list some special times in the time diagram 400 here.Yet easy to understand is used in At All Other Times in other application similar result is provided.Duration 403 equals 1 microsecond, and it is illustrated in the settling time of the synthesizer among the PLL100.An important strong point of wide as can be seen ring wave filter 100 provides filter with quick lock in time to PLL100.Duration 405 equals 5 microseconds.The time durations that time difference between from 402 to 408 indicates approximates 6 1/2 microseconds greatly.During this, narrow ring wave filter 108 is recharged and inserts in phase-locked loop circuit.As can be seen, the benefit of the short locking time of wide ring wave filter 110 can be finished the high-velocity scanning channel.Can reduce to minimum because of the access of narrow ring wave filter 108 by wide ring wave filter 110 problems relevant that cause with performance degradation, this narrow ring wave filter 108 after a channel is locked just by precharge and start working.After scanning process is finished, and after the transmission of information and the reception beginning, narrow ring wave filter 108 just is converted and enters in the ring.
In a word, the phase-locked loop 100 that has two filters by use has been described, promptly 108 and with narrow ring feature have 110 of wide ring feature, so, communicator with high sweep speed can move in the TDM system, in send mode, when wide ring wave filter is used for scanning and can uses channel, reference signal to provide one to have precise frequency just is being provided narrow ring wave filter 108, and such frequency is through using the scanning of channel to determine.Owing to used the PLL100 with two filters 110 and 108, therefore, a plurality of channels of interscan are possible during the short time.Surmounting in sweep time, (overriding) factor no longer was the performance characteristic of ring wave filter.Between speed and ring performance, the needs that are used to sacrifice can reduce greatly.In receive mode, when the memory element 218 and 222 of narrow ring wave filter 108 had been recharged, the omen of a received information signal (preamble) was just assessed (evaluated) by wide ring wave filter 110.Very fast, being defined as when this signal is this receiver when required, and two filters 110 and 108 are converted offering whole superiority that PLL100 has the narrow ring feature of filter 108, and the charging rate that needn't slow down.Based on this scheme, conversion is actually no transition, because there is not decline in the voltage of the control signal of VCO104 103.An obvious advantage of the present invention is owing to have wide ring wave filter 110, communicator 508 can receive, decode and handle digital information signal and do not influence its sensitivity.During this, narrow ring wave filter 108 is ordered to prepare to receive by precharge.It should be noted that narrow ring feature need be used for keeping the advantage (spurs) by such transmitter that produces of discussing in the specification.
Another important advantage of quick lock in PLL of the present invention provides the power saving feature in the receiver.The fast speed of PLL allows radio device to remain on long period sleep (Sleep) mode, has lower battery consumption.This strong point is particularly conducive in the portable communication appts with battery size restriction.
Those skilled in the art can utilize other phase-locked loop to finish identical result.Really, the circuit of use FLL also is applicable to the work of communicator 508.Here shown communication system 500 and its element provide the preferred embodiments of the present invention.Yet this does not think restriction.It is not only unique a kind of possibility mode that the present invention is able to work.It is possible not breaking away from other variation of spirit of the present invention (as claim).
Claims (9)
1, a phase-locked loop (PLL), it is used for the communicator that can work on a plurality of channels, and this PLL comprises:
A voltage controlled oscillator (VCO) has a control signal input;
Be coupled to first filter apparatus of VCO, have an output and wideband response;
Be coupled to second filter apparatus of VCO, have an output, memory element and narrow frequency response should, be used for offering the described filter apparatus of PLL to lock of a plurality of channels;
Conversion equipment, has an output that is coupled to the VCO signal input end, a first input end is coupled on the output of first filter, one second input is coupled on the output of second filter, and a charging output is coupled on the memory element of second filter apparatus, when to the memory element precharge of second filter, conversion equipment is used for making in the pre-time durations of determining the output of first filter to be coupled to the signal input end of VCO, then, after finishing at the fixed time, the output of second filter is coupled to the signal input end of VCO.
2, according to the PLL of claim 1, wherein, memory element comprises an electric capacity.
3, according to the PLL of claim 1, wherein, conversion equipment comprises a plurality of switches.
4, according to the PLL of claim 1, wherein, conversion equipment comprises an analog gate.
5, a kind of transceiver, be used for a kind of time division multiplex communication system, this communication system has at least one control station, a plurality of radio device, and a plurality of radio frequency communications channels, they are distributed in and are used for the signal that exchanges information at least in two time slots (time slots) on set rates, and this transceiver comprises:
Scanning means is coupled on the receiver apparatus, is used for scanning selectively and as quick as thought radio frequency communications channels to determine a spendable channel;
Transmitter device is used to utilize described spendable channel to send information signal;
Receiver apparatus is used to utilize described spendable channel receiving information signal;
Phase-locked loop (PLL) device is used to lock above-mentioned spendable channel, and provides a reference signal to transceiver; This PLL comprises:
A voltage controlled oscillator (VCO), it has a signal input end;
First filter apparatus, it has an output and a wideband response, and being used for provides filter apparatus with scan communication channels apace to scanning means;
Second filter apparatus, it has an output, a memory element, and narrow frequency response should, be used for providing filter apparatus locking spendable channel, and have minimum interference noise level to PLL;
Conversion equipment, has an output that is coupled to the VCO signal input end, a first input end is coupled to the output of first filter, one second input is coupled to the output of second filter, and a charging output is coupled to the memory element of second filter apparatus, during the memory element precharge of described at that time second filter, in described conversion equipment is used for during preset time, make the output of first filter be coupled to the signal input end of VCO, then, after during above-mentioned preset time, finishing, the output of second filter is coupled to the signal input end of VCO.
6, according to the transceiver of claim 5, wherein, transmitter installation and receiver apparatus are worked on same frequency.
7, according to the transceiver of claim 5, wherein, memory element comprises electric capacity.
8, according to the transceiver of claim 5, wherein, conversion equipment comprises a plurality of switches (transducer).
9, according to the transceiver of claim 5, wherein, conversion equipment comprises analog gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 92105655 CN1029720C (en) | 1992-06-12 | 1992-06-12 | Radio with fast lock phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 92105655 CN1029720C (en) | 1992-06-12 | 1992-06-12 | Radio with fast lock phase-locked loop |
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| CN1080446A true CN1080446A (en) | 1994-01-05 |
| CN1029720C CN1029720C (en) | 1995-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 92105655 Expired - Fee Related CN1029720C (en) | 1992-06-12 | 1992-06-12 | Radio with fast lock phase-locked loop |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101823421A (en) * | 2008-07-31 | 2010-09-08 | 通用汽车环球科技运作公司 | Single-phase phase locked loop suitable for use in a hybrid vehicle charging system and method for charging a hybrid vehicle from a single-phase power source |
| CN102893522A (en) * | 2010-03-23 | 2013-01-23 | 华盛顿大学 | Frequency multiplying transceiver |
| CN104967448A (en) * | 2015-06-02 | 2015-10-07 | 海能达通信股份有限公司 | Phase-locked loop quick lock circuit and control method thereof |
-
1992
- 1992-06-12 CN CN 92105655 patent/CN1029720C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101823421A (en) * | 2008-07-31 | 2010-09-08 | 通用汽车环球科技运作公司 | Single-phase phase locked loop suitable for use in a hybrid vehicle charging system and method for charging a hybrid vehicle from a single-phase power source |
| CN101823421B (en) * | 2008-07-31 | 2014-08-06 | 通用汽车环球科技运作公司 | Single-phase phase locked loop suitable for use in a hybrid vehicle charging system and method for charging a hybrid vehicle from a single-phase power source |
| CN102893522A (en) * | 2010-03-23 | 2013-01-23 | 华盛顿大学 | Frequency multiplying transceiver |
| CN102893522B (en) * | 2010-03-23 | 2016-03-09 | 华盛顿大学 | Frequency multiplication transceiver |
| CN104967448A (en) * | 2015-06-02 | 2015-10-07 | 海能达通信股份有限公司 | Phase-locked loop quick lock circuit and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1029720C (en) | 1995-09-06 |
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