CN108037445A - FPGA aging tests system and its circuit collocation method - Google Patents
FPGA aging tests system and its circuit collocation method Download PDFInfo
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- CN108037445A CN108037445A CN201711186421.8A CN201711186421A CN108037445A CN 108037445 A CN108037445 A CN 108037445A CN 201711186421 A CN201711186421 A CN 201711186421A CN 108037445 A CN108037445 A CN 108037445A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
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Abstract
The invention discloses a kind of FPGA aging tests system and its circuit collocation method.Wherein, FPGA aging tests system includes：Multiple aging boards, are placed in ageing incubator, and each aging board includes：Several fpga chip socket, power interface and crystal oscillators, excitation is provided for aging board；Power distribution board, is placed in outside ageing incubator, and the power supply of multichannel independence is provided for each aging board；And configuration and monitoring board, it is placed in outside ageing incubator, comprising：PROM configures chip；Wherein, in aging test, several different fpga chips are positioned in the fpga chip socket in the aging board, several different fpga chips are configured at the same time from the PROM of monitoring board configurations one PROM of chip controls with passive serial mode by configuring.The system is suitable for the different fpga chips of same package, has versatility, saves the quantity of required nonvolatile semiconductor memory member, while introduces condition monitoring system and Safety assurance measures, and the chip status during ageing is monitored in real time.
Description
Technical field
The disclosure belongs to technical field of integrated circuits, is related to a kind of FPGA aging tests system and its circuit collocation method.
Background technology
FPGA has the advantages that programmable, high integration, high speed and high reliability.Pass through the logic work(inside configuration device
Energy and input/output end port, the design that original circuit board rank is realized is put and is carried out in the chips, improves circuit performance, is contracted
Small circuit volume, reduces circuit power consumption, effectively increases flexibility and the efficiency of design.
Integrated circuit has been widely used in the industries such as aviation, military affairs, industry at present, and its reliability is extensive as device
The one of application is big to consider key element, is that one kind allows product under stress as the aging test of one of most important reliability test
A period of time work to stablize the method for its characteristic.The stress that aging test uses needs to meet not destroying product electric property
Premise, can be rejected from a collection of product those raw material, design, production etc. because potential undesirable element and caused by have
The product of the meeting initial failure of defect；Choose the product of qualification with this, the reliability of product is protected.Tried by ageing
Test, can effectively reject the device containing inherent inherent shortcoming as caused by defective workmanship, ensure that the crash rate of device is horizontal and meet
User demand.If do not carried out aging test, catastrophic failure at initial stage or early stage occur under conditions of use containing defective device
Life failure.It is one for the extra high industry of reliability requirement, aging test especially for military industry, space flight industry etc.
Kind conventional means, and in reliability test, aging test is time-consuming most long, design therein experiment the most complicated.
Carrying out aging test for FPGA becomes a kind of optional reliability test of guarantee FPGA qualification rates, relative to it
Its monolithic integrated optical circuit, FPGA has the characteristics that volatibility, it is necessary to special non-volatile device storage configuration information, FPGA works
Need to configure it before work, and function is lost after powering down chips.
And the extensive use based on FPGA, aging test is carried out to various FPGA devices and various tests then occurs
System and method, between different test system and methods may compatibility it is poor, cumbersome and take, then it is a kind of there is an urgent need for proposing
FPGA aging test systems with versatility, and system structure is simple, is adapted to technology volume production.
The content of the invention
(1) technical problems to be solved
Present disclose provides a kind of FPGA aging tests system and its circuit collocation method, at least partly to solve above institute
The technical problem of proposition.
(2) technical solution
According to one aspect of the disclosure, there is provided a kind of FPGA aging tests system, including：Multiple aging boards, are placed in
In ageing incubator, each aging board includes：Several fpga chip sockets and power interface；Crystalline substance is additionally provided with outside ageing incubator
Shake, excitation is provided for each aging board；Power distribution board, is placed in outside ageing incubator, and multichannel independence is provided for each aging board
Power supply；And configuration and monitoring board, it is placed in outside ageing incubator, comprising：PROM configures chip；Wherein, it is some in aging test
A different fpga chips to be tested are positioned in the fpga chip socket in the aging board, by configuring and monitoring board
PROM configurations one PROM of chip controls configures several different fpga chips with passive serial mode at the same time.
In some embodiments of the present disclosure, configuration is further included with monitoring board：LED light, it is each for monitoring in real time
The working status of fpga chip, under the configuration mode of passive serial mode, any one FPGA in one group of fpga chip goes out
Now abnormal, LED light will indicate to make mistake.
In some embodiments of the present disclosure, output current maximum is set to the power supply powered to power distribution board, with
Preventing short circuit causes chip to burn.
In some embodiments of the present disclosure, power distribution board provides the power supply of three tunnel independences for each aging board, this three
The power supply of road independence is respectively：Core voltage (VCCINT), IO voltages (VCCO) and boost voltage (VCCAUX).
In some embodiments of the present disclosure, several different fpga chips have identical encapsulation, in control one
When PROM configures this several different fpga chip with passive serial mode at the same time, according to the demand of fpga chip to configuration electricity
Road carries out adaptability renewal.
According to another aspect of the disclosure, there is provided a kind of circuit collocation method of FPGA aging tests system, including：
FPGA ageing functional circuits are designed, bipolar random access memory (BRAM), digital signal inside maximal cover FPGA device
Handle the resource of (DSP), input and output (IO), D type flip-flops (DFF) and display look-up table (LUT)；Shaken electricity by inner inserting ring
Road measures device junction temperature, and junction temperature reaches setting during ensureing ageing, and ageing did not occurred；Using passive serial
Pattern configures fpga chip, and aging circuit excitation input is provided by crystal oscillator；And by configuring with monitoring board to old
Device state is monitored during refining.
In some embodiments of the present disclosure, interpolation annular oscillation circuit measures device junction temperature, during guarantee ageing
Junction temperature reaches setting, and ageing did not occurred, including：Determined that the vacant of temperature measurement circuit can be inserted into according to current configuration bit stream
Multigroup temperature measurement circuit is simultaneously inserted into position, and amended code stream is configured in FPGA to be measured；When reset signal is effective, ring
Enable Pin of shaking and the Enable Pin of frequency counter are in enabled disarmed state, and after reset signal relieving, temperature measurement circuit starts
Work, the enabled counter that produces start to count under the driving of external clock, while make ring Enable Pin of shaking effective；Produced when enabled
When the value meter of counter is to a certain predetermined value, make the Enable Pin of frequency counter effective, frequency counter shakes in ring exports clock
Driving under count；During when the enabled value meter for producing counter to another predetermined value more than a certain predetermined value, ring is allowed to shake enabled
The Enable Pin of end and frequency counter is invalid, and the count value in frequency counter and the frequency of external clock calculate at this time
Go out the frequency of oscillation of ring oscillator；And configuration calculates currently with monitoring board according to the count value of received frequency counter
The temperature of temperature measurement circuit position, while make it that reset signal is effective using the edging trigger of the Enable Pin of frequency counter,
Temperature measurement circuit is stopped.
In some embodiments of the present disclosure, the result measured according to interpolation annular oscillation circuit to device junction temperature is come to old
The input clock working frequency of refining circuit carries out feedback modification and iteration optimization.
In some embodiments of the present disclosure, the FPGA ageings functional circuit of design meets：Dominant bit is realized in BRAM
Wide RAM data storage and reading；The multiplying of maximum bit wide is realized in dsp；In DFF with realizing that four inputs are different in LUT
Or function；And in addition to input signal is encouraged, remaining all user's input/output pin (USER IO) passes through printed circuit board (PCB)
(PCB, Printed Circuit Board) path forms a scan chain with configuration inside FPGA.
In some embodiments of the present disclosure, it is at the same time to multiple to carry out configuration to fpga chip using passive serial mode
Fpga chip is configured, with the quantity of nonvolatile semiconductor memory member needed for saving.
(3) beneficial effect
It can be seen from the above technical proposal that FPGA aging tests system and its circuit methods that the disclosure provides, have
Following beneficial effect：
(1) by setting configuration and monitoring board in aging test system, which includes PROM configuration cores with monitoring board
Piece, the configuration of multiple fpga chips is carried out at the same time using a PROM under passive serial mode, and the mode of configuration is included outside piece
Clock source, microcontroller or daisy-chain etc., can carry out adaptability renewal to configuration circuit according to the demand of fpga chip, fit
For the different fpga chips of same package, there is versatility, and save the quantity of required nonvolatile semiconductor memory member；
(2) output current maximum is set to the power supply powered to power distribution board, prevents possible short circuit from causing chip
Burn；And the actual working state with fpga chip under a string formation row mode can be monitored in monitoring board in real time is configured, as long as
There is one of fpga chip to break down, just can be indicated, be convenient for fault diagnosis and re-power；Work along both lines,
Ageing system and the security of tested device are ensured；
(3) FPGA device inside junction temperature is carried out by the method for PROM configuration mode combination interpolation annular oscillation circuits real-time
Accurate test, accordingly carries out input clock working frequency feedback modification and iteration optimization, to reach ageing requirement junction temperature, realizes
The purpose of effective aging；And
(4) the characteristics of being enriched for IP kernel built in FPGA device, devises aging circuit, and is calculated by device junction temperature,
Rationally definite aging circuit working frequency, aging board exit is few, simple and convenient with the connecting line construction outside incubator.
Brief description of the drawings
Fig. 1 is the hardware architecture diagram according to embodiment of the present disclosure FPGA aging test systems.
Fig. 2 is the hardware system structure block diagram according to embodiment of the present disclosure aging board.
Fig. 3 is the configuration circuit schematic diagram according to embodiment of the present disclosure FPGA aging test systems.
Fig. 4 is according to the modularization design figure under embodiment of the present disclosure passive serial mode.
Fig. 5 is to be shaken temperature measurement circuit schematic diagram according to embodiment of the present disclosure ring.
【Symbol description】
10- power supplys；20- power distribution boards；
30- is configured and monitoring board；40- aging boards；
50- ageing incubators.
Embodiment
Present disclose provides a kind of FPGA aging tests system and its circuit collocation method, based on programmable read only memory
(PROM, Programmable Read-Only Memory) configuration mode, using PS configuration pattern, by incubator outside
Configuration FPGA is configured with monitoring board, the device state during ageing can monitor in real time；For in FPGA device
The characteristics of IP kernel is abundant is put, devises aging circuit, and is calculated by device junction temperature, rationally definite aging circuit working frequency,
Aging board exit is few, simple and convenient with the connecting line construction outside incubator；The aging test system, can be according to the demand of fpga chip
Adaptability renewal is carried out to configuration circuit, suitable for the different fpga chips of same package, there is versatility；And to power supply point
The power supply of matching board power supply sets output current maximum, prevents possible short circuit from causing chip to burn, plus to device state
The double shield security of ageing system and tested device is monitored in real time.
For the purpose, technical scheme and advantage of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
Attached drawing, is further described the disclosure.
The method that the FPGA aging test systems that the disclosure provides employ multiple FPGA while configuration, it is also non-needed for saving
The quantity of volatile memory device, while condition monitoring system and Safety assurance measures are introduced, to the chip during ageing
State is monitored.In terms of definite ageing stress, the method that device operating frequencies are determined by interpolation annular oscillation circuit is employed.
In first exemplary embodiment of the disclosure, there is provided a kind of FPGA aging tests system.
Fig. 1 is the hardware architecture diagram according to embodiment of the present disclosure FPGA aging test systems.Fig. 2 is according to the disclosure
The hardware system structure block diagram of embodiment aging board.
With reference to shown in Fig. 1 and Fig. 2, the FPGA aging test systems of the disclosure, including：
Multiple aging boards 40, are placed in ageing incubator 50, and each aging board 40 includes：Several fpga chip socket, electricity
Source interface and crystal oscillator, excitation is provided for aging board 40；
Power distribution board 20, is placed in outside ageing incubator 50, and the power supply of multichannel independence is provided for each aging board 40；And
Configuration and monitoring board 30, are placed in outside ageing incubator 50, comprising：Power interface, PROM configuration chips and LED instructions
Lamp, for monitoring the working status of each fpga chip in real time；
Wherein, in aging test, the fpga chip that several different fpga chips are positioned in the aging board 40 is inserted
In seat, configure one PROM of chip controls by configuring with the PROM of monitoring board 30 to configure with passive serial mode this at the same time some
A different fpga chip.
It is discussed in detail the various pieces of disclosure FPGA aging test systems below in conjunction with the accompanying drawings.
With reference to shown in Fig. 2, in the present embodiment, aging board 40 includes 9 fpga chip sockets, power interface and is ageing
Plate provides the crystal oscillator of excitation.
With reference to shown in Fig. 1, in the present embodiment, configuration is connected with the power interface that monitoring board 30 includes with power supply 10；This
In power supply can with power distribution board 20 share a power supply, independent other power supplys can also be used, as long as playing power supply
The power supply of effect, for simplicity, is illustrated in attached drawing with same reference numeral.
Shown in Figure 2, configuration further includes PROM configuration chips with monitoring board 30, and chip is configured by a PROM
To realize to being configured while 9 different fpga chips, fpga chip here has an identical encapsulation, but internal circuit knot
Structure is different, so just saves the quantity of required nonvolatile semiconductor memory member, and improves allocative efficiency.
Shown in Figure 2, in the present embodiment, configuration further includes the work for monitoring each fpga chip in real time with monitoring board 30
The LED light of state, it is same with passive serial mode with one PROM of the PROM of monitoring board 30 configuration chip controls due to configuring
When the different fpga chip of configuration, in the present embodiment, every 3 different fpga chips form the knot of a chain as one group
Structure, is configured with passive serial mode, as shown in Figure 2, share 3 assemble confidence number and meanwhile be configured to this 9 it is different
In fpga chip, the corresponding result of every group of fpga chip is exported to LED light, then as long as one of fpga chip occurs
Abnormal, LED light will indicate to make mistake, then can monitor the actual work of all fpga chips in real time by LED light
Make state.
With reference to shown in Fig. 2, excitation input terminal includes Din and rst_b.Wherein, Din is data input stimulus, it is preferred that
Din is the square-wave signal that amplitude is fixed, and is conducive to save memory space；Rst_b is circuit reset signal.Logic output terminal is
Dout, three chips are one group, and the Dout ends of first chip lead to the Din ends of second chip, the Dout of second chip
End leads to the Din ends of the 3rd chip, the Dout ends of the 3rd chip lead to incubator it is outer and with the LED light phase on monitoring board
Even, the working status inside FPGA is monitored accordingly.
Fig. 3 is the configuration circuit schematic diagram according to embodiment of the present disclosure FPGA aging test systems.With reference to Fig. 2 and Fig. 3 couples
The internal circuit configuration of FPGA aging test systems describes in detail.
Set for the hardware system of FPGA, it is contemplated that the test procedure of aging test maximal cover FPGA device as far as possible
The bipolar random access memory (BRAM, Biopolar Random Access Memory) of inside, Digital Signal Processing
(DSP, Digital Signal Processing), input and output (IO, Input-Output), D type flip-flops (DFF, D-
Type Flip-Flop) and display look-up table (LUT, Look-Up-Table) etc. resource：Maximum bit wide is realized in BRAM
RAM data is stored and read；The multiplying of maximum bit wide is realized in dsp；Four input exclusive or work(are realized in DFF and LUT
Energy；With reference to shown in Fig. 2, Fig. 3, in addition to input signal is encouraged, remaining all USER IO inside PCB paths and FPGA by configuring
A scan chain is formed, the output of I/O scan chain is Dout.
FPGA uses PS configuration pattern, shown in Figure 3 with the signal connection mode of configuration chip PROM, this reality
Apply in example, chip is configured using XCF32P as PROM FPGA is configured.Input signal includes two-way：Clock is defeated all the way
Enter signal；Circuit reset signal all the way, low level is effective, and corresponding in figure 3 here is PROG_B, represents configuration logical synchronization
Reset signal, low level are effective.Configurable clock generator (CCLK) is provided by crystal oscillator, and DONE pins and INIT_B pins need to connect drawing electricity
Resistance.Logic output signal：1 bit flag data output signal, which is followed by LED light, right during experiment
The working status of FPGA is monitored in real time.IO points of USER is three parts, and a part is excitation input terminal, a part is logic
Output terminal, another part are IO chains, wherein IO chains it is as detailed above in introduction to logic output terminal, which is not described herein again.
In the present embodiment, all output IO are each configured to LVTTL agreements, select maximum current drive ability.
With reference to shown in Fig. 1, power distribution board 20 is connected with power supply 10, and the power supply of multichannel independence is provided for aging board 40, this
In embodiment, it is illustrated with the power supply requirement of common FPGA, shown in Figure 3, power distribution board 20 is aging board
40 provide independent three-way power, this three-way power is respectively core voltage (VCCINT), IO voltages (VCCO) and auxiliary electricity
Press (VCCAUX), its corresponding magnitude of voltage is respectively：1.5V、3.3V、3.3V.
Preferably, to ensure the security of ageing system and measured device, to the power supply 10 powered to power distribution board 20
Output current maximum is set, prevents possible short circuit from causing chip to burn.
Fig. 4 is according to the modularization design figure under embodiment of the present disclosure passive serial mode.
Under series arrangement pattern, FPGA loads 1 configuration bit in each CCLK cycles.PROG_B is same for configuration logic
Reset signal is walked, low level is effective, and configuration is proceeded by after INIT_B rises, and DONE completes id signal for configuration.
Under passive serial mode, the CCLK pins of FPGA are driven by piece external clock source, and FPGA can also be patrolled by other
Collect to be configured, for example microcontroller is either configured in a manner of daisy-chain.
In the present embodiment, the aging test condition for the FPGA being placed in the FPGA aging test systems is as follows：
Ageing voltage：VCCINT is 1.5V, VCCO 3.3V, VCCAUX 3.3V；
Ageing temperature：125±5℃；
Burning-in period：240h；
Input terminal requirement：Input terminal uses the square-wave signal that crystal oscillator provides, and duty cycle is 40%~60%；
Output terminal requirement：LVTTL agreements are configured to, select 24mA driving forces；
Input request signal：Square wave, duty cycle are 40%~60%；
Amplitude：VIHShould be in the range of 2V to 3.6V, VILShould be in the range of 0V to 0.8V, conversion time t is less than or equal to
250ns；
R should be in the range of 1 × (1 ± 10%) k Ω.
Certainly, carrying out the parameter of specific aging test also needs the actual working stress tolerance range with reference to fpga chip, examination
Specific environment tested etc. carries out adaptability setting, and above-mentioned aging test condition is illustrative only.
In second exemplary embodiment of the disclosure, there is provided a kind of circuit configuration side of FPGA aging tests system
Method, including：FPGA ageing functional circuits are designed, BRAM, DSP, IO, DFF and LUT resource inside maximal cover FPGA device；
Device junction temperature is measured by interpolation annular oscillation circuit, junction temperature reaches setting during ensureing ageing, and does not occur old
Refining；Fpga chip is configured using passive serial mode, aging circuit excitation input is provided by crystal oscillator；And by with
Put and device state during ageing is monitored with monitoring board.
In the present embodiment, BRAM, DSP, IO, DFF inside FPGA ageing functional circuit maximal cover FPGA devices are designed
And LUT resources include：The RAM data storage of maximum bit wide is realized in BRAM and is read；Multiplying for maximum bit wide is realized in dsp
Method computing；Four input exclusive or functions are realized in DFF and LUT；In addition to input signal is encouraged, remaining all USER IO passes through PCB
Path forms a scan chain with configuration inside FPGA.
In the present embodiment, interpolation annular oscillation circuit, which measures device junction temperature, carries out input clock working frequency with realizing
Feedback modification and iteration optimization.
In the present embodiment, it is same to multiple and different fpga chips to carry out configuration to fpga chip using passive serial mode
When configure, save the quantity of configuration chip, i.e., the quantity of required nonvolatile semiconductor memory member greatly reduces.
For corps level and aerospace level FPGA device, internal junction temperature, which usually requires that, reaches 145 DEG C.To ensure device during ageing
The junction temperature of part reaches setting, and ageing does not occur, it is necessary to be measured to the device virtual junction temperature during ageing, accordingly
Feedback modification and iteration optimization are carried out to input clock working frequency.It is described below and is carried out using the FPGA aging tests system
During test, for the real-time testing means of temperature.
For the FPGA aging test systems, the present disclosure proposes shaken in the FPGA aging test systems by inner inserting ring
The method of circuit carries out the real-time testing of ageing junction temperature.To ensure the accuracy of temperature test, and suppress supply voltage and shake to ring
Frequency of oscillation influences, and phase inverter series is set as 25, as shown in the phase inverter illustrated in figure.To avoid the temperature measurement circuit of insertion certainly
Temperature caused by body heat production influences, and usually only allows temperature measurement circuit to run relatively short a period of time.
Fig. 5 is to be shaken temperature measurement circuit schematic diagram according to embodiment of the present disclosure ring.
With reference to shown in Fig. 5, using inner inserting ring shake circuit monitoring ageing junction temperature testing scheme it is as follows：
(1) determined to may be inserted into the vacant position of temperature measurement circuit according to current configuration bit stream, be inserted into multigroup temperature measurement circuit,
And amended code stream is configured in FPGA to be measured.The operation principle of each temperature measurement circuit is consistent.
(2) when reset signal reset is effective, ring shakes the Enable Pin of Enable Pin Ring_Enable and frequency counter
Capture_Enable is in enabled disarmed state.After reset signal reset relievings, temperature measurement circuit is started to work, and is enabled
Produce counter to start to count under the driving of external clock, while make Ring_Enable effective.
(3) when the enabled value meter for producing counter is to 1023, make Capture_Enable effective, frequency counter is in ring
Shake output clock Clk_out driving under count.There is time enough starting of oscillation in order to ensure ring shakes, retain enabled generation counter
1024 sufficient argins are count down to from 0.
(4) the equal nothings of Capture_Enable and Ring_Enable are allowed when the enabled value meter for producing counter is to 2047,
Effect.The count value in frequency counter and the frequency of external clock can calculate the oscillation frequency of ring oscillator at this time
Rate.
(5) configuration calculates current temperature measurement circuit position with monitoring board according to the count value of received frequency counter
Temperature.Make it that reset signal reset is effective using the edging trigger of Capture_Enable at the same time, temperature measurement circuit stops work
Make.
Making the effective count value of Enable Pin (the 1023 of the present embodiment) of frequency counter and allow ring to shake Enable Pin here
Count value (the 2047 of the present embodiment) invalid the Enable Pin Capture_Enable of Ring_Enable and frequency counter is only
Illustrate as more excellent example, in concrete operations, can rationally be set according to actual conditions.Certainly, to avoid inserting
Temperature caused by itself heat production of the temperature measurement circuit entered influences, and usually only allows temperature measurement circuit to run relatively short a period of time,
Set when counting it is also contemplated that this condition.
In conclusion present disclose provides a kind of FPGA aging tests system and its circuit collocation method, by ageing
Configuration and monitoring board are set in pilot system, which includes PROM configuration chips with monitoring board, using a PROM passive
The configuration of multiple fpga chips is carried out at the same time under serial mode, the mode of configuration includes piece external clock source, microcontroller or daisy-
Chain etc., can carry out adaptability renewal, suitable for the different FPGA of same package according to the demand of fpga chip to configuration circuit
Chip, has versatility, and saves the quantity of required nonvolatile semiconductor memory member；To being set to the power supply that power distribution board is powered
Output current maximum is put, prevents possible short circuit from causing chip to burn；And configure with one can be monitored in real time in monitoring board
The actual working state of fpga chip under string formation row mode, as long as there is one of fpga chip to break down, just can be referred to
Show, be convenient for fault diagnosis and re-power；Work along both lines, ensured ageing system and the security of tested device；It is logical
The method for crossing PROM configuration mode combination interpolation annular oscillation circuits carries out FPGA device inside junction temperature accurate test in real time, accordingly
Feedback modification and iteration optimization are carried out to input clock working frequency, to reach ageing requirement junction temperature, realizes the mesh of effective aging
's；And the characteristics of being enriched for IP kernel built in FPGA device, aging circuit is devised, and calculated by device junction temperature, rationally
Determine aging circuit working frequency, aging board exit is few, simple and convenient with the connecting line construction outside incubator.
Through attached drawing, identical element is represented by same or like reference numeral.It may cause to the disclosure
When understanding causes to obscure, conventional structure or construction will be omitted.And the shape and size of each component do not reflect actual size in figure
And ratio, and only illustrate the content of the embodiment of the present disclosure., should not will be any between bracket in addition, in the claims
Reference symbol is configured to limitations on claims.
Certainly, those skilled in the art in the art can also add corresponding function module, herein according to the needs of function
Do not repeat.Furthermore word "comprising" or " comprising " do not exclude the presence of element or step not listed in the claims.Positioned at member
Word "a" or "an" before part does not exclude the presence of multiple such elements.
Particular embodiments described above, has carried out further in detail the purpose, technical solution and beneficial effect of the disclosure
Describe in detail bright, it should be understood that the foregoing is merely the specific embodiment of the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of FPGA aging tests system, including：
Multiple aging boards, are placed in ageing incubator, and each aging board includes：Several fpga chip sockets and power interface；
Crystal oscillator is additionally provided with outside ageing incubator, excitation is provided for each aging board；
Power distribution board, is placed in outside ageing incubator, and the power supply of multichannel independence is provided for each aging board；And
Configuration and monitoring board, are placed in outside ageing incubator, comprising：PROM configures chip；
Wherein, in aging test, several different fpga chips to be tested are positioned over the fpga chip in the aging board
In socket, configure one PROM of chip controls by configuring with the PROM of monitoring board to configure with passive serial mode this at the same time some
A different fpga chip.
2. FPGA aging tests system according to claim 1, wherein, the monitoring board that is configured at further includes：
LED light, for monitoring the working status of each fpga chip in real time, under the configuration mode of passive serial mode,
There is exception in any one FPGA in one group of fpga chip, and LED light will indicate to make mistake.
3. FPGA aging tests system according to claim 1, wherein, the power supply powered to the power distribution board is set
Output current maximum is put, causes chip to burn to prevent short circuit.
4. FPGA aging tests system according to claim 1, wherein, the power distribution board provides for each aging board
The power supply of three tunnel independences, the power supply of this three tunnels independence are respectively：Core voltage, IO voltages and boost voltage.
5. FPGA aging tests system according to claim 1, wherein, several described different fpga chips have phase
With encapsulation, when controlling a PROM to configure with passive serial mode this several different fpga chip at the same time, according to
The demand of fpga chip carries out adaptability renewal to configuration circuit.
6. a kind of circuit collocation method of FPGA aging tests system, including：
FPGA ageing functional circuits are designed, the resource of BRAM, DSP, IO, DFF and LUT inside maximal cover FPGA device；
Device junction temperature is measured by interpolation annular oscillation circuit, junction temperature reaches setting during ensureing ageing, and does not occur
Cross ageing；
Fpga chip is configured using passive serial mode, aging circuit excitation input is provided by crystal oscillator；And
Device state during ageing is monitored with monitoring board by configuring.
7. circuit collocation method according to claim 6, wherein, the interpolation annular oscillation circuit surveys device junction temperature
Amount, junction temperature reaches setting during ensureing ageing, and ageing did not occurred, including：
According to current configuration bit stream determine that the vacant position of temperature measurement circuit can be inserted into and be inserted into multigroup temperature measurement circuit, and will modification
Code stream afterwards is configured in FPGA to be measured；
When reset signal is effective, the shake Enable Pin of Enable Pin and frequency counter of ring is in enabled disarmed state, waits to reset
After signal is decontroled, temperature measurement circuit is started to work, and the enabled counter that produces starts to count under the driving of external clock, while allows ring
Enable Pin of shaking is effective；
When the enabled value meter for producing counter is to a certain predetermined value, make the Enable Pin of frequency counter effective, frequency counter
Ring shake output clock driving under count；
When the enabled value meter for producing counter is to another predetermined value for being more than a certain predetermined value, ring is allowed to shake Enable Pin and frequency meter
The Enable Pin of number device is invalid, and the count value in frequency counter and the frequency of external clock calculate ring oscillation at this time
The frequency of oscillation of device；And
Configuration calculates the temperature of current temperature measurement circuit position with monitoring board according to the count value of received frequency counter,
Make it that reset signal is effective using the edging trigger of the Enable Pin of frequency counter at the same time, temperature measurement circuit is stopped.
8. circuit collocation method according to claim 7, wherein, device junction temperature is carried out according to the interpolation annular oscillation circuit
The result of measurement carries out the input clock working frequency of aging circuit feedback modification and iteration optimization.
9. circuit collocation method according to claim 6, wherein, the FPGA ageings functional circuit of design meets：
The RAM data storage of maximum bit wide is realized in BRAM and is read；
The multiplying of maximum bit wide is realized in dsp；
Four input exclusive or functions are realized in DFF and LUT；And
In addition to input signal is encouraged, remaining all user's input/output pin is by printed circuit board traces with matching somebody with somebody inside FPGA
Put to form a scan chain.
10. according to claim 6 to 9 any one of them circuit collocation method, wherein, it is described to use passive serial mode pair
It is that multiple fpga chips are configured at the same time that fpga chip, which carries out configuration, with the number of nonvolatile semiconductor memory member needed for saving
Amount.
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