CN108022897A - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
CN108022897A
CN108022897A CN201710285973.8A CN201710285973A CN108022897A CN 108022897 A CN108022897 A CN 108022897A CN 201710285973 A CN201710285973 A CN 201710285973A CN 108022897 A CN108022897 A CN 108022897A
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China
Prior art keywords
layer
release layer
encapsulating structure
connection pad
structure according
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CN201710285973.8A
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English (en)
Inventor
郑群逸
郑惟元
郭书玮
杨钰贞
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Priority claimed from TW106105304A external-priority patent/TWI637471B/zh
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Publication of CN108022897A publication Critical patent/CN108022897A/zh
Pending legal-status Critical Current

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Abstract

一种封装结构，其包括重布线路层、芯片、模塑料、多个球底离型层及多个焊球。重布线路层包括第一表面、相对第一表面的第二表面以及图案化线路层，其中图案化线路层包括多个突出于第一表面的接垫。芯片设置于第二表面并电性连接图案化线路层。模塑料设置于第二表面以包覆芯片。球底离型层分别包覆突出于第一表面的接垫。焊球分别设置于球底离型层上并与接垫电性连接。

Description

封装结构及其制作方法
技术领域
本发明是有关于一种封装结构及其制作方法。
背景技术
芯片封装可保护裸露的芯片、降低芯片接点的密度及提供芯片良好的散热。当芯片的接点数不断地增加，而芯片的面积却越来越小的情况下，势必难以将芯片所有的接点以面矩阵的方式重新分布于芯片的表面，即使芯片表面容纳得下所有的接点，也将造成接点之间的间距过小，而影响后续焊接焊球时的电性可靠度。
因此，一般封装技术提出了可先利用模塑料封装芯片来增加芯片的面积，其中芯片的有源表面与模塑料的底面暴露于外。之后，再于芯片的有源表面以及模塑料的底面上形成重布线路层，并在重布线路层的接点上分别形成焊球，来作为芯片与外界接点相电性连接的媒介。然而，此种方法由于封装时易产生溢胶的现象，而导致模塑料延伸至芯片的部分有源表面上，污染芯片的有源表面。
目前业界正在研发先于载板上形成重布线路层之后，再设置芯片于重布线路层上，并利用模塑料封装芯片之后再移除载板的做法。然而，移除载板后所暴露的重布线路层为平面且接合强度不足，难以进行植球。
发明内容
本发明实施例提供一种封装结构及其制作方法，其可在先形成重布线路层而后设置芯片的制作方法中增加与焊球的接合面积，以增进封装结构的可靠度。
本发明实施例的一种封装结构，包括：
重布线路层，包括第一表面、相对所述第一表面的第二表面以及图案化线路层，其中所述图案化线路层包括多个突出于所述第一表面的接垫；
芯片，设置于所述第二表面并电性连接所述图案化线路层；
模塑料，设置于所述第二表面以包覆所述芯片；
多个球底离型层，分别包覆突出于所述第一表面的所述接垫；以及
多个焊球，分别设置于所述球底离型层上并电性连接所述接垫。
根据本发明的实施例，各所述球底离型层包括与各所述焊球接触的接触表面，各所述接垫包括远离所述第一表面的外表面，所述接触表面的面积大于所述外表面的面积。
根据本发明的实施例，各所述球底离型层的表面粗糙度小于各所述接垫的表面粗糙度。
根据本发明的实施例，各所述球底离型层的材料包括金属、金属氧化物、金属合金或其组合。
根据本发明的实施例，所述重布线路层还包括：
第一介电层，包括多个开口及所述第一表面，其中所述图案化线路层设置于所述第一介电层上且所述接垫经由所述开口而突出于所述第一表面；
第二介电层，设置于所述第一介电层上并包括所述第二表面，所述第二介电层暴露部份所述图案化线路层；以及
球底金属层，设置于所述第二介电层上并电性连接所述图案化线路层。
根据本发明的实施例，所述芯片透过多个导电凸块而设置于所述球底金属层上。
本发明实施例还包括一种封装结构，包括：
重布线路层，包括第一表面、相对所述第一表面的第二表面以及设置于所述第一表面的图案化线路层，其中所述图案化线路层包括多个接垫，各所述接垫的外表面与所述第一表面共平面；
芯片，设置于所述第二表面并电性连接所述图案化线路层；
模塑料，设置于所述第二表面以包覆所述芯片；
多个球底离型层，设置于所述第一表面并分别覆盖所述接垫；以及
多个焊球，分别设置于所述球底离型层上并电性连接所述接垫，其中各所述球底离型层与各所述焊球接触的接触表面的面积大于各所述接垫的所述外表面的面积。
优选的，各所述球底离型层的表面粗糙度小于各所述接垫的表面粗糙度。
根据本发明的实施例，各所述球底离型层的材料包括金属、金属氧化物、金属合金或其组合。
根据本发明的实施例，所述重布线路层还包括：
第一介电层，包括多个开口，其中所述图案化线路层设置于所述第一介电层上且所述接垫设置于所述开口内，各所述接垫的所述外表面与所述第一介电层的表面共平面，以共同定义出所述第一表面；
第二介电层，设置于所述第一介电层上并包括所述第二表面，所述第二介电层暴露部份所述图案化线路层；以及
球底金属层，设置于所述第二介电层上并电性连接所述图案化线路层。
根据本发明的实施例，各所述球底离型层覆盖部分所述第一介电层。
根据本发明的实施例，所述芯片透过多个导电凸块而设置于所述球底金属层上。
本发明实施例还包括一种封装结构的制作方法，包括：
形成离型层于载板上；
形成重布线路层于所述离型层上，其中所述重布线路层包括连接所述离型层的第一表面、相对所述第一表面的第二表面以及图案化线路层，所述图案化线路层包括多个设置于所述第一表面的接垫，所述离型层与所述重布线路层之间的粘着力大于所述离型层与所述载板之间的粘着力；
设置芯片于所述第二表面上，其中所述芯片电性连接所述图案化线路层；
形成模塑料于所述第二表面以包覆所述芯片；
移除所述载板并图案化所述离型层，以形成多个覆盖所述接垫的球底离型层；以及
形成多个焊球于所述球底离型层上，其中所述焊球电性连接所述接垫。
根据本发明的实施例，还包括：
在形成所述离型层于所述载板上之前，形成多个粘着层于所述载板上。
根据本发明的实施例，所述离型层覆盖所述粘着层以及被所述粘着层所暴露的所述载板的表面，且所述离型层与所述粘着层之间的粘着力大于所述离型层与所述重布线路层之间的粘着力。
根据本发明的实施例，形成所述粘着层于所述载板上的方法包括溅射。
根据本发明的实施例，移除所述载板并图案化所述离型层的步骤还包括：
令所述载板及所述粘着层自所述离型层脱离，以移除与所述粘着层接触的部分所述离型层而形成所述球底离型层。
根据本发明的实施例，形成所述离型层于所述载板上的方法包括溅射，且所述离型层的材料包括金属、金属氧化物、金属合金或其组合。
根据本发明的实施例，图案化所述离型层的方法包括蚀刻。
根据本发明的实施例，所述芯片利用多个导电凸块以倒裝接合的方法设置于所述重布线路层上。
基于上述，本发明实施例的封装结构及其制作方法是先在载板上形成离型层，再于其上形成具有接垫的重布线路层，并在之后移除载板时对离型层进行图案化，以形成覆盖接垫的多个球底离型层。如此，在先形成重布线路层而后设置芯片的工艺下所形成的封装结构得以具有覆盖接垫的球底离型层。并且，由于球底离型层与焊球的接触面积大于接垫的外表面的面积，因而可增加其与焊球的接合面积，再者，球底离型层的表面粗糙度会小于接垫的表面粗糙度，因而可提升其与焊球的接合力，进而可在后续回焊工艺中帮助成球，增加封装结构的可靠度。
附图说明
图1至图9是依照本发明的一实施例的一种封装结构的制作方法的流程剖面示意图。
图10至图15是依照本发明的一实施例的一种封装结构的制作方法的流程剖面示意图。
其中附图标记为：
100、100a：封装结构 105：载板
110：粘着层 120：离型层
122：球底离型层 130：重布线路层
131、137：种子层 132：图案化线路层
132a：接垫 134：第一介电层
134a：开口 136：第二介电层
138：球底金属层 140：芯片
142：导电凸块 150：模塑料
160：焊球 R1：图案化光阻层
S1：第一表面 S2：第二表面
具体实施方式
为让本发明能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
有关本发明的前述及其他技术内容，在以下配合参考图式的各实施例的详细说明中，将可清楚的呈现。以下实施例中所提到的方向用语，例如：「上」、「下」、「前」、「后」、「左」、「右」等，仅是参考附加图式的方向。因此，使用的方向用语是用来说明，而并非用来限制本发明。并且，在下列各实施例中，相同或相似的元件将采用相同或相似的标号。
图1至图9是依照本发明的一实施例的一种封装结构的制作方法的流程剖面示意图。本实施例的封装结构的制作方法包括下列步骤。首先，请参照图1，形成多个粘着层110于载板105上，其中，任两相邻的粘着层110之间维持间距。在本实施例中，载板105可为玻璃载板、晶圆载板或不锈钢载板等。粘着层110的材料可包括金属、有机高分子材料或无机分子材料等。进一步而言，粘着层110的材料可包括钛，且粘着层110可例如透过溅射工艺而形成于载板105上。当然，本实施例仅用以举例说明，本发明并不限制载板105与粘着层110的材料及形成方法。
接着，请参照图2，形成离型层120于载板105上，其中，离型层120覆盖粘着层110以及被粘着层110所暴露的载板105的表面。在本实施例中，离型层120的厚度约介于50奈米(nm)至300奈米之间。离型层120的材料可包括金属、金属氧化物、金属合金或其组合。进一步而言，离型层120的材料可为铜或铝等具有导电性的材料，并且，离型层120可例如透过溅射工艺而形成于载板105上。离型层120与之后形成的图案化线路层132之间的粘着性可大于离型层120与载板105之间的粘着性。
接着，请参照图3至图6，形成重布线路层130于离型层120上，其中，重布线路层130可如图6所示的包括连接离型层120的第一表面S1、相对第一表面S1的第二表面S2以及图案化线路层132，其中，图案化线路层132包括多个设置于第一表面S1的接垫132a。在本实施例中，接垫132a突出于重布线路层130的第一表面S1。
详细而言，形成重布线路层130的方法可包括下列步骤。首先，如图3所示的形成第一介电层134于离型层120上，其中，第一介电层134包括多个开口134a及第一表面S1，此处的第一表面S1即为重布线路层130的第一表面S1。并且，开口134a暴露粘着层110之间的间距。接着，形成种子层131于第一介电层134上，且种子层131覆盖第一介电层134的开口134a及被开口134a所暴露的部分粘着层110。接着，如图4所示的形成图案化光阻层R1于第一介电层134上，且图案化光阻层R1的开口暴露第一介电层134的开口134a及开口134a所暴露的部分种子层131。之后再以种子层131作为导电路径进行电镀，而形成如图4所示的图案化线路层132于图案化光阻层R1的开口内，其中，图案化线路层132填充第一介电层134的开口134a，并经由开口134a而突出于第一介电层134的第一表面S1，以形成突出于第一表面S1的接垫132a。
接着，请参照图5，移除图案化光阻层R1并蚀刻移除被图案化光阻层R1所暴露的部分种子层131，之后再形成第二介电层136于第一介电层134上，其中，第二介电层136包括第二表面S2及多个暴露部分图案化线路层132的开口。接着，请参照图6，形成球底金属层138于第二介电层136的开口上，且球底金属层138透过第二介电层136的开口而电性连接至图案化线路层132。如此，即大致完成重布线路层130的制作。
详细而言，形成球底金属层138的方法可包括下列步骤。相似于前述形成图案线路层132的方法，首先，形成种子层137于第二介电层136上，且种子层137覆盖第二介电层136的开口及被其开口所暴露的图案化线路层132。接着，形成图案化光阻层于第二介电层136上，且图案化光阻层的开口暴露第二介电层136的开口及被其开口所暴露的部分种子层137。之后再以种子层137作为导电路径进行电镀，而形成如图5所示的球底金属层138于图案化光阻层的开口内。之后再移除图案化光阻层并蚀刻移除被图案化光阻层所暴露的部分种子层137即可完成球底金属层138的制作。
接着，请参照图7，设置芯片140于重布线路层130的第二表面S2上。在本实施例中，芯片140是利用多个导电凸块142而以倒裝接合的方法设置于重布线路层130的球底金属层138上，并透过球底金属层138而电性连接图案化线路层132。接着，形成模塑料150于重布线路层130的第二表面S2，以包覆芯片140。
接着，请参照图8，移除载板105并对离型层120进行图案化，以形成多个覆盖接垫132a的球底离型层122。在本实施例中，离型层120与重布线路层130的接垫132a之间的粘着力大于离型层120与载板105之间的粘着力，并且，离型层120与粘着层110之间的粘着力大于离型层120与重布线路层130的第一介电层134之间的粘着力。如此，当载板105及粘着层110自离型层120脱离时，与重布线路层130的介电层134接触的部分离型层120会随着粘着层110而一并被移除，以移除与粘着层110接触的部分离型层120，而与接垫132a接触的部分离型层120则因粘着力较强而留在接垫132a上，因而可形成包覆接垫132a的多个球底离型层122。如此，本实施例可在移除载板105的同时对离型层120进行图案化，以形成多个覆盖接垫132a的球底离型层122。在本实施例中，球底离型层122分别包覆突出于第一表面S1的接垫132a。
此外，由于在剥离载板105时容易对封装结构产生应力，进而导致重布线路层130中的线路产生断裂的情形，有鉴于此，在本实施例中，重布线路层130中的第一介电层134的材料硬度可小于第二介电层136的材料硬度。因此，换句话说，重布线路层130中较靠近载板105的介电层会比远离载板105的介电层更软，因而可帮助吸收远离载板105的介电层因载板105被剥离而承受的应力，进而可防止介电层内的线路产生断裂的情形。举例来说，由于无机材料相较于有机材料较硬，因此，在一实施例中，第一介电层134的材料可包括有机材料或有机无机混合材料，而第二介电层136的材料则可包括无机材料。或者，在另一实施例中，第一介电层134的材料可为有机材料，而第二介电层136的材料则可包括无机材料或有机无机混合材料。在本实施例中，球底离型层122可为有机材料。
接着，请参照图9，可形成多个焊球160于球底离型层122上，其中，焊球160与接垫132a透过球底离型层122而形成电性连接。至此，本实施例的封装结构100的制作方法即大致完成。在本实施例中，球底离型层122包括与焊球160接触的接触表面，接垫132a则包括远离第一表面S1的外表面，而球底离型层122的接触表面的面积大于接垫132a的外表面的面积。如此配置，本实施例的封装结构100的制作方法可在先形成重布线路层130而后设置芯片140的流程下，在移除载板105时即可同时形成包覆突出于第一表面S1的接垫132a的球底离型层122。并且，由于球底离型层122与焊球160的接触面积大于接垫132a的外表面的面积，因而可增加焊球160的接合面积，再者，溅射形成的球底离型层122的表面粗糙度会小于电镀形成的接垫132a的表面粗糙度，因而可提升焊球160的接合力，进而可在后续回焊工艺中帮助成球，增加封装结构100的可靠度。在本实施例中，溅射形成的球底离型层122的表面粗糙度约为0.2微米(μm)，而电镀形成的接垫132a的表面粗糙度则约为1.6微米。当然，本实施例仅为举例说明，实际的数值范围可能随着工艺技术的演进或实际产品需求而有所改变，本发明并不局限于此。
图10至图15是依照本发明的另一实施例的一种封装结构的制作方法的流程剖面示意图。在此必须说明的是，本实施例的封装结构100a的制作方法与前述实施例的封装结构100的制作方法相似，因此，本实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，本实施例不再重复赘述。以下将针对本实施例的封装结构100a与前述实施例的封装结构100的制作方法的差异做说明。
在本实施例中，离型层120可如图10所示的全面覆盖载板105的上表面。离型层120的材料可包括金属、金属氧化物、金属合金或其组合。接着，可依照相似于前述实施例图3至图6的制作流程形成如图11所示的重布线路层130于离型层120上。在本实施例中，重布线路层130包括第一表面S1、相对第一表面S1的第二表面S2以及设置于第一表面S1的图案化线路层132，其中，图案化线路层132包括多个接垫132a。
详细而言，重布线路层130的制作方法可如图11所示的形成第一介电层134于离型层120上，其中，第一介电层134包括多个开口(如图3所标示的开口134a)，且开口134a暴露部分离型层120。接着，形成种子层131于第一介电层134上，且种子层131覆盖第一介电层134的开口134a及被开口134a所暴露的部分离型层120。接着，可形成图案化光阻层于第一介电层134上，且图案化光阻层的开口暴露第一介电层134的开口134a及开口134a所暴露的部分种子层131。之后再以种子层131作为导电路径进行电镀，而形成图案化线路层132于第一介电层134上，且图案化线路层132填充于第一介电层134的开口134a内，以形成多个接垫132a。之后再移除图案化光阻层并蚀刻移除被图案化光阻层所暴露的部分种子层131即可。因此，在本实施例中，接垫132a(包含种子层131)的外表面与第一介电层134的表面共平面，以共同定义出重布线路层130的第一表面S1。接着，再依序形成第二介电层136以及球底金属层138而可完成如图11所示的重布线路层130的制作。
接着，如图11所示，芯片140可透过多个导电凸块142并以倒裝接合的方式设置于重布线路层130的第二表面S2上，并透过导电凸块142及球底金属层138而电性连接至图案化线路层130。接着，形成模塑料150于重布线路层130的第二表面S2，以包覆芯片140及导电凸块142。
接着，请参照图13及图14，移除载板105并对离型层120进行图案化工艺，以形成如图14所示的多个球底离型层122。在本实施例中，图案化工艺可包括激光钻蚀、干式蚀刻或湿式蚀刻等方法。如此，球底离型层122位于重布线路层130的第一表面S1并分别覆盖接垫132a，其中，各个球底离型层122会覆盖部分的第一介电层134。换句话说，球底离型层122会覆盖接垫132a，并覆盖接垫132a周围的部分第一介电层134。
之后，再如图15所示的形成多个焊球160于球底离型层122上，且焊球160透过球底离型层122而与接垫132a电性连接，其中，由于球底离型层122会覆盖接垫132a以及接垫132a周围的部分第一介电层134，故球底离型层122与焊球160接触的接触表面的面积会大于各接垫132a的外表面的面积，因而可增加焊球160的接合面积，再者，溅射形成的球底离型层122的表面粗糙度会小于电镀形成的接垫132a的表面粗糙度，因而可提升焊球160的接合力，进而可在后续回焊工艺中帮助成球，增加封装结构100a的可靠度。
综上所述，本发明实施例的封装结构及其制作方法是先在载板上形成离型层，再于其上形成重布线路层，并可在之后移除载板时对离型层进行图案化，以形成覆盖重布线路层的接垫的多个球底离型层。如此，在先形成重布线路层而后设置芯片的工艺下所形成的封装结构得以具有覆盖接垫的球底离型层。并且，由于球底离型层与焊球的接触面积大于接垫的外表面的面积，因而可增加其与焊球的接合面积，再者，溅射形成的球底离型层的表面粗糙度会小于电镀形成的接垫的表面粗糙度，因而可提升其与焊球的接合力，进而可在后续回焊工艺中帮助成球，因此，本发明实施例的封装结构及其制作方法可有效增加封装结构的可靠度。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (20)

1.一种封装结构，其特征在于，包括：
重布线路层，包括第一表面、相对所述第一表面的第二表面以及图案化线路层，其中所述图案化线路层包括多个突出于所述第一表面的接垫；
芯片，设置于所述第二表面并电性连接所述图案化线路层；
模塑料，设置于所述第二表面以包覆所述芯片；
多个球底离型层，分别包覆突出于所述第一表面的所述接垫；以及
多个焊球，分别设置于所述球底离型层上并电性连接所述接垫。
2.根据权利要求1所述的封装结构，各所述球底离型层包括与各所述焊球接触的接触表面，各所述接垫包括远离所述第一表面的外表面，所述接触表面的面积大于所述外表面的面积。
3.根据权利要求1所述的封装结构，各所述球底离型层的表面粗糙度小于各所述接垫的表面粗糙度。
4.根据权利要求1所述的封装结构，各所述球底离型层的材料包括金属、金属氧化物、金属合金或其组合。
5.根据权利要求1所述的封装结构，所述重布线路层还包括：
第一介电层，包括多个开口及所述第一表面，其中所述图案化线路层设置于所述第一介电层上且所述接垫经由所述开口而突出于所述第一表面；
第二介电层，设置于所述第一介电层上并包括所述第二表面，所述第二介电层暴露部份所述图案化线路层；以及
球底金属层，设置于所述第二介电层上并电性连接所述图案化线路层。
6.根据权利要求5所述的封装结构，所述芯片透过多个导电凸块而设置于所述球底金属层上。
7.一种封装结构，其特征在于，包括：
重布线路层，包括第一表面、相对所述第一表面的第二表面以及设置于所述第一表面的图案化线路层，其中所述图案化线路层包括多个接垫，各所述接垫的外表面与所述第一表面共平面；
芯片，设置于所述第二表面并电性连接所述图案化线路层；
模塑料，设置于所述第二表面以包覆所述芯片；
多个球底离型层，设置于所述第一表面并分别覆盖所述接垫；以及
多个焊球，分别设置于所述球底离型层上并电性连接所述接垫，其中各所述球底离型层与各所述焊球接触的接触表面的面积大于各所述接垫的所述外表面的面积。
8.根据权利要求7所述的封装结构，各所述球底离型层的表面粗糙度小于各所述接垫的表面粗糙度。
9.根据权利要求7所述的封装结构，各所述球底离型层的材料包括金属、金属氧化物、金属合金或其组合。
10.根据权利要求7所述的封装结构，所述重布线路层还包括：
第一介电层，包括多个开口，其中所述图案化线路层设置于所述第一介电层上且所述接垫设置于所述开口内，各所述接垫的所述外表面与所述第一介电层的表面共平面，以共同定义出所述第一表面；
第二介电层，设置于所述第一介电层上并包括所述第二表面，所述第二介电层暴露部份所述图案化线路层；以及
球底金属层，设置于所述第二介电层上并电性连接所述图案化线路层。
11.根据权利要求10所述的封装结构，各所述球底离型层覆盖部分所述第一介电层。
12.根据权利要求10所述的封装结构，所述芯片透过多个导电凸块而设置于所述球底金属层上。
13.一种封装结构的制作方法，其特征在于，包括：
形成离型层于载板上；
形成重布线路层于所述离型层上，其中所述重布线路层包括连接所述离型层的第一表面、相对所述第一表面的第二表面以及图案化线路层，所述图案化线路层包括多个设置于所述第一表面的接垫，所述离型层与所述重布线路层之间的粘着力大于所述离型层与所述载板之间的粘着力；
设置芯片于所述第二表面上，其中所述芯片电性连接所述图案化线路层；
形成模塑料于所述第二表面以包覆所述芯片；
移除所述载板并图案化所述离型层，以形成多个覆盖所述接垫的球底离型层；以及
形成多个焊球于所述球底离型层上，其中所述焊球电性连接所述接垫。
14.根据权利要求13所述的封装结构的制作方法，还包括：
在形成所述离型层于所述载板上之前，形成多个粘着层于所述载板上。
15.根据权利要求14所述的封装结构的制作方法，所述离型层覆盖所述粘着层以及被所述粘着层所暴露的所述载板的表面，且所述离型层与所述粘着层之间的粘着力大于所述离型层与所述重布线路层之间的粘着力。
16.根据权利要求14所述的封装结构的制作方法，形成所述粘着层于所述载板上的方法包括溅射。
17.根据权利要求15所述的封装结构的制作方法，移除所述载板并图案化所述离型层的步骤还包括：
令所述载板及所述粘着层自所述离型层脱离，以移除与所述粘着层接触的部分所述离型层而形成所述球底离型层。
18.根据权利要求13所述的封装结构的制作方法，形成所述离型层于所述载板上的方法包括溅射，且所述离型层的材料包括金属、金属氧化物、金属合金或其组合。
19.根据权利要求13所述的封装结构的制作方法，图案化所述离型层的方法包括蚀刻。
20.根据权利要求13所述的封装结构的制作方法，所述芯片利用多个导电凸块以倒裝接合的方法设置于所述重布线路层上。
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CN112151490B (zh) * 2019-06-27 2022-11-18 何崇文 基板结构及其制作方法与封装载板及其制作方法
CN113675155A (zh) * 2020-05-14 2021-11-19 南茂科技股份有限公司 晶圆级芯片尺寸封装结构及其制造方法

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