CN108009044B - Method for verifying FLASH data correctness in real time - Google Patents
Method for verifying FLASH data correctness in real time Download PDFInfo
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- CN108009044B CN108009044B CN201711100928.7A CN201711100928A CN108009044B CN 108009044 B CN108009044 B CN 108009044B CN 201711100928 A CN201711100928 A CN 201711100928A CN 108009044 B CN108009044 B CN 108009044B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/805—Real-time
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Abstract
The invention discloses a method for verifying FLASH data correctness in real time, and belongs to the technical field of high-reliability fault-tolerant computer design and comprehensive verification. The method is realized by adopting a bus with a check function, hardware circuits for checking FLASH and the like and an FPGA, check data is written in a maintenance mode, real-time check is realized in an application mode, and system overhead is not increased. A solution for verifying FLASH in real time is provided for a high-reliability fault-tolerant computer. The invention has the advantages that the verification is completed when the data FLASH is read, and the system overhead is not increased.
Description
Technical Field
The invention discloses a method for verifying FLASH data correctness in real time, and belongs to the technical field of high-reliability fault-tolerant computer design and comprehensive verification.
Background
In the development of a new generation of warplanes, the reliability of the operation of a fault-tolerant computer is more and more emphasized, and higher requirements are also put forward on the integrity of system test verification. The traditional method for verifying the data FLASH mainly performs primary verification on the data FLASH after the data FLASH is cured at two occasions, namely, the first occasion, and the data FLASH is verified correctly and then the cured data is considered correct; secondly, the data FLASH is tested in the testing stage, and both methods cannot detect the data accuracy in real time, so that the system reliability is low. The other method is to design a piece of check FLASH for storing check data, firstly read the data in the data FLASH, calculate the check value by software, then read the data in the check FLASH, and compare the two.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a method for verifying FLASH data correctness in real time. The method is realized by adopting a bus with a check function, hardware circuits for checking FLASH and the like and an FPGA, check data is written in a maintenance working stage, real-time check is realized in an application working stage, and system overhead is not increased. A solution for verifying FLASH in real time is provided for a high-reliability fault-tolerant computer.
The technical scheme of the invention is as follows: a method for verifying FLASH data correctness in real time is based on a hardware platform, the hardware platform comprises a bus with a verification function, a CPU, a memory, an FPGA and a FLASH hardware verification circuit, the FLASH hardware verification circuit comprises a data FLASH and a FLASH verification, data lines, address lines and control signals of the data FLASH and the FLASH verification are all connected to the FPGA, and the CPU, the FPGA and the memory are communicated through the bus, and the method comprises the following steps:
maintenance work phase
The CPU solidifies data to the data FLASH through the FPGA in a programming command sequence mode, solidifies a check value to the check FLASH through the FPGA, and the programming command sequence is formed by a series of write operations; in the stage, the FPGA allocates different chip selection spaces for the data FLASH and the check FLASH; the data and check value curing is divided into the following three steps:
1) the CPU initiates a programming command sequence to a chip selection space where the data FLASH is located, the programming command sequence is used for solidifying the data into the data FLASH, and the programming command sequence is formed by a series of write operations; after receiving each write operation, the FPGA controls a data line, an address line and a control signal of the data FLASH to realize the write operation on the data FLASH, and after the execution of the programming command sequence is finished, the data is solidified into the data FLASH;
2) calculating a check value of the solidified data in the FLASH data by the bus, and recording the check value by the FPGA;
3) the CPU reads the check value from the FPGA, and then initiates a programming command sequence to the chip selection space where the check FLASH is located; the programming command sequence is composed of a series of write operations and is used for solidifying the verification value into the verification FLASH; after receiving each write operation, the FPGA controls a data line, an address line and a control signal of the verification FLASH to realize the write operation of the verification FLASH; after the programming command sequence is executed, the check value is solidified into a check FLASH;
(II) working phase of application
The method realizes real-time verification at this stage, when the hardware platform is powered on to work, the CPU reads out the solidified data in the data FLASH and writes the data into the memory; in the stage, the FPGA allocates the same chip selection space to the data FLASH and the check FLASH; reading the solidified data in the data FLASH comprises the following two steps:
1) the CPU initiates a read operation to a chip selection space which is common to the data FLASH and the check FLASH; after receiving the read operation, the FPGA controls the data FLASH and the data line, the address line and the control signal of the verification FLASH to realize the concurrent read operation of the data FLASH and the verification FLASH; the FPGA submits the data returned by the FLASH reading operation and the check value returned by the FLASH reading operation to the bus;
2) and the bus carries out verification judgment according to the obtained data and the verification value, if the verification result is correct, the hardware platform works normally, if the verification result is wrong, the data is possibly wrong, and the bus sends an interrupt signal to the CPU to inform the CPU of the error.
The invention has the advantages that:
1. the verification is completed while the data FLASH and the verification FLASH are read, so that the real-time verification is realized;
2. and the bus is adopted to complete the verification, so that the system overhead is not increased.
Description of the drawings:
FIG. 1 is a schematic diagram of a hardware platform design
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The data FLASH stores key data such as an operating system, a driver and the like, and if the data stored in the data FLASH is wrong, the system cannot work normally, so that the data stored in the data FLASH is very key. A method for verifying FLASH data correctness in real time is based on a hardware platform, and the hardware platform comprises the following parts: the FLASH memory comprises a bus circuit with a check function, a CPU, a memory circuit, an FPGA circuit and a check FLASH hardware circuit, wherein the FPGA and the CPU communicate through a bus, the CPU is connected with the memory, the check FLASH hardware circuit comprises a data FLASH and a check FLASH, and data lines, address lines and control signals of the data FLASH and the check FLASH are all connected into the FPGA. The communication relationship among the components is detailed in the attached figure 1.
The method has two working stages, wherein the maintenance working stage writes in verification data, and the real-time verification is realized in the application working stage. The method adopts the following two working stages:
maintenance work phase
The maintenance work phase needs to complete three tasks: the FLASH data needs to be solidified; the bus needs to calculate the check value of the solidified data in the data FLASH; the verification of the FLASH requires the completion of the solidification of the verification value. The following is a detailed description:
1. the data FLASH needs to be solidified at this stage, and the CPU solidifies the data to the data FLASH. The data FLASH solidification data comprises the following three steps:
1) the solidified data is executed in a programming command sequence mode, the CPU initiates a programming command sequence to a chip selection space where the data FLASH is located, and the programming command sequence is formed by 4 times of write operations;
2) after receiving the write operation instruction, the FPGA controls a data line, an address line and a control signal of the data FLASH to realize the write operation on the data FLASH, the FPGA sets a chip selection signal and a write enable signal of the data FLASH to be valid, and data transmitted from the bus are solidified into a corresponding address space of the data FLASH to finish the solidification of the data;
3) the steps 1-2 are repeatedly executed until all the data are solidified into the data FLASH.
2. The bus calculates the check value of the solidified data in the FLASH, the FPGA records the check value, and the following two steps are required:
1) the bus with the check function is provided with a check bit data line, the check bit data line on the bus is accessed to the FPGA, when the CPU solidifies data in the data FLASH, the data is transmitted to the data FLASH through the bus, and the bus simultaneously generates a check value of the data;
2) and the FPGA records the check value.
3. And the verification FLASH needs to be solidified, and the verification FLASH is solidified by the CPU. The following three steps are adopted for verifying FLASH solidification data:
1) the solidification check value is executed in a programming command sequence mode, the CPU reads the check value from the FPGA, and initiates a programming command sequence to a chip selection space where the verification FLASH is located, wherein the programming command sequence is formed by 4 times of write operations;
2) after receiving the write operation instruction, the FPGA controls a data line, an address line and a control signal of the verification FLASH to realize the write operation on the verification FLASH, the FPGA sets a chip selection signal and a write enable signal of the verification FLASH to be valid, and the verification value is solidified into a corresponding address space of the verification FLASH to finish the solidification of the verification value;
3) and repeating the steps 1-2 until all the check values are completely solidified to the check FLASH.
In the maintenance working stage, the data in the data FLASH and the check value in the check FLASH are solidified, and the data FLASH and the check FLASH are not solidified any more after the stage is finished.
(II) working phase of application
The normal work of the hardware platform is in the application working stage, and the method realizes real-time verification at the stage. This stage accomplishes two tasks: reading data in the data FLASH and verifying a verification value in the FLASH; and the bus carries out checking judgment according to the obtained data and the check value. The following is a detailed description:
1. when the hardware platform is powered on and starts working, the CPU reads out the solidified data in the data FLASH and writes the data into the memory, the FPGA allocates the same chip selection space to the data FLASH and the check FLASH at the stage, and the reading of the check value in the data FLASH and the check FLASH is divided into the following two steps:
1) the CPU initiates a read operation to a chip selection space which is common to the data FLASH and the check FLASH; after receiving the read operation, the FPGA controls the data FLASH and the data line, the address line and the control signal of the verification FLASH, the FGPA sets the chip selection signal and the read enable signal of the data FLASH to be valid, and the FPGA sets the chip selection signal and the read enable signal of the verification FLASH to be valid, so that the concurrent read operation of the data FLASH and the verification FLASH is realized;
2) and the FPGA submits the data returned by the FLASH data reading operation and the check value returned by the FLASH check reading operation to the bus.
2. The bus acquires the FLASH data and the check value of the FLASH, the bus carries out check judgment, if the check result is correct, the hardware platform works normally, if the check result is wrong, the data is possibly wrong, and the bus sends an interrupt signal to the CPU to inform the CPU that the error occurs.
When the hardware platform is powered on to work, the invention reads the solidified data in the data FLASH and writes the data into the memory at the time when the CPU needs to read the data in the data FLASH and checks the FLASH check value, and the bus finishes the check without increasing the system overhead. A solution for verifying FLASH in real time is provided for a high-reliability fault-tolerant computer.
Claims (1)
1. A method for verifying FLASH data correctness in real time is characterized in that the method is based on a hardware platform, the hardware platform comprises a bus with a verification function, a CPU, a memory, an FPGA and a verification FLASH hardware circuit, the verification FLASH hardware circuit comprises a data FLASH and a verification FLASH, data lines, address lines and control signals of the data FLASH and the verification FLASH are all accessed to the FPGA, and the CPU, the FPGA and the memory are communicated through the bus, and the method comprises the following steps:
maintenance work phase
The CPU solidifies data to the data FLASH through the FPGA in a programming command sequence mode, solidifies a check value to the check FLASH through the FPGA, and the programming command sequence is formed by a series of write operations; in the stage, the FPGA allocates different chip selection spaces for the data FLASH and the check FLASH; the data and check value curing is divided into the following three steps:
1) the CPU initiates a programming command sequence to a chip selection space where the data FLASH is located, the programming command sequence is used for solidifying the data into the data FLASH, and the programming command sequence is formed by a series of write operations; after receiving each write operation, the FPGA controls a data line, an address line and a control signal of the data FLASH to realize the write operation on the data FLASH, and after the execution of the programming command sequence is finished, the data is solidified into the data FLASH;
2) calculating a check value of the solidified data in the FLASH data by the bus, and recording the check value by the FPGA;
3) the CPU reads the check value from the FPGA, and then initiates a programming command sequence to the chip selection space where the check FLASH is located; the programming command sequence is composed of a series of write operations and is used for solidifying the verification value into the verification FLASH; after receiving each write operation, the FPGA controls a data line, an address line and a control signal of the verification FLASH to realize the write operation of the verification FLASH; after the programming command sequence is executed, the check value is solidified into a check FLASH;
(II) working phase of application
The method realizes real-time verification at this stage, when the hardware platform is powered on to work, the CPU reads out the solidified data in the data FLASH and writes the data into the memory; in the stage, the FPGA allocates the same chip selection space to the data FLASH and the check FLASH; reading the solidified data in the data FLASH and the check value in the check FLASH comprises the following two steps:
1) the CPU initiates a read operation to a chip selection space which is common to the data FLASH and the check FLASH; after receiving the read operation, the FPGA controls the data FLASH and the data line, the address line and the control signal of the verification FLASH to realize the concurrent read operation of the data FLASH and the verification FLASH; the FPGA submits the data returned by the FLASH reading operation and the check value returned by the FLASH reading operation to the bus;
2) and the bus carries out verification judgment according to the obtained data and the verification value, if the verification result is correct, the hardware platform works normally, if the verification result is wrong, the data is possibly wrong, and the bus sends an interrupt signal to the CPU to inform the CPU of the error.
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