CN110674055B - Cache consistency simulation verification method for component level and component joint level - Google Patents
Cache consistency simulation verification method for component level and component joint level Download PDFInfo
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Abstract
The application relates to a cache consistency simulation verification method for a component level and a component joint level, which comprises the following steps: modeling a core cache; modeling the core function of the processor according to the interface protocol of the core and the out-core cache consistency control module; creating a core instruction monitor model, wherein the instruction monitor model is used for monitoring the communication condition of the core model and an out-of-core cache consistency control module; establishing a data comparison model; and creating a scoreboard model, wherein the scoreboard model is communicated with the instruction monitor model, and is used for receiving the information sent by the instruction monitor model and respectively processing according to the information type to finish verification. The application solves the problem of the re-establishment of the Cache consistency component level and component joint level verification environment caused by the modification of the design architecture due to the change of the core number.
Description
Technical Field
The application relates to the technical field of processor verification, in particular to a cache consistency simulation verification method for a component level and a component joint level.
Background
With the increasing size and complexity of integrated circuits, the design of a processor is more and more complex, and a plurality of processor cores are usually integrated on a chip, when two or more processor cores can perform read-write operation on the same Cache (Cache) block, if one core modifies the data, other cores containing the content of the data block do not update the data state in time, and data inconsistency can occur. The Cache consistency protocol is to maintain the consistency of a plurality of cores to the same visible Cache data. The Cache consistency protocol is a mechanism adopted for realizing consistency of shared data access and providing a logically unified shared main memory access interface. The correctness of the Cache consistency protocol design and implementation not only directly determines the correctness of the functions of the multi-core processor, but also has a critical influence on the scale and performance of the whole processor. Therefore, in the process of verifying the design of the chip, various verification and test works are performed for the design of the multi-core shared Cache.
At present, most of research and verification are carried out aiming at Cache consistency protocols, and various methods such as analog verification, formal verification, protocol level modeling and the like are adopted, so that the verification level is single, and the multi-level and multi-angle verification requirement of chip verification in large-scale integrated circuit design cannot be met. And the principle of verification adopted is as follows: and setting various states of the Cache blocks according to the Cache consistency protocol, and verifying that all paths which can reach the ending state are traversed from the initial state, so as to verify the completeness of the Cache consistency protocol. However, the protocol verification can only check the correctness of the jump between various states of the Cache line, and in the actual design, whether the data is stored, forwarded, lost, covered and the like among a plurality of cores, caches and main memories is also checked, not only if the result of the state transition is correct.
Disclosure of Invention
The application provides a Cache consistency simulation verification method for a component level and a component combination level, which solves the problem of Cache consistency component level and component combination level verification environment re-establishment caused by design architecture modification due to core number change.
The technical scheme adopted for solving the technical problems is as follows: the cache consistency simulation verification method for the component level and the component joint level comprises the following steps:
(1) Modeling a core cache to obtain a core cache model, wherein the core cache model has a function of an in-core cache controller conforming to the design, and can modify the state of a cache block and access the data of the cache block according to the request response type;
(2) Modeling a processor core function according to an interface protocol of a core and an out-of-core cache consistency control module to obtain a core model, wherein the core model can send legal requests to the out-of-core cache consistency control module according to a cache block state of the core cache model, and can change the cache block state of the core cache model according to a received response packet type and write cache block data;
(3) Creating a core instruction monitor model, wherein the instruction monitor model is used for monitoring the communication condition of the core model and an out-of-core cache consistency control module;
(4) Establishing a data comparison model, wherein the data comparison model is used for recording the latest data indexed by the cache line address of the core cache model, communicating with the scoreboard model, and updating the cache line address data according to the data instruction of the scoreboard model;
(5) And creating a scoreboard model, wherein the scoreboard model is communicated with the instruction monitor model, and is used for receiving the information sent by the instruction monitor model and respectively processing according to the information type to finish verification.
And (3) updating the cache line address data by the data comparison module in the step (4) when a write data instruction of the scoreboard model is received, and sending the data of the cache line address to the scoreboard model by the data comparison module when a read data instruction of the scoreboard model is received.
When the message type in the step (5) is a request type message, the scoreboard model takes the ID number of the request as an index, and registers the address and the type of the request; when the message type is a write data message, the scoreboard model sends write address and data to the data comparison model; and when the message type is a response type message, the scoreboard model inquires according to the ID number of the response, and if a corresponding request exists and the request type accords with the cache consistency protocol description type, checking to pass and deleting the registered request.
If the response type information carries data, the scoreboard model also needs to inquire the data comparison model according to the request address, check whether the response data is consistent with the data of the data comparison model, and accordingly check whether the design of the cache consistency control processing module is correct.
And (5) creating a main memory model connected with the out-of-core cache consistency control processing module according to the interface protocol of the out-of-core cache consistency control processing module and the main memory module, wherein the main memory model is used for receiving a memory access request from the out-of-core cache consistency control processing module.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the application has the following advantages and positive effects: the built core model comprises an intra-core Cache model, a pseudo-random excitation generator, a monitor model and a scoreboard model, wherein each core model achieves self-checking correctness, and when a simulation environment is built, the number of the core models can be configured according to the design scale, so that the problem of large-scale change of the simulation environment caused by the fact that the design architecture is simply increased or decreased due to cores is avoided; the method and the system verify the contents of the request, the response type and the data processing result of the Cache consistency protocol, and verify the correctness of the Cache consistency protocol, the Cache array, the design of the Cache controller and the like by traversing the legal request response type. The application models the memory control, realizes a complete memory access path of core memory access, off-core Cache and memory control, can directly build a component level environment to simulate and verify a Cache consistency control processing module, can directly replace a memory control model into a real memory control design after a later memory control code is mature, and can be used as a simulated environment for the transition of the off-core Cache and the memory control to a component joint level together to verify the memory control modeling, and the memory control modeling is completed according to an interface protocol, so that the verification environment can be switched between the component level and the component joint level at will.
Drawings
FIG. 1 is a block diagram of the core model architecture of the present application;
FIG. 2 is a schematic diagram of a component level verification environment of the present application;
fig. 3 is a verification flow chart of the present application.
Detailed Description
The application will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present application and are not intended to limit the scope of the present application. Furthermore, it should be understood that various changes and modifications can be made by one skilled in the art after reading the teachings of the present application, and such equivalents are intended to fall within the scope of the application as defined in the appended claims.
The embodiment of the application relates to a Cache consistency simulation verification method for a component level and a component joint level, which is characterized in that cores are required to be modeled, and as shown in fig. 1, the core model at least comprises an intra-core Cache model, a pseudo-random excitation generator, an instruction monitor model and a scoreboard model, each core model can achieve self-verification correctness through the structure, and when a simulation environment is built, the number of the core models can be configured according to a design scale, so that the problem of large-scale modification of the simulation environment caused by the increase and decrease of cores only by a design framework is avoided. The method specifically comprises the following steps:
a first step of: modeling the core Cache to obtain a core Cache model, so that the core Cache model has the function of a Cache controller in the core conforming to the design, and the Cache block state, the Cache block data access and the like can be modified according to the request response type.
And a second step of: modeling a processor core function according to an interface protocol of the core and the out-of-core Cache consistency control module to obtain a core model, so that the core model can send legal requests to the out-of-core Cache consistency control module according to the Cache block state of the core Cache model, and can change the Cache block state of the core Cache model according to the received response packet type and write Cache block data. Wherein the issuing of the request is implemented by the pseudo-random stimulus generator in fig. 1 and the receiving of the response packet type is implemented by the response controller in fig. 1.
And a third step of: and creating an instruction monitor model of the processor core, wherein the instruction monitor model is used for monitoring the communication condition of the core model and the out-of-core Cache consistency control processing module, and comprises a request initiated by the core model, write data sent to the Cache consistency control processing module by the core model, response sent to the core model by the Cache consistency control processing module, response data sent to the core model by the Cache consistency control processing module and the like.
Fourth step: the method comprises the steps of establishing a data comparison model, wherein the data comparison model is used for recording the latest data indexed by a Cache line address of a core Cache model, communicating with the scoreboard model, updating the Cache line address data of the data comparison model after receiving a write data instruction of the scoreboard model, and sending the data of the Cache address of the data comparison model to the scoreboard model after receiving a read data instruction of the scoreboard model. The verification environment for the construction of the data comparison model and the core model is shown in fig. 2.
Fifth step: and creating a scoreboard model which is communicated with the data comparison model and the instruction monitor model, and is used for receiving the information sent by the instruction monitor model and respectively processing according to the information type. As shown in fig. 3, if the message type is a request type message, the scoreboard model uses the ID number of the request as an index, registers the address and type of the request, and the like, if the message type is a write data message, the scoreboard model transmits the write address and data to the data comparison model, if the message type is a response type message, the scoreboard model queries according to the ID number of the response, if there is a corresponding request, and the request type matches the Cache coherence protocol description type, checks to pass, deletes the registered request, if the response carries data, checks whether the response data matches the data in the data comparison model according to the request address query data in addition to checking whether the request response type of the coherence protocol matches, so as to check whether the design of the Cache coherence control processing module is correct.
Therefore, the verification of the embodiment combines the contents of the request, the response type and the data processing result of the Cache consistency protocol, and the correctness checking of the two aspects can mutually check the correctness of the processing result of the Cache consistency protocol and the correctness of the design of the Cache consistency control processing module.
Sixth step: and creating a main memory model connected with the Cache consistency control processing module according to the interface protocol of the Cache consistency control processing module and the main memory module to perform modeling, so as to obtain the main memory model (namely the memory controllers 0-n in FIG. 3). The main memory model can receive the access memory request from the Cache consistency control processing module, and a storage array model is arranged in the main memory model, so that the address and the data of the write main memory request can be stored, and the data can be returned to the read main memory request.
The embodiment models the memory control, realizes a complete memory access path of core memory access, out-of-core Cache and memory control, can directly build a component level environment to simulate and verify a Cache consistency control processing module, can directly replace a main memory model into a real memory control design after a later memory control code is mature, and can directly verify the out-of-core Cache and memory control together as a simulation environment for transitioning to a component joint level by using the DUT, wherein the memory control modeling is completed according to an interface protocol, so that the verification environment can be switched between the component level and the component joint level at will.
Therefore, each module connected with the Cache consistency control module is modeled from the simulation angle, so that the correctness verification of the multi-core shared Cache function under the component-level and component-combination-level simulation environment is realized, the problem that the Cache consistency component-level and component-combination-level verification environment is built again due to the design architecture modification caused by the core number change is solved, and the Cache consistency results are verified from multiple angles, so that the Cache consistency verification is more reliable and universal.
Claims (2)
1. A cache coherency simulation verification method for a component level and a component joint level, comprising the steps of:
(1) Modeling a core cache to obtain a core cache model, wherein the core cache model has a function of an in-core cache controller conforming to the design, and can modify the state of a cache block and access the data of the cache block according to the request response type;
(2) Modeling a processor core function according to an interface protocol of a core and an out-of-core cache consistency control module to obtain a core model, wherein the core model can send legal requests to the out-of-core cache consistency control module according to a cache block state of the core cache model, and can change the cache block state of the core cache model according to a received response packet type and write cache block data;
(3) Creating a core instruction monitor model, wherein the instruction monitor model is used for monitoring the communication condition of the core model and an out-of-core cache consistency control module;
(4) Establishing a data comparison model, wherein the data comparison model is used for recording the latest data indexed by the cache line address of the core cache model, communicating with the scoreboard model, and updating the cache line address data according to the data instruction of the scoreboard model; the data comparison module updates the cache line address data when receiving a write data instruction of the scoreboard model, and sends the data of the cache line address to the scoreboard model when receiving a read data instruction of the scoreboard model;
(5) Creating a scoreboard model, wherein the scoreboard model is communicated with the instruction monitor model, and is used for receiving messages sent by the instruction monitor model and respectively processing according to the message types to finish verification; when the message type is a request type message, the scoreboard model takes the ID number of the request as an index, and registers the address and the type of the request; when the message type is a write data message, the scoreboard model sends write address and data to the data comparison model; when the message type is a response type message, the scoreboard model inquires according to the response ID number, and if a corresponding request exists and the request type accords with the cache consistency protocol description type, checking to pass and deleting the registered request; if the response type information carries data, the scoreboard model also needs to inquire the data comparison model according to the request address, and check whether the response data is consistent with the data of the data comparison model, so as to check whether the design of the cache consistency control processing module is correct.
2. The method for cache coherency simulation verification at the component level and the component joint level according to claim 1, further comprising the step of creating a master memory model connected to the off-core cache coherency control processing module according to an interface protocol of the off-core cache coherency control processing module and the master memory module after the step (5), wherein the master memory model is configured to receive a memory access request from the off-core cache coherency control processing module.
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| CN113315664B (en) * | 2021-06-16 | 2023-07-11 | 无锡江南计算技术研究所 | Message processing chip verification method |
| CN115618801B (en) * | 2022-12-01 | 2023-04-07 | 北京智芯微电子科技有限公司 | Cache consistency checking method and device and electronic equipment |
| CN116627331B (en) * | 2023-01-05 | 2024-04-02 | 摩尔线程智能科技(北京)有限责任公司 | Cache verification device, method and system |
| CN116167310A (en) * | 2023-04-25 | 2023-05-26 | 上海芯联芯智能科技有限公司 | Method and device for verifying cache consistency of multi-core processor |
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