CN107978585B - 堆叠式存储器封装件、其制造方法和ic封装基板 - Google Patents

堆叠式存储器封装件、其制造方法和ic封装基板 Download PDF

Info

Publication number
CN107978585B
CN107978585B CN201711370619.1A CN201711370619A CN107978585B CN 107978585 B CN107978585 B CN 107978585B CN 201711370619 A CN201711370619 A CN 201711370619A CN 107978585 B CN107978585 B CN 107978585B
Authority
CN
China
Prior art keywords
contacts
data
package
subset
package substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711370619.1A
Other languages
English (en)
Other versions
CN107978585A (zh
Inventor
A·费
E·R·博约
杨志平
吴忠华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of CN107978585A publication Critical patent/CN107978585A/zh
Application granted granted Critical
Publication of CN107978585B publication Critical patent/CN107978585B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06151—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1414—Circular array, i.e. array with radial symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1443—Non-volatile random-access memory [NVRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开提供了堆叠式存储器封装件、其制造方法和IC封装基板。更具体而言，涉及用于堆叠式半导体存储器封装件的***和方法。每个封装件可包括能够通过两个通道将数据传输到堆叠在封装件内的存储器裸片的集成电路(“IC”)封装基板。每个通道可位于IC封装基板的一侧上，并且来自每个通道的信号可从其相应侧引导到存储器裸片。

Description

堆叠式存储器封装件、其制造方法和IC封装基板
本申请是申请日为2013年12月19日、发明名称为“堆叠式存储器封装件、其制造方法和IC封装基板的插脚引线设计”的中国专利申请201380074494.1的分案申请。
技术领域
本公开涉及堆叠式存储器封装件、其制造方法和IC封装基板的插脚引线设计。
背景技术
各种类型的非易失性存储器(“NVM”)诸如闪存存储器(例如NAND闪存存储器和NOR闪存存储器)可被用于进行海量存储。例如，消费电子设备(例如便携式媒体播放器)使用闪存存储器来存储数据，包括音乐、视频、图像、和其它媒体或信息类型。消费电子工业中目前的趋势涉及在更小的设备中使用更多NVM，从而导致需要增加数据存储密度的创新封装方案。
发明内容
本发明提供了用于堆叠式半导体存储器设备的***和方法。堆叠式半导体存储器封装件可包括封装基板和被布置成箭头形叠层的多个NVM裸片。NVM裸片叠层可用表面安装插座(诸如例如矩栅阵列(“LGA”))被安装在封装基板上并且通信地耦接到该封装基板。NVM裸片可以箭头形构型被堆叠在封装件内，其中一半的NVM裸片沿第一方向形成阶梯，并且一半的NVM裸片旋转180°并沿相反的第二方向继续所述堆叠。存储器控制器可经由印刷电路板(“PCB”)或印刷线路板(“PWB”)、封装基板、和引线键合所提供的电连接来与NVM裸片通信。
根据一些实施例，可与上述堆叠式半导体存储器设备一起使用新型表面安装插脚引线设计。插脚引线设计可被配置为通过例如使承载高速信号的连接的差分对之间的距离最小化、使引线键合长度最小化、避免封装件内高速信号的交叉、在高速引脚的中央提供接地(“GND”)引脚、以及将高速引脚和低速引脚分开来提高信号完整性。根据其他实施例，可优化高速引脚的放置，以改善每个单独NVM封装件内或在整个NVM***上的信号完整性。表面安装插脚引线设计可适应两个通信通道，所述两个通信通道被配置为使得每个通道的相应引脚在旋转180°时对称地放置。
附图说明
本发明的上述及其他方面、其性质和各种特征将在考虑到下面结合附图进行的详细描述后变得更为显而易见，附图中相似的附图标记始终指示相似的部件，并且其中：
图1是示出根据各种实施例的包括主机和具有存储器控制器的NVM封装件的示例性***的示意图；
图2为根据各种实施例的图1的NVM封装件的剖视图；
图3为根据各种实施例的原生NVM封装件的剖视图；
图4是根据各种实施例的示出插脚引线设计的表面安装封装基板的仰视平面图；
图5是根据各种实施例的示出另一插脚引线设计的表面安装封装基板的另一仰视平面图；并且
图6为根据各种实施例的用于制造堆叠式半导体存储器设备的方法的流程图。
具体实施方式
近年来随着每个集成电路(“IC”)所需要的互连数量已经增大超过了传统通孔IC封装件(例如双列直插式封装件(“DIP”)和针栅阵列(“PGA”))的能力，用于IC的表面安装封装件已经变得普及。表面安装IC封装件的示例包括球栅阵列(“BGA”)和矩栅阵列(“LGA”)。BGA或LGA可包括在封装基板的底表面上布置在x-y平面中的触点阵列。触点可被焊接到第二基板(诸如例如PCB或PWB)的相应触点。第二基板可包括用于向IC封装件承载信号的导电迹线和从IC封装件承载信号的导电迹线。
本文所公开的示例性实施例可涉及IC封装基板，为清楚起见将其称为LGA。然而，本领域的技术人员可认识到，可用任何合适类型的表面安装封装件或通孔封装件来替代LGA，而不会背离本发明的实质。
特别地，LGA的底表面上的触点可利用穿过封装基板形成的导电通路而被引导到顶表面。LGA还可包括封装基板的顶表面上的导电焊盘和/或迹线，用于通信地耦接到安装在LGA之上的一个或多个IC。在一些实施例中，引线键合焊盘可形成在LGA的顶表面上，用于将触点通信地耦接到一个或多个IC。另外，叠层中的第一IC可被倒装芯片键合到封装基板的顶表面。在一些实施例中，IC封装件可以是NVM封装件，并且倒装芯片键合的IC可以是NVM封装件的存储器控制器。
在一些实施例中，NVM封装件可包括安装到LGA的顶表面的NVM裸片的叠层。该叠层可以是箭头形的，其中第一一半的NVM裸片沿第一方向形成阶梯，并且第二一半的NVM裸片继续该堆叠并沿相反的方向形成阶梯。这个箭头形堆叠式裸片布局可在每个NVM裸片的顶表面上提供暴露部分，用于接收引线键合线。第一一半的NVM裸片可从LGA的与阶梯的台阶相邻的侧引线键合到封装基板，而第二一半的NVM裸片可从相对侧(即与第二阶梯的台阶相邻)引线键合到LGA。第二阶梯中的NVM裸片可相对于第一一半中的那些NVM裸片旋转180°，使得键合焊盘面向正确的方向来接收引线键合线。
形成在LGA的底侧面上的触点可被布置为使得第一组触点(例如第一通道)可被布置在封装基板的与第一阶梯的台阶最靠近的侧上，以使那些触点与顶表面上的引线键合焊盘之间的布线距离最小。第一组触点可专用于第一一半的NVM裸片。类似地，第二组触点(例如第二通道)可被布置在封装基板的与第二阶梯的台阶最靠近的侧上。第二组触点可专用于第二一半的NVM裸片。下文中将参考图4和5更详细地讨论各种触点布置的进一步优化。
图1是示出***100的示意图，包括主机102和NVM封装件104。主机102可与NVM封装件104通信，NVM封装件104可包括存储器控制器106、主机接口110、和具有相应NVM 128a-n的存储器裸片112a-n。主机102可以是多种主机设备和/或***中的任一种，诸如便携式媒体播放器、蜂窝电话、口袋大小的个人计算机、个人数字助理(“PDA”)、台式计算机、膝上型计算机、和/或平板计算设备。NVM封装件104可包括NVM 128a-n(例如在存储器裸片112a-n中)，并且可以是球栅阵列封装件或其他合适类型的集成电路(“IC”)封装件。NVM封装件104可以是主机102的一部分，和/或可以与主机102分开。例如，主机102可以是板级设备，并且NVM封装件104可以是安装在板级设备上的存储器子***。在其它实施例中，NVM封装件104可以有线(例如SATA)或无线(例如蓝牙TM)接口耦接到主机102。
主机102可包括被配置为与NVM封装件104交互的主机控制器114。例如，主机102可将各种访问请求(诸如读取、编程、和擦除操作)传输到NVM封装件104。主机控制器114可包括被配置为基于软件和/或固件指令的运行来执行操作的一个或多个处理器和/或微处理器。除此之外和/或另选地，主机控制器114可包括被配置为执行各种操作的基于硬件的部件，诸如专用集成电路(“ASIC”)。主机控制器114可根据主机102与NVM封装件104之间共享的通信协议来为传输给NVM封装件104的信息(例如命令、数据)制定格式。
主机102可包括存储部件134，存储部件可包括易失性存储器108。易失性存储器108可以是多种易失性存储器类型中的任何一种，诸如高速缓存存储器或RAM。主机102可使用易失性存储器108来执行存储器操作和/或暂时存储正从NVM封装件104读取和/或正被写入到NVM封装件104的数据。例如，易失性存储器108可暂时存储要被发送到NVM封装件104或要存储从NVM封装件104接收的数据的存储器操作队列。
主机102可通过通信通道116与NVM封装件104通信。通信通道116可以是固定的(例如固定的通信通道)、可拆卸的(例如通用串行总线(USB)、串行高级技术(SATA))、或者无线的(例如蓝牙TM)。与NVM封装件104的交互可包括提供访问请求和传输数据(诸如要被编程到一个或多个存储器裸片112a-n的数据)给NVM封装件104。通过通信通道116的通信可在NVM封装件104的主机接口110处被接收。主机接口110可以是存储器控制器106的一部分和/或可以通信地连接到存储器控制器106。在一些实施例中，例如当存储器控制器106位于NVM封装件104之外时，也可从NVM封装件104中省略主机接口110。
类似于主机控制器114，存储器控制器106可包括被配置为基于软件和/或固件指令的运行来执行操作的一个或多个处理器和/或微处理器120。除此之外和/或另选地，存储器控制器106可包括被配置为执行各种操作的基于硬件的部件，诸如ASIC。存储器控制器106可执行多种操作，诸如执行主机102发起的访问请求。
主机控制器114和存储器控制器106单独地或组合地可执行各种存储器管理功能，诸如垃圾回收和磨损均衡。在存储器控制器106被配置为执行至少一些存储器管理功能的具体实施中，NVM封装件104可被称为“被管理NVM”(或对于NAND闪存存储器，被称为“被管理NAND”)。这可与“原生NVM”(或对于NAND闪存存储器是“原生NAND”)形成对照，在“原生NVM”(或对于NAND闪存存储器是“原生NAND”)中，NVM封装件104外部的主机控制器114为NVM封装件104执行存储器管理功能。
在一些实施例中，存储器控制器106可与存储器裸片112a-n并入到同一封装件中。在其它实施例中，存储器控制器106可物理地位于单独封装件中或与主机102位于同一封装件中。在一些实施例中，存储器控制器106可被省略，并且通常由存储器控制器106执行的所有存储器管理功能(例如垃圾回收和磨损均衡)可由主机控制器(例如主机控制器114)来执行。
存储器控制器106可包括易失性存储器122和NVM124。易失性存储器122可以是多种易失性存储器类型中的任何一种，诸如高速缓存存储器或RAM。例如，存储器控制器106可使用易失性存储器122来执行访问请求和/或暂时存储正从和/或向存储器裸片112a-n中的NVM 128a-n读取和/或写入的数据。此外，易失性存储器122可存储固件，并且存储器控制器106可使用固件来对NVM封装件104执行操作(例如读取/编程操作)。
存储器控制器106可使用共享内部总线126来访问可被用于持久性数据存储的NVM128a-n。虽然在NVM封装件104中示出了仅一个共享内部总线126，但NVM封装件可包括不止一个共享内部总线。每个内部总线可连接到多个(例如2个、3个、4个、8个、32个等等)存储器裸片，如参考存储器裸片112a-n所描绘的那样。存储器裸片112a-n可被物理地布置在多种构型中，包括堆叠构型，并且根据一些实施例可以是IC裸片。根据一些实施例，布置为堆叠构型的存储器裸片112a-n可用导电环氧树脂迹线被电耦接到存储器控制器106。将在下文参考图3至5对这些实施例进行更详细的讨论。
NVM 128a-n可以是多种NVM中任何一种，诸如NAND闪存存储器(基于浮栅或电荷捕获技术)、NOR闪存存储器、可擦除可编程只读存储器(“EPROM”)、电可擦可编程只读存储器(“EEPROM”)、铁电RAM(“FRAM”)、磁阻RAM(“MRAM”)、相变存储器(“PCM”)、或其任意组合。
图2为根据各种实施例的NVM封装件204的剖视图。NVM封装件204可包括存储器裸片212a-h和LGA 230，如上所述，LGA 230可以是任何适当的封装基板，诸如例如LGA、BGA、或PGA。NVM封装件204和存储器裸片212a-h可分别对应于图1中的NVM封装件104和存储器裸片112a-n。NVM封装件204还可包括包封232和引线键合线240。特别地，NVM封装件204可以是不包括专用的封装内存储器控制器(诸如例如存储器控制器106)的“原生”NVM封装件。
上述元件可被安装在基板234上，基板234可以是用于整个NVM***(例如图1的***100)或NVM***一部分的基板，诸如例如PCB或PWB。基板234可包括促成***多个部件之间的连通性的传导引线。例如，NVM封装件204的LGA 230可(例如利用焊料)通信地耦接到基板234的触点(未示出)，并且所印刷的导体(未示出)可将存储器裸片212a-h电耦接到主机控制器(例如图1的主机控制器114)和/或其他***部件。
为了防止操作期间或在极端条件下对NVM封装件204的损坏，LGA 230、包封232、和存储器裸片212a-h可由具有类似热膨胀系数的材料制成。例如，存储器裸片212a-h可以是在硅晶片上处理的集成电路裸片，LGA 230可以是由布料或纤维材料和树脂的层形成的层合体，并且包封232可以是塑料、陶瓷、或硅橡胶复合物。在其它实施例中，存储器控制器206可在任何合适的基板(例如Ge、GaAs、InP)上处理，并且包封232可以是为存储器控制器206提供物理保护和环境保护的任何合适的包封材料。包封232也可被选择为有效地从存储器裸片212a-h散热。
NVM封装件204可完全或部分地被包封在电磁干扰(“EMI”)屏蔽罩236中。EMI屏蔽罩236可阻止从NVM封装件204的部件发射电磁辐射。类似地，EMI屏蔽罩236可防止外部源所发射的电磁和/或射频干扰对NVM封装件204的部件产生损坏。一般来讲，EMI屏蔽罩236可充当法拉第笼，其可阻碍电场和/或电磁场的传播。此外，EMI屏蔽罩236可耦接到地，以便消散电荷。如图2所示，EMI屏蔽罩236可以是包围NVM封装件204的一部分或全部的“罐”型EMI屏蔽罩。根据一些实施例，EMI屏蔽罩236内的空间可以是空的(例如填充以空气)。在其它实施例中，EMI屏蔽罩336内的空间可被填充以适当的电介质材料。根据一些实施例，EMI屏蔽罩236也可利用标准涂层技术(例如物理气相沉积(“PVD”)、化学气相沉积(“CVD”)、旋涂等)而被沉积在包封232材料上，作为共形导电薄膜。
虽然本文所述的实施例涉及特定半导体裸片(例如存储器控制器和存储器裸片)，但本领域的技术人员将会知道，半导体封装件(例如NVM封装件204)可包含半导体裸片的任何适当组合。例如，封装件可包括连接到其它半导体裸片的叠层(包括易失性存储器、非易失性存储器、和/或一个或多个模拟电路裸片)的微处理器裸片。
NVM封装件204可以是堆叠式半导体裸片构型的示例，因为一个或多个单独半导体芯片(例如存储器裸片212a-h)被布置为堆叠构型。在一些实施例中，存储器裸片212a-h利用任何适当的粘合剂(例如环氧树脂)附连到LGA 230的表面，并且彼此附连。堆叠式半导体裸片构型相比于电路板构型提供了大量优点，在电路板构型中，各个半导体芯片侧向地安装在电路板上。例如，堆叠构型的裸片具有更小的“占用面积”，这在期望总体设备尺寸小的应用中可能是有利的。事实上，因为封装件的占用面积可非常接近最大半导体芯片的尺寸，所以NVM封装件204可被称为“芯片级封装件”。堆叠存储器裸片还提高了电子设备的数据存储密度，从而允许在相同物理空间中存储更多数据。
虽然在图2中示出了八个存储器裸片，但本领域的技术人员将会知道，任何适当数量的存储器裸片可被并入到NVM封装件204中，这受制于空间、布线、和/或结构限制。
根据一些实施例，各个存储器裸片可利用引线键合线240被通信地耦接到LGA230。引线键合方法可涉及将柔性线从LGA 230的第一表面238上的键合焊盘260附接到在存储器裸片212a-h上形成的键合焊盘262。这些线可由任何合适的高导电的可延展金属(例如Al、Au、Cu)制成。根椐所需要的外部连接的数量，LGA 230和/或存储器裸片212a-h上的键合焊盘可交错。使键合焊盘交错可降低键合焊盘间距(键合焊盘之间中心到中心的距离)，并允许比直列键合焊盘更多的外部连接。使键合焊盘交错可能要求LGA 230上的键合焊盘成阶梯状，以防止相邻线之间的短接。
通过这个引线键合方法，存储器裸片212a-h可通信地耦接到LGA 230以及各个其它***部件(例如图1的主机102)。引线键合线240以及LGA 230与基板234的电连接组合地可代表例如图1的共享内部总线126。
为了形成图2中所示的箭头形结构，各个存储器裸片212a-h可被堆叠并胶合在一起，其中相邻存储器裸片彼此略微偏移，从而在每个存储器裸片上得到暴露表面。存储器裸片212a-h的暴露表面可包括用于耦接到引线键合线240的键合焊盘262。如图2中所示，存储器裸片的一半(即存储器裸片212a-d)可沿第一方向形成阶梯，从而留出更靠近NVM封装件204的第一边缘的暴露表面，并且存储器裸片的一半(即存储器裸片212e-h)可沿第二方向形成阶梯，从而留出更接近NVM封装件204的与第一侧相对的第二边缘的暴露表面。引线键合线240可分别从NVM封装件204的第一侧和第二侧耦接到存储器裸片212a-d和212e-h。
图3为根据各种实施例的NVM封装件304的剖视图。NVM封装件304可包括存储器控制器306、存储器裸片312a-f、和LGA 330。NVM封装件304、存储器控制器306、存储器裸片312a-h可分别对应于例如图1的NVM封装件104、存储器控制器106、和存储器裸片112a-n。NVM封装件304还可包括包封332和引线键合线340。以上元件可被安装在基板334上，基板334可以是用于整个NVM***(例如图1的***100)或NVM***的一部分的基板。因为NVM封装件304可包括存储器控制器306，所以NVM封装件304可以是“被管理”NVM。
如图3所示，存储器控制器306可以任何合适的粘合剂(例如环氧树脂)被键合到LGA 330，如上所述，LGA 330可以是任何适当的封装基板，诸如例如LGA、BGA、或PGA。另外，存储器控制器306可包括活性表面350和非活性表面352。在这些实施例中，存储器控制器306的活性表面350可被倒装芯片键合到LGA 330的第一表面338。因此，存储器控制器306可包括形成在活性表面350上的焊料凸块316，其可用于将存储器控制器306倒装芯片键合到LGA 330的第一表面338。存储器裸片312a-h可利用任何适当的粘合剂(例如环氧树脂)被安装在存储器控制器306的非活性表面352上。
一般来讲，倒装芯片键合与其它键合方法(例如引线键合和TAB键合)相比可减小芯片到封装件互连长度，从而得到降低的电感并因此得到改善的高速信号完整性。焊料凸块316可在晶片处理期间被添加到存储器控制器裸片。当存储器控制器306和LGA 330正确地对齐时，焊料凸块316可回流以在存储器控制器306和LGA 330的第一表面338之间生成电连接。底层填料粘合剂可被添加在存储器控制器306和LGA 330之间，以降低焊料凸块316上的应力。
在附图中未示出的其它实施例中，存储器控制器306可用活性表面350背向LGA330的第一表面338被耦接到LGA 330。在这些实施例中，存储器控制器306可经由引线键合线340与存储器裸片312a-h一起通信地耦接到LGA 330。因此，存储器控制器306可包括暴露表面上的引线键合焊盘，用于耦接到引线键合线340。
图4为根据一些实施例的LGA 430的底面的示例性平面图。LGA 430例如可对应于图2中的LGA 230。触点450的阵列可被布置在LGA 430的底面上，用于在NVM封装件(例如NVM封装件204)和各个其它***部件(例如图1中的主机102)之间传导信号。触点450可包括适于与NVM封装件中的一个或多个裸片通信的以下触点：
·Vcc：供电电压(读取)(x4)
·VccQ：供电电压(I/O)(x4)
·Vpp：供电电压(编程/擦除)
·Vref：基准电压
·GND：接地(x6)
·PPM0-PPM1IN：功率控制输入通道0,1
·PPM0-PPM1OUT：功率控制输出通道0,1
·WE0#-WE1#：写使能通道0,1
·CLE0-CLE1：命令锁存使能通道0,1
·ALE0-ALE1：地址锁存使能通道0,1
·RE0-RE1：读使能通道0,1
·RE0#-RE1#：读使能通道0,1
·CE0#-CE7#：芯片使能0-7
·R/B0-R/B1：就绪/忙碌通道0,1
·DQS0-DQS1：数据队列选通通道0,1
·DQS0#-DQS1#：数据队列选通通道0,1
·IO(0-7)-0：数据I/O引脚0-7通道0
·IO(0-7)-1：数据I/O引脚0-7通道1
触点450的阵列可布置为x-y具有从0-8延伸的行(y轴)坐标和用于可布置在阵列边缘处的电力和接地引脚的从OA-OF延伸、以及用于可相对于y-轴在阵列中一般中心地布置的信号引脚的从A-N延伸的列坐标。本领域的技术人员将会知道，引脚坐标系是任意的，并且可使用任何合适的坐标系。
数据I/O引脚(例如IO(0-7)-0和IO(0-7)-1)可被用于将高速数据信号传送到NVM封装件中的一个或多个NVM裸片(例如图1中的存储器裸片112a-n)。特别地，每组数据I/O引脚可代表控制器与NVM裸片(例如图2的存储器裸片212a-h中的一者)之间的8位通信通道。例如，对于上面参考图2所述的原生NAND NVM封装件，控制器可以是主机设备的控制器(例如图1中的主机控制器114)。另一方面，对于上面参考图3所述的被管理NAND NVM封装件，控制器可以是NVM封装件的存储器控制器(例如图3的存储器控制器306)。
在高速应用中，使差分对之间的距离最小化以及减小信号必须行进的总距离可有助于改善数据I/O引脚上的信号完整性。特别地，可要求差分对触点之间的距离小于预先确定的阈值距离。因此，最佳插脚引线设计可减小承载差分对信号的引脚之间的距离以及那些信号行进的总距离。这些目标可通过图4中所示的引脚布置而大体满足。
每个通道的数据I/O引脚可被布置为围绕GND引脚的环形。差分对信号可在环形布局中相邻的数据I/O引脚上被承载。例如，以下引脚可承载通道0的差分对信号：IO0-0和IO3-0；IO1-0和IO2-0；IO4-0和IO7-0；以及IO5-0和IO6-0。这以必要的变更同样适用于通道1的数据I/O引脚。将GND引脚引入在环形数据I/O引脚布局内就可通过降低每个差分对的引脚之间的接地偏移而进一步有助于改善信号完整性。环形布局还可减少对于在NVM封装件内交叉高速信号载体的需求，从而降低了载体之间的串扰，并因此改善信号完整性。
另外的引脚可以是环形数据I/O引脚布局的一部分，包括例如RE0、RE1、RE0#、RE1#、DQS0#、和DQS1#引脚。
数据I/O引脚的环形布局可在y轴上彼此偏移，并且布置在专用于非数据I/O活动的引脚行之间。例如，GND、VccQ、Vcc、PPM0IN、和PPM1IN引脚可布置在沿阵列的顶部边缘和底部边缘的行中，并且环形数据I/O引脚布局可被设置在那些行之间。另外的引脚(包括写使能、芯片使能、地址锁存使能、PPM OUT、和命令锁存使能引脚)可在环形布局之间被布置在对角线行中。
根据一些实施例，专用于每个通道的引脚可关于旋转对称中心点470对称地放置。专用于每个通道的引脚可被布置在通过旋转对称点的中心轴线472的任一侧上。因此，如图4所示，数据I/O引脚IO(0-7)-0可对应于关于旋转对称点反射的数据I/O引脚IO(0-7)-1。类似地，通道0的每个引脚在关于对称轴线反射时映射到通道1的相应引脚。
LGA 430可能对于将信号引导到堆叠式NVM封装件(诸如例如图2的NVM封装件204)的NVM裸片特别有用。因为一半的存储器裸片(即存储器裸片212a-d)可沿第一方向形成阶梯，从而留出更靠近NVM封装件204的第一边缘的暴露表面，所以从触点450中专用于单个通道(例如通道0)并且布置在LGA 430的一部分上(例如更靠近NVM封装件204的第一边缘)的子组引导的信号可以最小信号载体长度被引导到存储器裸片212a-d的键合焊盘。例如，触点450的专用于通道0的第一子组452可被布置在LGA 430的最靠近存储器裸片212a-d的暴露表面的部分上。触点450的专用于通道1的第二子组454可被布置在阵列的相对侧上(例如在中心轴线472的相对侧上)，并且因此最靠近存储器裸片212e-h的暴露表面。因为存储器裸片212e-h可相对于存储器裸片212a-d旋转180°，并且通道0可相对于通道1旋转180°，所以每个通道可利用相同布线布局被引导到相应的一组存储器裸片(通过相互旋转180°)。
图5为根据一些实施例的LGA 530的底面的示例性平面图。LGA 530例如可对应于图2的LGA 230。触点550的阵列可被布置在LGA 530的底面上，用于在NVM封装件(例如NVM封装件204)和各个其它***部件(例如图1的主机102)之间传导信号。触点550可包括适于与NVM封装件中的一个或多个裸片通信的以下触点：
·Vcc：供电电压(读取)(x4)
·VccQ：供电电压(I/O)(x4)
·Vpp：供电电压(编程/擦除)
·Vref：基准电压
·GND：接地(x6)
·PPM0-PPM1IN：功率控制输入通道0,1
·PPM0-PPM1OUT：功率控制输出通道0,1
·WE0#-WE1#：写使能通道0,1
·CLE0-CLE1：命令锁存使能通道0,1
·ALE0-ALE1：地址锁存使能通道0,1
·RE0-RE1：读使能通道0,1
·RE0#-RE1#：读使能通道0,1
·CE0#-CE7#：芯片使能0-7
·R/B0-R/B1：就绪/忙碌通道0,1
·DQS0-DQS1：数据队列选通通道0,1
·DQS0#-DQS1#：数据队列选通通道0,1
·IO(0-7)-0：数据I/O引脚0-7通道0
·IO(0-7)-1：数据I/O引脚0-7通道1
触点550的阵列可被布置为x-y具有从0-8延伸的行(y轴)坐标和用于电力和接地引脚的从OA-OF延伸和用于信号引脚的从A-N延伸的列(x轴)坐标。如图5所示，电力和接地引脚被布置在阵列的边缘处，其被布置在阵列的边缘处，并且信号引脚一般被布置在阵列的中心。本领域的技术人员将会知道，引脚坐标系是任意的，并且可使用任何合适的坐标系。
数据I/O引脚(IO(0-7)-0和IO(0-7)-1)可被用于将高速数据信号传送到NVM封装件中的一个或多个NVM裸片(例如图1的存储器裸片112a-n)。特别地，每组数据I/O引脚可代表控制器与NVM裸片(例如图2中的存储器裸片212a-h中的一者)之间的8位通信通道。例如，对于上面参考图2所述的原生NAND NVM封装件，控制器可以是主机设备的控制器(例如图1的主机控制器114)。另一方面，对于上面参考图3所述的被管理NAND NVM封装件，控制器可以是NVM封装件的存储器控制器(例如图3的存储器控制器306)。
图5中显示的引脚布置可代表用于改善数据I/O引脚上信号完整性的替代实施例。
每个通道的数据I/O引脚可被布置为围绕GND引脚的C形。差分对信号可在C形布局中相邻的数据I/O引脚上被承载。例如，以下引脚可承载通道0的差分对信号：IO0-0和IO1-0；IO2-0和IO3-0；IO4-0和IO5-0；以及IO6-0和IO7-0。这以必要的变更同样适用于通道1的数据I/O引脚。将GND引脚引入在C形数据I/O引脚布局内就可通过降低每个差分对的引脚之间的接地偏移而进一步有助于改善信号完整性。C形布局还可减少对于在NVM封装件内交叉高速信号载体的需求，从而降低载体之间的串扰，并因此改善信号完整性。
另外的引脚可以是C形数据I/O引脚布局的一部分，包括例如RE0、RE1、RE0#、RE1#、DQS0#、和DQS1#引脚。
数据I/O引脚的C形布局可在y轴上位于专用于非数据I/O活动的引脚行之间的正中。例如，GND、VccQ、Vcc、PPM0IN、和PPM1IN引脚可布置在沿阵列的顶部边缘和底部边缘的行中，并且C形数据I/O引脚布局可位于那些行之间的正中。另外的引脚(包括写使能、芯片使能、地址锁存使能、PPM OUT、和命令锁存使能引脚)可被布置在设置于边缘行与C形布局之间的行中。
根据一些实施例，专用于每个通道的引脚可关于y轴取向的对称中心轴线对称地放置。专用于每个通道的引脚可被布置在对称轴线570的任一侧上，使得第二LGA可沿对称轴线旋转颠倒。因此，第二LGA的引脚可与LGA 530的引脚协作。因此，如图5所示，数据I/O引脚IO(0-7)-0可对应于关于对称轴线反射的数据I/O引脚IO(0-7)-1。类似地，通道0的每个引脚在关于对称轴线反射时映射到通道1的相应引脚。
LGA 530可与堆叠式NVM封装件(诸如例如图2的NVM封装件204)一起使用。如上所述，专用于通道0并且布置在对称轴线570的一侧上的触点550的第一子组552可以最小信号载体距离被引导，以将第一子组552与例如存储器裸片212a-d的暴露表面上的键合焊盘通信地耦接。类似地，专用于通道1并且布置在对称轴线570的另一侧上的触点第二子组554可以最小信号载体距离被引导，以将子组554与存储器裸片212e-h的暴露表面上的键合焊盘通信地耦接。因为触点550可能不是关于点旋转对称的，所以对于每个通道可能需要改变NVM封装件204内的布线，以考虑存储器裸片212a-d相对于存储器裸片212e-h旋转180°。
图6为根据一些实施例的用于制造堆叠式半导体存储器设备的方法600的流程图。在步骤601，可提供IC封装基板(例如图2中的LGA230)。LGA的底表面可包括用于将LGA与***基板(例如图2中的基板234)通信耦接的触点阵列。触点阵列可例如被布置为如上文参考图4和5所述的那样。因此，第一通信通道可被设置在LGA的底表面的第一部分上，并且第二通信通道可被设置在LGA的底表面的第二部分上。另外，LGA可包括用于将LGA的底表面上的触点引导到LGA的顶表面上的导电特征部(例如键合焊盘)的任何合适的通路和/或迹线。
然后，在步骤603，存储器控制器(例如图3的存储器控制器306)可任选地被物理耦接到LGA。在一些实施例中，存储器控制器可以倒装芯片构型被耦接到封装基板。在这些实施例中，存储器控制器的活性表面可包括允许存储器控制器和LGA之间直接连接的多个焊料凸块。在其它实施例中，存储器控制器可被引线键合到设置于LGA的第一表面上的键合焊盘。在另外的实施例中，存储器控制器可完全被省略，使得堆叠式半导体存储器设备是原生NVM设备。
在步骤605，NVM裸片(例如存储器裸片212a-h)的叠层可利用适当的粘合剂以箭头形构型被耦接到LGA的顶表面或存储器控制器。在一些实施例中，可在每个存储器裸片之间引入环氧树脂。叠层然后可被布置到箭头形叠层中。最后，环氧树脂可被固化以固化存储器裸片的叠层。存储器裸片212a-h的叠层然后可利用任何合适的方法被附接到LGA 230。根据一些实施例，存储器裸片212a-c的叠层可在叠层自身正被形成的同时用环氧树脂粘合到LGA 230。
任意数量的NVM裸片可被包括在叠层中，这受制于空间、布线、和/或结构限制。每个NVM裸片可用合适的粘合剂被物理地耦接到相邻裸片，并且裸片可被布置为使得第一一半的NVM裸片沿第一方向形成阶梯，并且第二一半的NVM裸片旋转180°并沿第二方向形成阶梯。所得到的箭头形叠层可在每个NVM裸片上提供暴露表面，在暴露表面上可设置键合焊盘。可使用任何合适的用于沉积和从表面移除导电材料的技术来提供键合焊盘。
在步骤607，设置在第一一半箭头形叠层中的NVM裸片边缘上的键合焊盘可电耦接到与第一通信通道相关联的LGA的触点的第一子组(例如图5的第一子组552)。在一些实施例中，引线键合线可被用于这个目的，如上面参考图2所述。类似地，在步骤609，设置在第二一半箭头形叠层中的NVM裸片边缘上的键合焊盘可电耦接到与第二通信通道相关联的LGA的触点的第二子组(例如图5的子组554)。
然后，在步骤611，EMI屏蔽罩(例如图3的EMI屏蔽罩336)可任选地被耦接到堆叠式半导体存储器封装件。EMI屏蔽罩可以是空罐型EMI屏蔽罩，其可覆盖堆叠式半导体存储器封装件的全部或部分。在一些实施例中，EMI屏蔽罩与存储器设备的部件之间的空间可被填充以电介质材料。在其他实施例中，传导性薄膜可被沉积在电介质材料上以形成EMI屏蔽罩。为了消散电荷，EMI屏蔽罩可被引线连接到地面(例如附近电路板上的接地引脚)。
应当理解，图6的方法600中所示的步骤仅仅是例示性的，以及可以修改或省略现有步骤，可以增加额外的步骤，并可以改变某些步骤的顺序。
尽管已经描述了用于堆叠式半导体存储器设备的***和方法，但应当理解，可在不脱离本发明实质和范围的情况下对其做出很多变更。本领域普通技术人员视为要求保护的主题的非实质变更，无论是现在已知的还是以后设计的，都被明确考虑为等同地在权利要求的范围之内。因此，本领域普通技术人员现在或以后所知的明显置换被定义为在所定义元件的范围之内。
本发明提供的所述实施例是出于示例性目的，而不是为了限制。

Claims (17)

1.一种集成电路IC封装基板，包括具有触点阵列的底表面，所述触点阵列包括多个数据I/O触点，其中：
所述多个数据I/O触点的第一子组形成布置在所述底表面的第一部分上的第一C形布局；
所述多个数据I/O触点的第二子组形成布置在所述底表面的第二部分上的第二C形布局；并且
所述第一部分和所述第二部分关于中心轴线反射对称。
2.根据权利要求1所述的IC封装基板，所述触点阵列还包括多个接地GND触点，其中所述多个GND触点中的至少一个GND触点被所述多个数据I/O触点的所述第一子组和所述第二子组中的每一者的所述数据I/O触点围绕。
3.根据权利要求1所述的IC封装基板，所述触点阵列还包括多个数据队列选通DQS触点，其中所述多个DQS触点中的至少一个DQS触点被所述多个数据I/O触点的所述第一子组和所述第二子组中的每一者的所述数据I/O触点围绕。
4.根据权利要求1所述的IC封装基板，其中所述多个数据I/O触点的所述第一子组包括第一通信通道，并且所述多个数据I/O触点的所述第二子组包括第二通信通道。
5.根据权利要求4所述的IC封装，所述触点阵列还包括多个芯片使能CE触点，其中所述多个CE触点的第一子组与所述多个CE触点的第二子组关于所述对称轴线反射对称。
6.根据权利要求5所述的IC封装，其中所述CE触点的所述第一子组使第一组存储器裸片能够进行以下中的至少一者：经由所述第一通信通道发送信号和接收信号，并且其中所述CE触点的所述第二子组使第二组存储器裸片能够进行以下中的至少一者：经由所述第二通信通道发送信号和接收信号。
7.根据权利要求1所述的IC封装，所述触点阵列还包括在所述触点阵列的边缘处布置在平行轴线中的多个供电电压Vcc触点和GND触点，其中所述第一C形布局和所述第二C形布局在所述平行轴线之间居中。
8.一种集成电路IC封装基板，包括具有触点阵列的底表面，所述触点阵列包括多个数据I/O触点，其中：
所述多个数据I/O触点的第一子组形成布置在所述底表面的第一侧上的第一C形布局；
所述多个数据I/O触点的第二子组形成布置在所述底表面的第二侧上的第二C形布局；并且
所述第一侧和所述第二侧关于中心轴线反射对称，其中所述触点阵列还包括多个接地GND触点，其中所述多个GND触点中的仅两个GND触点被所述多个数据I/O触点的所述第一子组和所述第二子组的所述数据I/O触点围绕。
9.根据权利要求8所述的IC封装基板，所述触点阵列还包括多个数据队列选通DQS触点，其中所述多个DQS触点中的至少一个DQS触点被所述多个数据I/O触点的所述第一子组和所述第二子组中的每一者的所述数据I/O触点围绕。
10.根据权利要求8所述的IC封装基板，其中所述多个数据I/O触点的所述第一子组包括第一通信通道，并且所述多个数据I/O触点的所述第二子组包括第二通信通道。
11.根据权利要求8所述的IC封装基板，所述触点阵列还包括在所述第一C形布局和所述第二C形布局之间布置在两个平行对角线轴线中的多个写使能WE触点。
12.根据权利要求8所述的IC封装基板，其中所述WE触点的第一子组被布置在所述两个平行对角线轴线中邻近所述第一C形布局的第一平行对角线轴线中，并且其中所述WE触点的第二子组被布置在所述两个平行对角线轴线中邻近所述第二C形布局的第二平行对角线轴线中。
13.根据权利要求12所述的IC封装基板，其中在关于位于所述中心轴线上的对称点旋转180°时，所述WE触点的所述第一子组映射到所述多个WE触点的所述第二子组的对应的WE触点上。
14.一种半导体封装件，包括：
集成电路IC封装基板，包括形成在所述集成电路IC封装基板的底表面上的多个导电触点，其中所述多个导电触点还包括多个数据I/O触点和多个接地GND触点，其中所述多个GND触点中的仅两个GND触点被与所述多个导电触点的子组的第一C形布局和第二C形布局中的相应的一个相关联的数据I/O触点围绕。
15.根据权利要求14所述的半导体封装件，其中所述仅两个GND触点中的第一GND触点与所述第一C形布局相关联，并且其中所述仅两个GND触点中的第二GND触点与所述第二C形布局相关联。
16.根据权利要求14所述的半导体封装件，其中：
对应于第一通信通道的所述第一C形布局被布置在所述IC封装基板的所述底表面的第一侧上；并且
对应于第二通信通道的所述第二C形布局被布置在所述IC封装基板的所述底表面的第二侧上。
17.根据权利要求14所述的半导体封装件，其中所述IC封装基板包括矩栅阵列(“LGA”)、球栅阵列(“BGA”)、和针栅阵列(“PGA”)中的一者。
CN201711370619.1A 2013-03-13 2013-12-19 堆叠式存储器封装件、其制造方法和ic封装基板 Active CN107978585B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/801,722 2013-03-13
US13/801,722 US9087846B2 (en) 2013-03-13 2013-03-13 Systems and methods for high-speed, low-profile memory packages and pinout designs
CN201380074494.1A CN105074918B (zh) 2013-03-13 2013-12-19 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201380074494.1A Division CN105074918B (zh) 2013-03-13 2013-12-19 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计

Publications (2)

Publication Number Publication Date
CN107978585A CN107978585A (zh) 2018-05-01
CN107978585B true CN107978585B (zh) 2020-05-26

Family

ID=50030447

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201380074494.1A Active CN105074918B (zh) 2013-03-13 2013-12-19 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计
CN201711370619.1A Active CN107978585B (zh) 2013-03-13 2013-12-19 堆叠式存储器封装件、其制造方法和ic封装基板

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201380074494.1A Active CN105074918B (zh) 2013-03-13 2013-12-19 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计

Country Status (7)

Country Link
US (4) US9087846B2 (zh)
EP (1) EP2973698B1 (zh)
JP (2) JP6081655B2 (zh)
KR (2) KR101893318B1 (zh)
CN (2) CN105074918B (zh)
TW (2) TWI518912B (zh)
WO (1) WO2014163687A1 (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008131058A2 (en) * 2007-04-17 2008-10-30 Rambus Inc. Hybrid volatile and non-volatile memory device
KR102276477B1 (ko) * 2014-11-19 2021-07-13 에스케이하이닉스 주식회사 오버행부를 갖는 반도체 패키의 제조방법
US9627367B2 (en) 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
US9824978B2 (en) * 2015-07-31 2017-11-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Connection patterns for high-density device packaging
US20200066640A1 (en) * 2015-12-26 2020-02-27 Intel Corporation Hybrid technology 3-d die stacking
US9875993B2 (en) 2016-01-14 2018-01-23 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
US20200066676A1 (en) * 2016-02-05 2020-02-27 Hewlett Packard Enterprise Development Lp Dual in-line memory module
KR102440182B1 (ko) * 2016-04-11 2022-09-06 에스케이하이닉스 주식회사 칩인에이블 패드를 선택할 수 있는 반도체 패키지
JP6839395B2 (ja) * 2016-05-30 2021-03-10 国立研究開発法人産業技術総合研究所 半導体演算装置
US10381327B2 (en) * 2016-10-06 2019-08-13 Sandisk Technologies Llc Non-volatile memory system with wide I/O memory die
US20180122777A1 (en) * 2016-10-31 2018-05-03 Raytheon Company Hybrid micro-circuit device with stacked chip components
JP2018082110A (ja) * 2016-11-18 2018-05-24 東芝メモリ株式会社 回路基板および電子機器
KR20180064734A (ko) 2016-12-06 2018-06-15 삼성전자주식회사 반도체 메모리 장치 및 이를 구비하는 메모리 모듈
US10497669B2 (en) 2016-12-21 2019-12-03 Intel Corporation Hybrid die stacking
US10607977B2 (en) 2017-01-20 2020-03-31 Google Llc Integrated DRAM with low-voltage swing I/O
US11397687B2 (en) * 2017-01-25 2022-07-26 Samsung Electronics Co., Ltd. Flash-integrated high bandwidth memory appliance
KR20180099266A (ko) * 2017-02-28 2018-09-05 삼성전자주식회사 데이터 저장 장치, 그의 동작 방법 및 그를 포함하는 전자 시스템
JP6709180B2 (ja) * 2017-02-28 2020-06-10 キオクシア株式会社 メモリシステムおよび制御方法
US10358089B2 (en) * 2017-03-28 2019-07-23 GM Global Technology Operations LLC Method and apparatus for triggering hitch view
US10553259B2 (en) * 2017-08-23 2020-02-04 Micron Technology, Inc. Semiconductor dies supporting multiple packaging configurations and associated methods
CN109509736A (zh) * 2017-09-14 2019-03-22 晨星半导体股份有限公司 电路板及芯片封装体
KR102540050B1 (ko) 2018-07-05 2023-06-05 삼성전자주식회사 반도체 패키지
KR102605145B1 (ko) * 2018-07-13 2023-11-24 에스케이하이닉스 주식회사 복수의 채널로 동작하는 복수의 다이를 포함하는 반도체 장치
JP2020043258A (ja) * 2018-09-12 2020-03-19 キオクシア株式会社 半導体メモリおよびその製造方法
CN110323176B (zh) * 2019-05-29 2021-10-22 宁波芯健半导体有限公司 一种芯片的三维封装方法及封装结构
US11081468B2 (en) * 2019-08-28 2021-08-03 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses
CN110534494B (zh) * 2019-09-06 2020-11-06 深圳市安信达存储技术有限公司 一种bga芯片引脚二次排列封装方法及封装结构
US11171109B2 (en) * 2019-09-23 2021-11-09 Micron Technology, Inc. Techniques for forming semiconductor device packages and related packages, intermediate products, and methods
KR20210097406A (ko) 2020-01-30 2021-08-09 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11569259B2 (en) 2020-08-05 2023-01-31 Sandisk Technologies Llc Three-dimensional memory device with double-sided stepped surfaces and method of making thereof
US11631660B2 (en) 2020-08-24 2023-04-18 Samsung Electronics Co., Ltd. Semiconductor package
CN114121873A (zh) 2020-08-25 2022-03-01 美光科技公司 具有球栅阵列的设备和***及相关微电子装置和装置封装
JP2022049485A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体記憶装置
TWI763337B (zh) * 2021-02-26 2022-05-01 瑞昱半導體股份有限公司 封裝載板及應用其的晶片封裝結構
CN116113137A (zh) * 2021-11-10 2023-05-12 华为技术有限公司 一种电路板封装结构、电路板组件以及电子设备

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323559B1 (en) * 1998-06-23 2001-11-27 Lsi Logic Corporation Hexagonal arrangements of bump pads in flip-chip integrated circuits
TW498530B (en) 2001-08-29 2002-08-11 Via Tech Inc Flip-chip pad and redistribution layer arrangement
US6870273B2 (en) * 2002-04-29 2005-03-22 Pmc-Sierra, Inc. High speed I/O pad and pad/cell interconnection for flip chips
JP2007066922A (ja) * 2003-11-28 2007-03-15 Renesas Technology Corp 半導体集積回路装置
JP3896112B2 (ja) * 2003-12-25 2007-03-22 エルピーダメモリ株式会社 半導体集積回路装置
GB2422963B (en) 2005-02-02 2008-01-30 Samsung Electronics Co Ltd Printed wires arrangment for in-line memory (IMM) module
JP5096730B2 (ja) * 2006-11-13 2012-12-12 ルネサスエレクトロニクス株式会社 半導体装置
KR101660430B1 (ko) 2009-08-14 2016-09-27 삼성전자 주식회사 반도체 패키지
WO2010100682A1 (ja) * 2009-03-03 2010-09-10 パナソニック株式会社 半導体集積回路装置
US8097956B2 (en) * 2009-03-12 2012-01-17 Apple Inc. Flexible packaging for chip-on-chip and package-on-package technologies
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
WO2011085131A2 (en) 2010-01-06 2011-07-14 Ching-Hsiang Simon Huang Expandable capacity solid state drive
JP2011171480A (ja) * 2010-02-18 2011-09-01 Elpida Memory Inc 半導体装置
KR20110137565A (ko) 2010-06-17 2011-12-23 삼성전자주식회사 반도체 칩 패키지 및 반도체 칩 패키지의 제조 방법
US8338948B2 (en) * 2010-06-30 2012-12-25 International Business Machines Corporation Ball grid array with improved single-ended and differential signal performance
KR20120131530A (ko) 2011-05-25 2012-12-05 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR101909203B1 (ko) 2011-07-21 2018-10-17 삼성전자 주식회사 멀티-채널 패키지 및 그 패키지를 포함한 전자 시스템
KR101774938B1 (ko) 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
US8345441B1 (en) 2011-10-03 2013-01-01 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows

Also Published As

Publication number Publication date
EP2973698B1 (en) 2023-02-22
US20170005056A1 (en) 2017-01-05
KR101893318B1 (ko) 2018-08-29
CN105074918B (zh) 2017-12-26
TWI518912B (zh) 2016-01-21
US9466571B2 (en) 2016-10-11
JP2016512391A (ja) 2016-04-25
TW201436167A (zh) 2014-09-16
KR20150122724A (ko) 2015-11-02
US20140264906A1 (en) 2014-09-18
JP6081655B2 (ja) 2017-02-15
KR101774415B1 (ko) 2017-09-04
US20170162546A1 (en) 2017-06-08
KR20170102376A (ko) 2017-09-08
WO2014163687A1 (en) 2014-10-09
JP2017092491A (ja) 2017-05-25
TWI619227B (zh) 2018-03-21
CN105074918A (zh) 2015-11-18
TW201440221A (zh) 2014-10-16
JP6343359B2 (ja) 2018-06-13
EP2973698A1 (en) 2016-01-20
US20150325560A1 (en) 2015-11-12
US9853016B2 (en) 2017-12-26
US9583452B2 (en) 2017-02-28
US9087846B2 (en) 2015-07-21
CN107978585A (zh) 2018-05-01

Similar Documents

Publication Publication Date Title
CN107978585B (zh) 堆叠式存储器封装件、其制造方法和ic封装基板
US8643175B2 (en) Multi-channel package and electronic system including the same
US8791554B2 (en) Substrates for semiconductor devices including internal shielding structures and semiconductor devices including the substrates
US8218346B2 (en) Multi-chip packages including extra memory chips to define additional logical packages and related devices
US10593617B2 (en) Semiconductor device
US10128191B2 (en) Package-on-package type package including integrated circuit devices and associated passive components on different levels
US11355485B2 (en) Semiconductor die and semiconductor package
TWI520279B (zh) 用於固態硬碟（ｓｓｄ）應用，不同密度組態及直接反及閘（ｎａｎｄ）存取之統一印刷電路板（ｐｃｂ）設計
KR20160014475A (ko) 스택 패키지
US10028380B2 (en) Semiconductor package with dual second level electrical interconnections
US20240063135A1 (en) Flexible interposer for semiconductor dies
US20240128182A1 (en) Dielectric interposer with electrical-connection cut-in

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant