CN107978557B - Method for manufacturing vacuum gap in etching groove - Google Patents
Method for manufacturing vacuum gap in etching groove Download PDFInfo
- Publication number
- CN107978557B CN107978557B CN201711184301.4A CN201711184301A CN107978557B CN 107978557 B CN107978557 B CN 107978557B CN 201711184301 A CN201711184301 A CN 201711184301A CN 107978557 B CN107978557 B CN 107978557B
- Authority
- CN
- China
- Prior art keywords
- oxide layer
- vacuum gap
- layer
- etching groove
- hydrofluoric acid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052802 copper Inorganic materials 0.000 claims abstract description 24
- 239000010949 copper Substances 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000004020 conductor Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000005086 pumping Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 230000036962 time dependent Effects 0.000 abstract description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 229910004014 SiF4 Inorganic materials 0.000 description 3
- -1 ammonium fluorosilicate Chemical compound 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910019975 (NH4)2SiF6 Inorganic materials 0.000 description 1
- 229910020439 SiO2+4HF Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
The invention relates to a method for manufacturing a vacuum gap in an etching groove, which comprises the following steps: introducing hydrofluoric acid and ammonia gas into the etching groove, and removing the first oxide layer in the etching groove by controlling the concentration and the introduction rate of the introduced hydrofluoric acid and ammonia gas; and forming a linear second oxide layer at the top of the etching groove and forming a vacuum gap. According to the method for manufacturing the vacuum gap in the etching groove, the vacuum gap is manufactured among the metal copper, and the vacuum has the lowest dielectric constant, so that the capacitance among the copper layers can be greatly reduced, the leakage current phenomenon is reduced, the time-dependent dielectric breakdown characteristic is improved, and the performance of a device is improved. In addition, the invention does not adopt a plasma etching process when removing the oxide, so that the nitride layer can be well reserved while the oxide layer is eliminated, and the window formed by a new oxide layer is improved.
Description
Technical Field
The invention relates to a method for manufacturing a vacuum gap in an etching groove, and relates to the technical field of 3D NAND memory manufacturing.
Background
With the development of semiconductor technology, various semiconductor memory devices have been proposed. Semiconductor memory devices have advantages of fast access speed, high memory density, and the like, compared to conventional memory devices such as magnetic memory devices. Among these, the NAND structure is receiving more and more attention. To further increase memory density, a variety of three-dimensional (3D) NAND devices have emerged.
Fig. 1A-1F are schematic diagrams illustrating a process of forming a 3D NAND etched trench in the prior art. The method specifically comprises the following steps:
(1) as shown in fig. 1A, a standard film structure (film structure) is obtained after exposure on the basis of the initial structure, and includes a photoresist 1, a silicon oxynitride layer 2(SiON), an oxide layer 3, a tungsten layer 5, and a silicon carbonitride layer 4(SiCN) in this order from top to bottom.
(2) As shown in fig. 1B, the photoresist 1, the silicon oxynitride layer 2(SiON), and a part of the oxide layer 3 are removed by dry/wet etching, thereby exposing the tungsten layer 5.
(3) As shown in fig. 1C, a nitride layer 6 is deposited over the structure of step (2) by atomic layer deposition technique (ALD).
(4) As shown in fig. 1D, the nitride layer 6 on the oxide layer 3 and the nitride layer 6 on the tungsten layer 5 are removed by dry etching, but the nitride layer 6 on the side wall of the oxide layer 3 remains.
(5) As shown in fig. 1E, the structure obtained in step (4) is completely covered with metallic copper by Electroplating (ECP), forming a copper layer 7.
(6) As shown in fig. 1F, the top layer of copper metal is removed by Chemical Mechanical Polishing (CMP) until the top surfaces of the nitride layer 6 and the oxide layer 3 are exposed. Thus, through a plurality of steps, the etching groove structure can be finally obtained.
The following drawbacks exist during the above process: since the electroplating process can cause metal copper to diffuse in the nitride layer 6 and the oxide layer 3, the insulating property between every two copper layers 7 is affected, and current breaks down between the two copper layers 7 to form leakage current, so that the device performance is affected.
Disclosure of Invention
In order to solve the above technical problems, the present invention is directed to a method for manufacturing a vacuum gap in an etching trench, which is used to replace the isolation function of an oxide layer by manufacturing a vacuum gap in an etching trench structure, thereby solving the problem of copper diffusion and the problem of electrical leakage.
According to an aspect of the present invention, there is provided a method of manufacturing a vacuum gap in an etching bath, comprising the steps of:
introducing hydrofluoric acid and ammonia gas into the etching groove, and removing the first oxide layer in the etching groove by controlling the concentration and the introduction rate of the introduced hydrofluoric acid and ammonia gas;
and forming a linear second oxide layer at the top of the etching groove and forming a vacuum gap.
Preferably, the etching groove comprises a silicon nitride layer positioned at the bottom and a first oxide layer positioned above the silicon nitride layer, a plurality of conducting channels are distributed in the silicon nitride layer and the first oxide layer at intervals, the bottom of each conducting channel is provided with a conductor layer made of conducting materials, a copper layer is arranged on the conductor layer, and a nitride layer is arranged between the copper layer and the first oxide layer.
More preferably, the nitride layer is made of silicon nitride.
More preferably, the conductor layer is made of a conductive material.
Preferably, the conductive material comprises one or more of tungsten, cobalt, copper, aluminum and silicide.
Preferably, the first oxide layer is silicon dioxide.
Preferably, the second oxide layer is made of silicon dioxide.
Preferably, the hydrofluoric acid and the ammonia react with the first oxide layer to generate ammonium fluorosilicate and water, and the ammonium fluorosilicate and the water are pumped by the pumping equipment and discharged.
Preferably, the second oxide layer is formed by directly covering the prepared linear oxide on the top of the etching groove or by a slow-deposition film deposition process.
According to another aspect of the present invention, there is also provided a 3D NAND memory comprising etched trenches fabricated according to the above method.
The novel method for manufacturing the vacuum gap in the etching groove of the invention manufactures the vacuum gap between the metal copper, and the vacuum has the lowest dielectric constant, so the method can greatly reduce the capacitance between the copper layers, reduce the leakage current phenomenon, improve the time-dependent dielectric breakdown characteristic and further improve the performance of the device. In addition, the invention does not adopt a plasma etching process when removing the oxide, so that the nitride layer can be well reserved while the oxide layer is eliminated, and the window formed by a new oxide layer is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIGS. 1A-1F are schematic diagrams of a prior art process for creating a vacuum gap in an etched trench;
FIGS. 2A-2B are schematic views of a process for forming a vacuum gap in an etch trench in accordance with the present invention;
FIG. 3 shows the elimination of an oxide layer (SiO) using hydrofluoric acid and ammonia gas according to the present invention2) Schematic diagram of the principle of (1).
Detailed Description
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout the specification.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being "on," "connected to" or "coupled to" another element, it can be directly on or connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between," "adjacent" with respect to "directly adjacent," etc.). When an element is referred to herein as being "on" or "under" another element, it can be directly coupled to the other element, or intervening elements may be present, or the elements may be separated by gaps or spaces.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The method for manufacturing the vacuum gap in the etching groove of the embodiment of the invention is applied to the current common etching groove structure. As shown in fig. 1F, the etching groove includes a silicon nitride carbide layer 4 at the bottom and a first oxide layer 3 on the silicon nitride carbide layer 4, a plurality of conductive channels are distributed at intervals in the silicon nitride carbide layer 4 and the first oxide layer 3, the bottom of the conductive channels is provided with a conductor layer 5 formed by a conductive material, the conductor layer 5 is provided with a copper layer 7, and a nitride layer 6 is arranged between the copper layer 7 and the first oxide layer 3. The nitride layer 6 may be made of silicon nitride.
In some embodiments, the conductor layer 5 in the etched trenches may be made of a conductive material, including but not limited to one or a combination of tungsten, cobalt, copper, aluminum, and silicide.
The process of manufacturing a vacuum gap in an etching tank according to an embodiment of the present invention is shown in fig. 2A-2B, and includes the following steps:
s1, as shown in fig. 2A, hydrofluoric acid and ammonia gas are introduced, and the first oxide layer (i.e., the oxide layer 3 in fig. 1A to 1F) in the etching trench is removed by controlling the concentration and the introduction rate of the introduced hydrofluoric acid and ammonia gas.
In this step the first oxide layer is removed and the nitride layer 6 is retained. Thus, a wider window is provided for the next step of forming a new oxide layer to cover.
In some embodiments, the first oxide layer is silicon dioxide. In some embodiments, the concentration of hydrofluoric acid is 1:500 (HF: H) by mass2O), the time of passage is from 1 to 5 minutes. And in the time of the buffer etching period, by controlling the dosage and the injection speed of hydrofluoric acid and ammonia gas, introducing the hydrofluoric acid and the ammonia gas into the surface of the first oxide layer to perform chemical reaction. In this process, the following chemical reaction processes occur gradually on the surface of the silica: SiO 22+4HF＝SiF4+2H2O、SiO2+4HF+4NH3＝SiF4+2H2O+4NH3、 SiF4+2HF+2NH3＝(NH4)2SiF6. Finally, a solid-liquid mixture of ammonium fluorosilicate and water is produced. During the reaction, the solid-liquid mixture formed by the reaction is pumped away and discharged by a pumping device (such as a common vacuum pumping device) from time to time, and the process is repeated until the first oxide layer formed by the silicon dioxide is gradually corroded and disappears. In this process, since the nitride layer 6 does not chemically react with hydrofluoric acid or ammonia gas, it remains.
Because the ammonium fluosilicate generated by the reaction is quickly pumped away by a vacuum pumping device and the concentration of the hydrofluoric acid used by the method is low, the hydrofluoric acid etching process can easily remove the redundant oxide without damaging the nitride layer 6 which needs to be remained. The invention does not adopt the plasma etching process when removing the oxide, thereby well retaining the nitride layer while eliminating the oxide layer, and further improving the window formed by the new oxide layer.
S2, as shown in fig. 2B, the top of the etched trench is covered with the second oxide layer 8. The second oxide layer 8 is linear and extends continuously in the horizontal direction. The second oxide layer 8 is made of silicon dioxide.
In some embodiments, the second oxide layer 8 may be formed by directly covering the top of the etched trench with a prepared linear oxide, and then the space formed after the original first oxide layer 3 is etched is evacuated to form the vacuum gap 9. In other embodiments, the second oxide layer 8 may also be formed by a slow-deposition thin film deposition process including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and/or other suitable methods.
In this way, a vacuum gap 9 is formed between the metallic copper layers 7 of the etched trench. Because the vacuum has the lowest dielectric constant, the invention can greatly reduce the capacitance between copper layers, reduce the leakage current phenomenon, improve the time-dependent dielectric breakdown characteristic and further improve the device performance.
The novel method for manufacturing the vacuum gap in the etching groove of the invention manufactures the vacuum gap between the metal copper, and the vacuum has the lowest dielectric constant, so the method can greatly reduce the capacitance between the copper layers, reduce the leakage current phenomenon, improve the time-dependent dielectric breakdown characteristic and further improve the performance of the device. In addition, the invention does not adopt a plasma etching process when removing the oxide, so that the nitride layer can be well reserved while the oxide layer is eliminated, and the window for depositing a new oxide layer is improved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. A method of forming a vacuum gap in an etch chamber, comprising the steps of:
introducing hydrofluoric acid and ammonia gas into the etching groove, removing the first oxide layer in the etching groove by controlling the concentration and the introduction rate of the introduced hydrofluoric acid and ammonia gas, reacting the hydrofluoric acid and ammonia gas with the first oxide layer to generate a solid-liquid mixture of ammonium fluosilicate and water, and pumping the solid-liquid mixture generated by the reaction away by extraction equipment in the reaction process; the etching groove comprises a silicon carbonitride layer positioned at the bottom and a first oxide layer positioned above the silicon carbonitride layer, a plurality of conductive channels are distributed in the silicon carbonitride layer and the first oxide layer at intervals, the bottoms of the conductive channels are provided with conductor layers made of conductive materials, copper layers are arranged on the conductor layers, and nitride layers are arranged between the copper layers and the first oxide layer;
forming a linear second oxide layer on the top of the etching groove and forming a vacuum gap; the second oxide layer is formed by directly covering the prepared linear oxide on the top of the etching groove or by a slow-deposition film deposition process.
2. A method of fabricating a vacuum gap in an etched trench as claimed in claim 1, wherein:
the nitride layer is made of silicon nitride.
3. A method of fabricating a vacuum gap in an etched trench as claimed in claim 1, wherein:
the conductor layer is made of a conductive material.
4. A method of fabricating a vacuum gap in an etched trench as claimed in claim 3, wherein:
the conductive material comprises one or more of tungsten, cobalt, copper, aluminum and silicide.
5. A method of fabricating a vacuum gap in an etched trench as claimed in claim 1, wherein:
the first oxide layer is silicon dioxide.
6. A method of fabricating a vacuum gap in an etched trench as claimed in claim 1, wherein:
the second oxide layer is made of silicon dioxide.
7. A 3D NAND memory characterized in that it comprises etched trenches manufactured according to the method of any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711184301.4A CN107978557B (en) | 2017-11-23 | 2017-11-23 | Method for manufacturing vacuum gap in etching groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711184301.4A CN107978557B (en) | 2017-11-23 | 2017-11-23 | Method for manufacturing vacuum gap in etching groove |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107978557A CN107978557A (en) | 2018-05-01 |
| CN107978557B true CN107978557B (en) | 2021-05-04 |
Family
ID=62011262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711184301.4A Active CN107978557B (en) | 2017-11-23 | 2017-11-23 | Method for manufacturing vacuum gap in etching groove |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107978557B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050012219A1 (en) * | 2003-07-16 | 2005-01-20 | Huey-Chiang Liou | Air gap integration |
| CN101506955A (en) * | 2006-09-21 | 2009-08-12 | 英特尔公司 | Dielectric spacers for metal interconnects and method to form the same |
| US20160307773A1 (en) * | 2015-04-15 | 2016-10-20 | Samsung Electronics Co., Ltd. | Method of Manufacturing Semiconductor Devices |
-
2017
- 2017-11-23 CN CN201711184301.4A patent/CN107978557B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050012219A1 (en) * | 2003-07-16 | 2005-01-20 | Huey-Chiang Liou | Air gap integration |
| CN101506955A (en) * | 2006-09-21 | 2009-08-12 | 英特尔公司 | Dielectric spacers for metal interconnects and method to form the same |
| US20160307773A1 (en) * | 2015-04-15 | 2016-10-20 | Samsung Electronics Co., Ltd. | Method of Manufacturing Semiconductor Devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107978557A (en) | 2018-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20030057184A1 (en) | Method for pull back SiN to increase rounding effect in a shallow trench isolation process | |
| CN107863323B (en) | Method for forming semiconductor device | |
| CN101438389A (en) | Recessed workfunction metal in CMOS transistor gates | |
| KR20200055797A (en) | Multi-layer stacks for 3D NAND scalability | |
| US9754799B2 (en) | Fabrication method of interconnect structure | |
| CN102148191B (en) | Formation method for contact hole | |
| CN105448814A (en) | Method of forming semiconductor structure | |
| US20230320063A1 (en) | Memory device, semiconductor structure and method for manufacturing semiconductor structure | |
| US20060027875A1 (en) | Semiconductor device with gate space of positive slope and fabrication method thereof | |
| CN101410966A (en) | Trench isolation structure having an expanded portion thereof | |
| CN107978557B (en) | Method for manufacturing vacuum gap in etching groove | |
| US11848232B2 (en) | Method for Si gap fill by PECVD | |
| KR101767538B1 (en) | Metal-containing films as dielectric capping barrier for advanced interconnects | |
| US6974749B2 (en) | Bottom oxide formation process for preventing formation of voids in trench | |
| CN107527858B (en) | Method for fabricating shallow trench in flash memory | |
| CN104979269A (en) | Manufacturing method for semiconductor device | |
| JP2018032722A (en) | Method for manufacturing semiconductor device | |
| JP2005005697A (en) | Manufacturing method of semiconductor device | |
| CN110073467B (en) | Method for providing low-k spacers | |
| JP2005129937A (en) | Low k integrated circuit interconnection structure | |
| CN111029298A (en) | Manufacturing method of copper interconnection layer | |
| CN104392959A (en) | Method for manufacturing dual damascene structure | |
| CN105632909B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN104716085B (en) | A kind of semiconductor devices and its manufacturing method | |
| US9059094B2 (en) | Semiconductor gate structure and method of fabricating thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |