CN107976700A - A kind of stabilization output method of satellite navigation receiver pulse per second (PPS) - Google Patents
A kind of stabilization output method of satellite navigation receiver pulse per second (PPS) Download PDFInfo
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- CN107976700A CN107976700A CN201710966093.7A CN201710966093A CN107976700A CN 107976700 A CN107976700 A CN 107976700A CN 201710966093 A CN201710966093 A CN 201710966093A CN 107976700 A CN107976700 A CN 107976700A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
- G01S19/37—Hardware or software details of the signal processing chain
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- Radar, Positioning & Navigation (AREA)
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- Computer Networks & Wireless Communication (AREA)
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Abstract
The invention discloses a kind of stabilization output method of satellite navigation receiver pulse per second (PPS), FPGA maintains local PPS according to the frequency of local rubidium atomic clock, record the PPS of general-purpose satellite navigation receiver output, the time interval of the PPS and local PPS of the output of TDC measuring receivers;Measurement result is transmitted to DSP by FPGA, and DSP is defined the position of the processing of memory Kalman filtering and real-time estimation preferable second, and the position of preferable second is converted into the control parameter of numerical control delay line in dsp, and exports preferable second parameter by numerical control delay line;FPGA exports configuration parameter according to preferable second parameter, final second output is then adjusted by numerical control delay line, so as to complete the stabilization of pulse per second (PPS).Present system forms and is easier to realize, relatively low suitable for general purpose receiver, cost;Obtained by test, after synchronous 6h, output pulse per second (PPS) precision is better than 3ns(RMS);Using the Kalman filter of restricted memory, the system diverging for effectively inhibiting the non-Gaussian system of model to bring.
Description
Technical field
The invention belongs to atomic clock and Time-Frequency Technology field, and in particular to a kind of general-purpose satellite navigation receiver pulse per second (PPS)
Output method, for improving the stability of receiver output pulse per second (PPS).
Background technology
Satellite navigation system also provides a kind of high-precision time service means while navigator fix is provided.Based on satellite
The time service means of navigation are broadly divided into several sides such as one-way timing, common-view time transmission and two-way satellite time and frequency transfer
Method.
One-way timing refers to known to coordinate(Or coordinate is unknown but can receive more than four satellites)Observation station observation one
Or multi-satellite determine the method for our station clock jitter.Its time service precision mainly with receiver error, satellite ephemeris error,
Satellite clock correction, atmospheric correction error etc. are related.
Its advantages of is that time signal is covering the whole world, and the cost of required receiver is low using simply.But one can only be provided
Determine the time service precision of 100ns under confidential interval, it is difficult to meet the needs of high-precision applications clock.
Precision when common-view time transmission and two-way satellite time and frequency transfer are capable of providing higher pair, but it is substantially
The clock correction at two stations, i.e. time synchronization are obtained, essentially consists in the time contrast realized between a few users, and the cost is relatively high.
The content of the invention
It is an object of the invention to insufficient according to prior art, design is a kind of can be used for general-purpose satellite navigation receiver,
Pulse per second (PPS) antihunt means based on TDC_GPX and restricted memory Kalman filtering.
The technical solution adopted by the present invention to solve the technical problems is:A kind of stabilization of satellite navigation receiver pulse per second (PPS)
Output method, applied to the general-purpose satellite navigation receiver comprising FPGA, DSP and TDC, comprises the following steps:
S1, FPGA maintain local PPS according to the frequency of local rubidium atomic clock, the receiver output of record general-purpose satellite navigation
The time interval of the PPS and local PPS of the output of PPS, TDC measuring receiver;
Measurement result is transmitted to DSP by S2, FPGA, and DSP is defined memory Kalman filtering and handles the simultaneously real-time estimation preferable second
Position, the position of preferable second is converted into the control parameter of numerical control delay line in dsp, and exports ideal by numerical control delay line
Second parameter;
S3, FPGA export configuration parameter according to preferable second parameter, and final second output is then adjusted by numerical control delay line, so that
Complete the stabilization of pulse per second (PPS).
A kind of stabilization output method of satellite navigation receiver pulse per second (PPS), its S1 specifically include the following steps:
11)Electrification reset, using the PPS that the pps pulse per second signal construction of receiver is local in FPGA, the PPS for exporting receiver
Delay is about 5us between local PPS, it is ensured that in the measurement range of TDC, makes its direct measurement result be;
12)With lasting measurement, work as discoveryValue close to 0us either 10us when make local pulse per second (PPS) respectively forward or
After moveOr, to ensure that direct measurement result is maintained in measurement range, whereinFor the clock cycle of FPGA;
13)The measurement result of final output is。
A kind of stabilization output method of satellite navigation receiver pulse per second (PPS), the Kalman of atomic clock clock correction in its S2
The foundation of wave filter discretization model includes the following steps:
21)The time interval of measurement is known as to the clock correction x (t) of atomic clock, second-order model is established as follows to clock correction x (t):;In formulaFor the initial clock correction of atomic clock,For the initial frequency difference of atomic clock,For atom
The linear drift of clock.For the randomness change component of atomic clock clock correction;
Wherein, the frequency difference of atomic clock is expressed as:;
The frequency shift (FS) rate of atomic clock is expressed as:;
22)Three formulas establish the state transfer mould of the Kalman filter discretization of atomic clock clock correction in accordance with the following steps for more than
Type and observation model:
In formulaFor observation interval,Zero-mean Gaussian noise with uncorrelated sample, variance are。
A kind of stabilization output method of satellite navigation receiver pulse per second (PPS), remembers Kalman filter model in its S2
Foundation include the following steps:
31)The state model of restricted memory Kalman filtering is established in accordance with the following steps:
, wherein;
32)Observation model is established in accordance with the following steps:
, wherein;
33)Then according to Kalman's fundamental equation, correction formula can obtain:
And minimum prediction MSE matrixes:
And kalman gain vector:
。
The stabilization output method of a kind of satellite navigation receiver pulse per second (PPS), by the coarse adjustment and numerical control of FPGA in its S3
The output of final pulse per second (PPS) is completed in the accurate adjustment of delay line jointly.
A kind of stabilization output method of satellite navigation receiver pulse per second (PPS), the FPGA use altera corp
EP4CE115F23I7, the TDC uses TDC_GPX chips, and the DSP is using TI companies
TMS320F28335ZJZS, the numerical control delay line use DS1124
The beneficial effects of the invention are as follows:
Present system forms and is easier to realize, relatively low suitable for general-purpose satellite navigation receiver, cost;Obtained by test, together
After walking 6h, output pulse per second (PPS) precision is better than 3ns(RMS);Using the Kalman filter of restricted memory, model is effectively inhibited
The system diverging that non-Gaussian system is brought.
Brief description of the drawings
Fig. 1 is the functional block diagram of the present invention;
Fig. 2 is the software flow pattern of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
With reference to shown in Fig. 1, the invention discloses a kind of pulse per second (PPS) based on TDC_GPX and restricted memory Kalman filtering is steady
Method is determined, applied to including FPGA, DSP and TDC(Time-to-digit converter)General-purpose satellite navigation receiver, this method use
FPGA coordinates the TDC-GPX measuring receivers pulse per second (PPS) of ACAM companies and the time interval of local pulse per second (PPS), is limited in dsp
Surely remember the position of Kalman filtering processing and real-time estimation preferable second, and exported by the numerical control delay line adjustment preferable second, from
And complete the stabilization of pulse per second (PPS).
Specifically include following steps:
S1, FPGA maintain local PPS according to the frequency of local rubidium atomic clock(Pulses per second), record general-purpose satellite navigation and connect
The PPS of receipts machine output, the time interval of the PPS and local PPS of the output of TDC measuring receivers;
Measurement result is transmitted to DSP by S2, FPGA, and DSP is defined memory Kalman filtering and handles the simultaneously real-time estimation preferable second
Position, the position of preferable second is converted into the control parameter of numerical control delay line in dsp, and exports ideal by numerical control delay line
Second parameter;
S3, FPGA export configuration parameter according to preferable second parameter, and final second output is then adjusted by numerical control delay line, so that
Complete the stabilization of pulse per second (PPS).
The FPGA uses the EP4CE115F23I7 chips of altera corp, and the TDC uses TDC_GPX cores
Piece, the DSP use the TMS320F28335ZJZS chips of TI companies, and the numerical control delay line uses DS1124 chips.
The software flow of the present invention is as shown in Figure 2.
Initialization substantially is carried out after FPGA initial power-ons and the local second is synchronous, clock correction measurement result is sent out in the form of interrupting
It is sent in DSP.DSP controls each initialization, receives the interruption of FPGA, reads clock correction data and is defined memory Kalman's filter
Ripple, and the control of crossing the border of TDC is carried out, and control etc. of crossing the border of numerical control delay line.The key content of each several part is carried out below
It is described in detail.
1st, time interval measuring circuit
TDC_GPX be by German ACAM companies produce high precision time interval measurement chip, have high resolution, it is low in energy consumption,
The advantages that small.It is mainly characterized in that:1)It is logical with I patterns, G patterns, R patterns, a variety of resolution ratio of M patterns and measurement
The different measurement pattern in road;2)So that measurement accuracy is very small by the change of ambient temperature, voltage under the action of phaselocked loop;3)
Pattern, expansible measurement range are triggered again with inside.
The highest M-mode measurement accuracy of precision is 10ps, but measurement range only supports 0 ~ 10us, it is therefore desirable to which FPGA is controlled
Trigger pulse processed extends measurement range.Time interval measurement flow is:
11)Electrification reset, using the PPS that the pps pulse per second signal construction of receiver is local in FPGA, the PPS for exporting receiver
Delay is about 5us between local PPS, it is ensured that in the measurement range of TDC_GPX, makes its direct measurement result be。
12)With lasting measurement, work as discoveryValue close to 0us or 10us when, make local pulse per second (PPS) respectively forward
It is or rear mobileOr, to ensure that direct measurement result is maintained in measurement range, whereinFor the clock week of FPGA
Phase.
13)The measurement result of final output is。
2nd, atomic clock model is established
The result of time interval measurement is transferred to progress follow-up data processing in DSP, and core link therein is restricted memory
Kalman filtering algorithm, so as to estimate the position of preferable pulse per second (PPS).
This section first realizes process to atomic clock model modeling, next section explanation restricted memory.
21)The time interval of upper one section measurement gained is known as to the clock correction x (t) of atomic clock, to clock correction x (t) by following step
Suddenly second-order model is established:
;
In formulaFor the initial clock correction of atomic clock,For the initial frequency difference of atomic clock,For the linear drift of atomic clock.
For the randomness change component of atomic clock clock correction;
Then the frequency difference of atomic clock can be expressed as:
;
The frequency shift (FS) rate of atomic clock can be expressed as:
;
22)Three formulas establish the state transfer mould of the Kalman filter discretization of atomic clock clock correction in accordance with the following steps for more than
Type and observation model:
In formulaFor observation interval,Zero-mean Gaussian noise with uncorrelated sample, variance are。
3rd, limited memory filtering
To reduce the influence to filtering such as model error, thinking of the invention is that memory filtedng is defined.Reduce estimation
The weight of middle prediction, increase newly ceases the influence to data, when correcting premeasuring, only considers nearest N number of observation.
According to the content of upper one section, the state model of system is:
, wherein。
Observation model is:
, wherein。
Then according to Kalman's fundamental equation, can obtain
Prediction:
Minimum prediction MSE matrixes:
Kalman gain vector:
Correct:
Minimum MSE matrixes
And assume first to observe 2 ~ N+1 points, then observe at the 1st point, relational expression can be obtained
Two groups of formula can obtain more than
Above recursion flow is in addition to general multiplication and division computing, it is only necessary to calculates the inverse of third-order matrix, realizes in dsp easier.
And since operation frequency only has 1Hz, the requirement to DSP dominant frequency is also than relatively low.
4th, numerical control delay line is exported with the preferable second
The processing more than, if directly exported by FPGA, is limited to system it is estimated that the position of preferable pulse per second (PPS)
Highest frequency, output accuracy are difficult to ensure that.The present invention selects numerical control delay line to make up this defect, adjustment stepping is reached sub-
Ns magnitudes.
DS1124 is 5V, the 8 programmable numerical control delay lines that maxim is released, and device has 3 line serial line interfaces, can cascade
Multiple periods realize that multi-stage programmable postpones.Device has the nominal delay stepping of 0.25ns, and 0 grade of delay is 20ns, and 255
The delay of level is 83.75ns.In industrial temperature range, DS1124 with 3ns integral nonlinearity or as with 0 grade and 255
The maximum deviation value of 2 points of straight lines being linked to be of level.
It is assumed that the controlled quentity controlled variable of final output pulse per second (PPS) is, then by the coarse adjustment of FPGA and the accurate adjustment of numerical control delay line Lai common
Complete the output of final pulse per second (PPS).The cycle is among FPGA, then the adjustment amount of FPGA be, the tune of numerical control delay line
Whole amount is。
5th, estimated accuracy analysis and measured result
According to CRLB theorems, in observed quantity and the combined PD F of estimator(Probability density function)" canonical " condition of satisfactionIn the case of, any unbiased estimatorVariance must meet
In the case of it is assumed that noise is white Gaussian noise, observation signal is
Wherein clearly designate signal pairAccordance with tolerance.Likelihood function is
, wherein N is observation frequency
Derivation obtains
Secondary derivation obtains
Obtained after taking mathematic expectaion
So finally have
The form of lower limit indicates signal dependenceImportance.Signal changes with unknown parameter and changing will produce accurately rapidly
Ground estimator.
Calculated to simplify, only consider that the situation of scalar parameter then has
Then its standard deviation is
It is assumed that it is about 40ns to defend the PPS signal shake led(RMS), preferable stablizing effect is can obtain after 100 points in theory.But
According to inventor's actual measurement as a result, 3ns can be obtained after system stable operation 6h(RMS)Precision, difference among these comes from
The inaccuracy of rubidium clock model, and non-Gaussian noise of the original pulse per second (PPS) of receiver etc..
The above-described embodiments merely illustrate the principles and effects of the present invention, and the embodiment that part uses, for
For those of ordinary skill in the art, without departing from the concept of the premise of the invention, can also make it is some deformation and
Improve, these belong to protection scope of the present invention.
Claims (7)
- A kind of 1. stabilization output method of satellite navigation receiver pulse per second (PPS), it is characterised in that applied to comprising FPGA, DSP and The general-purpose satellite navigation receiver of TDC, comprises the following steps:S1, FPGA maintain local PPS, the PPS of record general-purpose satellite navigation receiver output according to the frequency of local rubidium atomic clock, The time interval of the PPS and local PPS of the output of TDC measuring receivers;Measurement result is transmitted to DSP by S2, FPGA, and DSP is defined memory Kalman filtering and handles the simultaneously real-time estimation preferable second Position, the position of preferable second is converted into the control parameter of numerical control delay line in dsp, and exports ideal by numerical control delay line Second parameter;S3, FPGA export configuration parameter according to preferable second parameter, and final second output is then adjusted by numerical control delay line, so that Complete the stabilization of pulse per second (PPS).
- A kind of 2. stabilization output method of satellite navigation receiver pulse per second (PPS) according to claim 1, it is characterised in that institute The S1 stated specifically includes the following steps:11)FPGA constructs local PPS using the pps pulse per second signal of receiver, between the PPS and local PPS that make receiver output Postpone as 5us, it is ensured that in the measurement range of TDC, make its direct measurement result be;12)With lasting measurement, work as discoveryValue close to 0us either 10us when make local pulse per second (PPS) respectively forward or after It is mobileOr, to ensure that direct measurement result is maintained in measurement range, whereinFor the clock cycle of FPGA;13)The measurement result of final output is。
- A kind of 3. stabilization output method of satellite navigation receiver pulse per second (PPS) according to claim 2, it is characterised in that institute The foundation of the Kalman filter discretization model of atomic clock clock correction includes the following steps in the S2 stated:21)The time interval of measurement is known as to the clock correction x (t) of atomic clock, second-order model is established as follows to clock correction x (t):;In formulaFor the initial clock correction of atomic clock,For the initial frequency difference of atomic clock,For the linear drift of atomic clock.
- 4.For the randomness change component of atomic clock clock correction;Wherein, the frequency difference of atomic clock is expressed as:;The frequency shift (FS) rate of atomic clock is expressed as:;22)Three formulas establish the state transfer mould of the Kalman filter discretization of atomic clock clock correction in accordance with the following steps for more than Type and observation model:In formulaFor observation interval,Zero-mean Gaussian noise with uncorrelated sample, variance are。
- A kind of 5. stabilization output method of satellite navigation receiver pulse per second (PPS) according to claim 3, it is characterised in that institute The foundation that Kalman filter model is remembered in the S2 stated includes the following steps:31)The state model of restricted memory Kalman filtering is established in accordance with the following steps:, wherein;32)Observation model is established in accordance with the following steps:, wherein;33)Then according to Kalman's fundamental equation, correction formula can obtain:;And minimum prediction MSE matrixes:;With kalman gain vector:。
- A kind of 6. stabilization output method of satellite navigation receiver pulse per second (PPS) according to claim 4, it is characterised in that institute The output of final pulse per second (PPS) is completed by the coarse adjustment of FPGA and the accurate adjustment of numerical control delay line jointly in the S3 stated.
- 7. a kind of stabilization output method of satellite navigation receiver pulse per second (PPS) according to claim 1 to 5 any one, its It is characterized in that, the FPGA uses the EP4CE115F23I7 of altera corp, the TDC to use TDC_GPX chips, institute The DSP stated uses the TMS320F28335ZJZS of TI companies, and the numerical control delay line uses DS1124.
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CN115561988A (en) * | 2022-12-06 | 2023-01-03 | 浙江赛思电子科技有限公司 | Time service terminal and time service system and method thereof |
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CN108680930A (en) * | 2018-05-17 | 2018-10-19 | 中国电子科技集团公司第五十四研究所 | A kind of method that embedded remote real time GPS common-view time compares |
CN109633700A (en) * | 2018-12-03 | 2019-04-16 | 天津津航计算技术研究所 | A kind of more GPS receiver time service precision test methods |
CN109633700B (en) * | 2018-12-03 | 2022-11-22 | 天津津航计算技术研究所 | Method for testing time service precision of multiple GPS receivers |
CN109508510A (en) * | 2018-12-20 | 2019-03-22 | 国网河南省电力公司焦作供电公司 | A kind of rubidium atomic clock parameter estimation algorithm based on improved Kalman filtering |
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